git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V8.1.1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 #ifndef __VFP_FP__\r
  75         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  76 #endif\r
  77 \r
  78 #ifndef configSYSTICK_CLOCK_HZ\r
  79         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  80         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  81         #define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )\r
  82 #else\r
  83         /* The way the SysTick is clocked is not modified in case it is not the same\r
  84         as the core. */\r
  85         #define portNVIC_SYSTICK_CLK_BIT        ( 0 )\r
  86 #endif\r
  87 \r
  88 /* Constants required to manipulate the core.  Registers first... */\r
  89 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  90 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  91 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  92 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  93 /* ...then bits in the registers. */\r
  94 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  95 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  96 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  97 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  98 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  99 \r
 100 #define portNVIC_PENDSV_PRI                                     ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 101 #define portNVIC_SYSTICK_PRI                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 102 \r
 103 /* Constants required to check the validity of an interrupt priority. */\r
 104 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 105 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 106 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 107 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 108 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 109 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 110 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 111 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 112 \r
 113 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
 114 #define portVECTACTIVE_MASK                                     ( 0x1FUL )\r
 115 \r
 116 /* Constants required to manipulate the VFP. */\r
 117 #define portFPCCR                                       ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
 118 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 119 \r
 120 /* Constants required to set up the initial stack. */\r
 121 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 122 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 123 \r
 124 /* The systick is a 24-bit counter. */\r
 125 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 126 \r
 127 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 128 occurred while the SysTick counter is stopped during tickless idle\r
 129 calculations. */\r
 130 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 131 \r
 132 /* Let the user override the pre-loading of the initial LR with the address of\r
 133 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 134 debugger. */\r
 135 #ifdef configTASK_RETURN_ADDRESS\r
 136         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 137 #else\r
 138         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 139 #endif\r
 140 \r
 141 /* Each task maintains its own interrupt status in the critical nesting\r
 142 variable. */\r
 143 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 144 \r
 145 /*\r
 146  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 147  * file is weak to allow application writers to change the timer used to\r
 148  * generate the tick interrupt.\r
 149  */\r
 150 void vPortSetupTimerInterrupt( void );\r
 151 \r
 152 /*\r
 153  * Exception handlers.\r
 154  */\r
 155 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 156 void xPortSysTickHandler( void );\r
 157 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 158 \r
 159 /*\r
 160  * Start first task is a separate function so it can be tested in isolation.\r
 161  */\r
 162 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 163 \r
 164 /*\r
 165  * Function to enable the VFP.\r
 166  */\r
 167  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 168 \r
 169 /*\r
 170  * Used to catch tasks that attempt to return from their implementing function.\r
 171  */\r
 172 static void prvTaskExitError( void );\r
 173 \r
 174 /*-----------------------------------------------------------*/\r
 175 \r
 176 /*\r
 177  * The number of SysTick increments that make up one tick period.\r
 178  */\r
 179 #if configUSE_TICKLESS_IDLE == 1\r
 180         static uint32_t ulTimerCountsForOneTick = 0;\r
 181 #endif /* configUSE_TICKLESS_IDLE */\r
 182 \r
 183 /*\r
 184  * The maximum number of tick periods that can be suppressed is limited by the\r
 185  * 24 bit resolution of the SysTick timer.\r
 186  */\r
 187 #if configUSE_TICKLESS_IDLE == 1\r
 188         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 189 #endif /* configUSE_TICKLESS_IDLE */\r
 190 \r
 191 /*\r
 192  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 193  * power functionality only.\r
 194  */\r
 195 #if configUSE_TICKLESS_IDLE == 1\r
 196         static uint32_t ulStoppedTimerCompensation = 0;\r
 197 #endif /* configUSE_TICKLESS_IDLE */\r
 198 \r
 199 /*\r
 200  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 201  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 202  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 203  */\r
 204 #if ( configASSERT_DEFINED == 1 )\r
 205          static uint8_t ucMaxSysCallPriority = 0;\r
 206          static uint32_t ulMaxPRIGROUPValue = 0;\r
 207          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 208 #endif /* configASSERT_DEFINED */\r
 209 \r
 210 /*-----------------------------------------------------------*/\r
 211 \r
 212 /*\r
 213  * See header file for description.\r
 214  */\r
 215 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 216 {\r
 217         /* Simulate the stack frame as it would be created by a context switch\r
 218         interrupt. */\r
 219 \r
 220         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 221         of interrupts, and to ensure alignment. */\r
 222         pxTopOfStack--;\r
 223 \r
 224         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 225         pxTopOfStack--;\r
 226         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 227         pxTopOfStack--;\r
 228         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 229 \r
 230         /* Save code space by skipping register initialisation. */\r
 231         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 232         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 233 \r
 234         /* A save method is being used that requires each task to maintain its\r
 235         own exec return value. */\r
 236         pxTopOfStack--;\r
 237         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 238 \r
 239         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 240 \r
 241         return pxTopOfStack;\r
 242 }\r
 243 /*-----------------------------------------------------------*/\r
 244 \r
 245 static void prvTaskExitError( void )\r
 246 {\r
 247         /* A function that implements a task must not exit or attempt to return to\r
 248         its caller as there is nothing to return to.  If a task wants to exit it\r
 249         should instead call vTaskDelete( NULL ).\r
 250 \r
 251         Artificially force an assert() to be triggered if configASSERT() is\r
 252         defined, then stop here so application writers can catch the error. */\r
 253         configASSERT( uxCriticalNesting == ~0UL );\r
 254         portDISABLE_INTERRUPTS();\r
 255         for( ;; );\r
 256 }\r
 257 /*-----------------------------------------------------------*/\r
 258 \r
 259 void vPortSVCHandler( void )\r
 260 {\r
 261         __asm volatile (\r
 262                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 263                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 264                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 265                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 266                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 267                                         "       isb                                                             \n"\r
 268                                         "       mov r0, #0                                              \n"\r
 269                                         "       msr     basepri, r0                                     \n"\r
 270                                         "       bx r14                                                  \n"\r
 271                                         "                                                                       \n"\r
 272                                         "       .align 2                                                \n"\r
 273                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 274                                 );\r
 275 }\r
 276 /*-----------------------------------------------------------*/\r
 277 \r
 278 static void prvPortStartFirstTask( void )\r
 279 {\r
 280         __asm volatile(\r
 281                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 282                                         " ldr r0, [r0]                  \n"\r
 283                                         " ldr r0, [r0]                  \n"\r
 284                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 285                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 286                                         " cpsie f                               \n"\r
 287                                         " dsb                                   \n"\r
 288                                         " isb                                   \n"\r
 289                                         " svc 0                                 \n" /* System call to start first task. */\r
 290                                         " nop                                   \n"\r
 291                                 );\r
 292 }\r
 293 /*-----------------------------------------------------------*/\r
 294 \r
 295 /*\r
 296  * See header file for description.\r
 297  */\r
 298 BaseType_t xPortStartScheduler( void )\r
 299 {\r
 300         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 301         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 302         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 303 \r
 304         #if( configASSERT_DEFINED == 1 )\r
 305         {\r
 306                 volatile uint32_t ulOriginalPriority;\r
 307                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 308                 volatile uint8_t ucMaxPriorityValue;\r
 309 \r
 310                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 311                 functions can be called.  ISR safe functions are those that end in\r
 312                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 313                 ensure interrupt entry is as fast and simple as possible.\r
 314 \r
 315                 Save the interrupt priority value that is about to be clobbered. */\r
 316                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 317 \r
 318                 /* Determine the number of priority bits available.  First write to all\r
 319                 possible bits. */\r
 320                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 321 \r
 322                 /* Read the value back to see how many bits stuck. */\r
 323                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 324 \r
 325                 /* Use the same mask on the maximum system call priority. */\r
 326                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 327 \r
 328                 /* Calculate the maximum acceptable priority group value for the number\r
 329                 of bits read back. */\r
 330                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 331                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 332                 {\r
 333                         ulMaxPRIGROUPValue--;\r
 334                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 335                 }\r
 336 \r
 337                 /* Shift the priority group value back to its position within the AIRCR\r
 338                 register. */\r
 339                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 340                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 341 \r
 342                 /* Restore the clobbered interrupt priority register to its original\r
 343                 value. */\r
 344                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 345         }\r
 346         #endif /* conifgASSERT_DEFINED */\r
 347 \r
 348         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 349         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 350         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 351 \r
 352         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 353         here already. */\r
 354         vPortSetupTimerInterrupt();\r
 355 \r
 356         /* Initialise the critical nesting count ready for the first task. */\r
 357         uxCriticalNesting = 0;\r
 358 \r
 359         /* Ensure the VFP is enabled - it should be anyway. */\r
 360         vPortEnableVFP();\r
 361 \r
 362         /* Lazy save always. */\r
 363         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 364 \r
 365         /* Start the first task. */\r
 366         prvPortStartFirstTask();\r
 367 \r
 368         /* Should never get here as the tasks will now be executing!  Call the task\r
 369         exit error function to prevent compiler warnings about a static function\r
 370         not being called in the case that the application writer overrides this\r
 371         functionality by defining configTASK_RETURN_ADDRESS. */\r
 372         prvTaskExitError();\r
 373 \r
 374         /* Should not get here! */\r
 375         return 0;\r
 376 }\r
 377 /*-----------------------------------------------------------*/\r
 378 \r
 379 void vPortEndScheduler( void )\r
 380 {\r
 381         /* Not implemented in ports where there is nothing to return to.\r
 382         Artificially force an assert. */\r
 383         configASSERT( uxCriticalNesting == 1000UL );\r
 384 }\r
 385 /*-----------------------------------------------------------*/\r
 386 \r
 387 void vPortYield( void )\r
 388 {\r
 389         /* Set a PendSV to request a context switch. */\r
 390         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 391 \r
 392         /* Barriers are normally not required but do ensure the code is completely\r
 393         within the specified behaviour for the architecture. */\r
 394         __asm volatile( "dsb" );\r
 395         __asm volatile( "isb" );\r
 396 }\r
 397 /*-----------------------------------------------------------*/\r
 398 \r
 399 void vPortEnterCritical( void )\r
 400 {\r
 401         portDISABLE_INTERRUPTS();\r
 402         uxCriticalNesting++;\r
 403         __asm volatile( "dsb" );\r
 404         __asm volatile( "isb" );\r
 405         \r
 406         /* This is not the interrupt safe version of the enter critical function so\r
 407         assert() if it is being called from an interrupt context.  Only API \r
 408         functions that end in "FromISR" can be used in an interrupt.  Only assert if\r
 409         the critical nesting count is 1 to protect against recursive calls if the\r
 410         assert function also uses a critical section. */\r
 411         if( uxCriticalNesting == 1 )\r
 412         {\r
 413                 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
 414         }\r
 415 }\r
 416 /*-----------------------------------------------------------*/\r
 417 \r
 418 void vPortExitCritical( void )\r
 419 {\r
 420         configASSERT( uxCriticalNesting );\r
 421         uxCriticalNesting--;\r
 422         if( uxCriticalNesting == 0 )\r
 423         {\r
 424                 portENABLE_INTERRUPTS();\r
 425         }\r
 426 }\r
 427 /*-----------------------------------------------------------*/\r
 428 \r
 429 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
 430 {\r
 431         __asm volatile                                                                                                          \\r
 432         (                                                                                                                                       \\r
 433                 "       mrs r0, basepri                                                                                 \n" \\r
 434                 "       mov r1, %0                                                                                              \n"     \\r
 435                 "       msr basepri, r1                                                                                 \n" \\r
 436                 "       bx lr                                                                                                   \n" \\r
 437                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 438         );\r
 439 \r
 440         /* This return will not be reached but is necessary to prevent compiler\r
 441         warnings. */\r
 442         return 0;\r
 443 }\r
 444 /*-----------------------------------------------------------*/\r
 445 \r
 446 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
 447 {\r
 448         __asm volatile                                                                                                  \\r
 449         (                                                                                                                               \\r
 450                 "       msr basepri, r0                                                                         \n"     \\r
 451                 "       bx lr                                                                                           \n" \\r
 452                 :::"r0"                                                                                                         \\r
 453         );\r
 454 \r
 455         /* Just to avoid compiler warnings. */\r
 456         ( void ) ulNewMaskValue;\r
 457 }\r
 458 /*-----------------------------------------------------------*/\r
 459 \r
 460 void xPortPendSVHandler( void )\r
 461 {\r
 462         /* This is a naked function. */\r
 463 \r
 464         __asm volatile\r
 465         (\r
 466         "       mrs r0, psp                                                     \n"\r
 467         "       isb                                                                     \n"\r
 468         "                                                                               \n"\r
 469         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 470         "       ldr     r2, [r3]                                                \n"\r
 471         "                                                                               \n"\r
 472         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 473         "       it eq                                                           \n"\r
 474         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 475         "                                                                               \n"\r
 476         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 477         "                                                                               \n"\r
 478         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 479         "                                                                               \n"\r
 480         "       stmdb sp!, {r3}                                         \n"\r
 481         "       mov r0, %0                                                      \n"\r
 482         "       msr basepri, r0                                         \n"\r
 483         "       bl vTaskSwitchContext                           \n"\r
 484         "       mov r0, #0                                                      \n"\r
 485         "       msr basepri, r0                                         \n"\r
 486         "       ldmia sp!, {r3}                                         \n"\r
 487         "                                                                               \n"\r
 488         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 489         "       ldr r0, [r1]                                            \n"\r
 490         "                                                                               \n"\r
 491         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 492         "                                                                               \n"\r
 493         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 494         "       it eq                                                           \n"\r
 495         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 496         "                                                                               \n"\r
 497         "       msr psp, r0                                                     \n"\r
 498         "       isb                                                                     \n"\r
 499         "                                                                               \n"\r
 500         #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r
 501                 #if WORKAROUND_PMU_CM001 == 1\r
 502         "                       push { r14 }                            \n"\r
 503         "                       pop { pc }                                      \n"\r
 504                 #endif\r
 505         #endif\r
 506         "                                                                               \n"\r
 507         "       bx r14                                                          \n"\r
 508         "                                                                               \n"\r
 509         "       .align 2                                                        \n"\r
 510         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 511         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 512         );\r
 513 }\r
 514 /*-----------------------------------------------------------*/\r
 515 \r
 516 void xPortSysTickHandler( void )\r
 517 {\r
 518         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 519         executes all interrupts must be unmasked.  There is therefore no need to\r
 520         save and then restore the interrupt mask value as its value is already\r
 521         known. */\r
 522         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 523         {\r
 524                 /* Increment the RTOS tick. */\r
 525                 if( xTaskIncrementTick() != pdFALSE )\r
 526                 {\r
 527                         /* A context switch is required.  Context switching is performed in\r
 528                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 529                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 530                 }\r
 531         }\r
 532         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 533 }\r
 534 /*-----------------------------------------------------------*/\r
 535 \r
 536 #if configUSE_TICKLESS_IDLE == 1\r
 537 \r
 538         __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 539         {\r
 540         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
 541         TickType_t xModifiableIdleTime;\r
 542 \r
 543                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 544                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 545                 {\r
 546                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 547                 }\r
 548 \r
 549                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 550                 is accounted for as best it can be, but using the tickless mode will\r
 551                 inevitably result in some tiny drift of the time maintained by the\r
 552                 kernel with respect to calendar time. */\r
 553                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 554 \r
 555                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 556                 tick periods.  -1 is used because this code will execute part way\r
 557                 through one of the tick periods. */\r
 558                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 559                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 560                 {\r
 561                         ulReloadValue -= ulStoppedTimerCompensation;\r
 562                 }\r
 563 \r
 564                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 565                 method as that will mask interrupts that should exit sleep mode. */\r
 566                 __asm volatile( "cpsid i" );\r
 567 \r
 568                 /* If a context switch is pending or a task is waiting for the scheduler\r
 569                 to be unsuspended then abandon the low power entry. */\r
 570                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 571                 {\r
 572                         /* Restart from whatever is left in the count register to complete\r
 573                         this tick period. */\r
 574                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 575 \r
 576                         /* Restart SysTick. */\r
 577                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 578 \r
 579                         /* Reset the reload register to the value required for normal tick\r
 580                         periods. */\r
 581                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 582 \r
 583                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 584                         above. */\r
 585                         __asm volatile( "cpsie i" );\r
 586                 }\r
 587                 else\r
 588                 {\r
 589                         /* Set the new reload value. */\r
 590                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 591 \r
 592                         /* Clear the SysTick count flag and set the count value back to\r
 593                         zero. */\r
 594                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 595 \r
 596                         /* Restart SysTick. */\r
 597                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 598 \r
 599                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 600                         set its parameter to 0 to indicate that its implementation contains\r
 601                         its own wait for interrupt or wait for event instruction, and so wfi\r
 602                         should not be executed again.  However, the original expected idle\r
 603                         time variable must remain unmodified, so a copy is taken. */\r
 604                         xModifiableIdleTime = xExpectedIdleTime;\r
 605                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 606                         if( xModifiableIdleTime > 0 )\r
 607                         {\r
 608                                 __asm volatile( "dsb" );\r
 609                                 __asm volatile( "wfi" );\r
 610                                 __asm volatile( "isb" );\r
 611                         }\r
 612                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 613 \r
 614                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 615                         accounted for as best it can be, but using the tickless mode will\r
 616                         inevitably result in some tiny drift of the time maintained by the\r
 617                         kernel with respect to calendar time. */\r
 618                         ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
 619                         portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
 620 \r
 621                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 622                         above. */\r
 623                         __asm volatile( "cpsie i" );\r
 624 \r
 625                         if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 626                         {\r
 627                                 uint32_t ulCalculatedLoadValue;\r
 628 \r
 629                                 /* The tick interrupt has already executed, and the SysTick\r
 630                                 count reloaded with ulReloadValue.  Reset the\r
 631                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 632                                 period. */\r
 633                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 634 \r
 635                                 /* Don't allow a tiny value, or values that have somehow\r
 636                                 underflowed because the post sleep hook did something\r
 637                                 that took too long. */\r
 638                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 639                                 {\r
 640                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 641                                 }\r
 642 \r
 643                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 644 \r
 645                                 /* The tick interrupt handler will already have pended the tick\r
 646                                 processing in the kernel.  As the pending tick will be\r
 647                                 processed as soon as this function exits, the tick value\r
 648                                 maintained by the tick is stepped forward by one less than the\r
 649                                 time spent waiting. */\r
 650                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 651                         }\r
 652                         else\r
 653                         {\r
 654                                 /* Something other than the tick interrupt ended the sleep.\r
 655                                 Work out how long the sleep lasted rounded to complete tick\r
 656                                 periods (not the ulReload value which accounted for part\r
 657                                 ticks). */\r
 658                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 659 \r
 660                                 /* How many complete tick periods passed while the processor\r
 661                                 was waiting? */\r
 662                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 663 \r
 664                                 /* The reload value is set to whatever fraction of a single tick\r
 665                                 period remains. */\r
 666                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 667                         }\r
 668 \r
 669                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 670                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 671                         value.  The critical section is used to ensure the tick interrupt\r
 672                         can only execute once in the case that the reload register is near\r
 673                         zero. */\r
 674                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 675                         portENTER_CRITICAL();\r
 676                         {\r
 677                                 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 678                                 vTaskStepTick( ulCompleteTickPeriods );\r
 679                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 680                         }\r
 681                         portEXIT_CRITICAL();\r
 682                 }\r
 683         }\r
 684 \r
 685 #endif /* #if configUSE_TICKLESS_IDLE */\r
 686 /*-----------------------------------------------------------*/\r
 687 \r
 688 /*\r
 689  * Setup the systick timer to generate the tick interrupts at the required\r
 690  * frequency.\r
 691  */\r
 692 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 693 {\r
 694         /* Calculate the constants required to configure the tick interrupt. */\r
 695         #if configUSE_TICKLESS_IDLE == 1\r
 696         {\r
 697                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 698                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 699                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 700         }\r
 701         #endif /* configUSE_TICKLESS_IDLE */\r
 702 \r
 703         /* Configure SysTick to interrupt at the requested rate. */\r
 704         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 705         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
 706 }\r
 707 /*-----------------------------------------------------------*/\r
 708 \r
 709 /* This is a naked function. */\r
 710 static void vPortEnableVFP( void )\r
 711 {\r
 712         __asm volatile\r
 713         (\r
 714                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 715                 "       ldr r1, [r0]                            \n"\r
 716                 "                                                               \n"\r
 717                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 718                 "       str r1, [r0]                            \n"\r
 719                 "       bx r14                                          "\r
 720         );\r
 721 }\r
 722 /*-----------------------------------------------------------*/\r
 723 \r
 724 #if( configASSERT_DEFINED == 1 )\r
 725 \r
 726         void vPortValidateInterruptPriority( void )\r
 727         {\r
 728         uint32_t ulCurrentInterrupt;\r
 729         uint8_t ucCurrentPriority;\r
 730 \r
 731                 /* Obtain the number of the currently executing interrupt. */\r
 732                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 733 \r
 734                 /* Is the interrupt number a user defined interrupt? */\r
 735                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 736                 {\r
 737                         /* Look up the interrupt's priority. */\r
 738                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 739 \r
 740                         /* The following assertion will fail if a service routine (ISR) for\r
 741                         an interrupt that has been assigned a priority above\r
 742                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 743                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 744                         from interrupts that have been assigned a priority at or below\r
 745                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 746 \r
 747                         Numerically low interrupt priority numbers represent logically high\r
 748                         interrupt priorities, therefore the priority of the interrupt must\r
 749                         be set to a value equal to or numerically *higher* than\r
 750                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 751 \r
 752                         Interrupts that use the FreeRTOS API must not be left at their\r
 753                         default priority of     zero as that is the highest possible priority,\r
 754                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 755                         and     therefore also guaranteed to be invalid.\r
 756 \r
 757                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 758                         interrupt entry is as fast and simple as possible.\r
 759 \r
 760                         The following links provide detailed information:\r
 761                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 762                         http://www.freertos.org/FAQHelp.html */\r
 763                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 764                 }\r
 765 \r
 766                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 767                 that define each interrupt's priority to be split between bits that\r
 768                 define the interrupt's pre-emption priority bits and bits that define\r
 769                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 770                 to be pre-emption priority bits.  The following assertion will fail if\r
 771                 this is not the case (if some bits represent a sub-priority).\r
 772 \r
 773                 If the application only uses CMSIS libraries for interrupt\r
 774                 configuration then the correct setting can be achieved on all Cortex-M\r
 775                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 776                 scheduler.  Note however that some vendor specific peripheral libraries\r
 777                 assume a non-zero priority group setting, in which cases using a value\r
 778                 of zero will result in unpredicable behaviour. */\r
 779                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 780         }\r
 781 \r
 782 #endif /* configASSERT_DEFINED */\r
 783 \r
 784 \r