+/*\r
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license\r
+ and contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
+ the code with commercial support, indemnification, and middleware, under\r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under\r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * This file implements functions to access and manipulate the PIC32 hardware\r
+ * without reliance on third party library functions that may be liable to\r
+ * change.\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo includes. */\r
+#include "ConfigPerformance.h"\r
+\r
+/* Hardware specific definitions. */\r
+#define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )\r
+#define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )\r
+#define hwMAX_FLASH_SPEED ( 30000000UL )\r
+#define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )\r
+#define hwUNLOCK_KEY_0 ( 0xAA996655UL )\r
+#define hwUNLOCK_KEY_1 ( 0x556699AAUL )\r
+#define hwLOCK_KEY ( 0x33333333UL )\r
+#define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )\r
+#define hwBEV_BIT ( 0x00400000 )\r
+#define hwEXL_BIT ( 0x00000002 )\r
+#define hwIV_BIT ( 0x00800000 )\r
+\r
+/*\r
+ * Set the flash wait states for the configured CPU clock speed.\r
+ */\r
+static void prvConfigureWaitStates( void );\r
+\r
+/*\r
+ * Use a divisor of 2 on the peripheral bus.\r
+ */\r
+static void prvConfigurePeripheralBus( void );\r
+\r
+/*\r
+ * Enable the cache.\r
+ */\r
+static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vHardwareConfigurePerformance( void )\r
+{\r
+unsigned long ulStatus;\r
+#ifdef _PCACHE\r
+ unsigned long ulCacheStatus;\r
+#endif\r
+\r
+ /* Disable interrupts - not taskDISABLE_INTERRUPTS() cannot be used here as\r
+ FreeRTOS does not globally disable interrupt. */\r
+ ulStatus = _CP0_GET_STATUS();\r
+ _CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );\r
+\r
+ prvConfigurePeripheralBus();\r
+ prvConfigureWaitStates();\r
+\r
+ /* Disable DRM wait state. */\r
+ BMXCONCLR = _BMXCON_BMXWSDRM_MASK;\r
+\r
+ #ifdef _PCACHE\r
+ {\r
+ /* Read the current CHECON value. */\r
+ ulCacheStatus = CHECON;\r
+\r
+ /* All the PREFEN bits are being set, so no need to clear first. */\r
+ ulCacheStatus |= hwCHECON_PREFEN_BITS;\r
+\r
+ /* Write back the new value. */\r
+ CHECON = ulCacheStatus;\r
+ prvKSeg0CacheOn();\r
+ }\r
+ #endif\r
+\r
+ /* Reset the status register back to its original value so the original\r
+ interrupt enable status is retored. */\r
+ _CP0_SET_STATUS( ulStatus );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vHardwareUseMultiVectoredInterrupts( void )\r
+{\r
+unsigned long ulStatus, ulCause;\r
+extern unsigned long _ebase_address[];\r
+\r
+ /* Get current status. */\r
+ ulStatus = _CP0_GET_STATUS();\r
+\r
+ /* Disable interrupts. */\r
+ ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;\r
+\r
+ /* Set BEV bit. */\r
+ ulStatus |= hwBEV_BIT;\r
+\r
+ /* Write status back. */\r
+ _CP0_SET_STATUS( ulStatus );\r
+\r
+ /* Setup EBase. */\r
+ _CP0_SET_EBASE( ( unsigned long ) _ebase_address );\r
+ \r
+ /* Space vectors by 0x20 bytes. */\r
+ _CP0_XCH_INTCTL( 0x20 );\r
+\r
+ /* Set the IV bit in the CAUSE register. */\r
+ ulCause = _CP0_GET_CAUSE();\r
+ ulCause |= hwIV_BIT;\r
+ _CP0_SET_CAUSE( ulCause );\r
+\r
+ /* Clear BEV and EXL bits in status. */\r
+ ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );\r
+ _CP0_SET_STATUS( ulStatus );\r
+\r
+ /* Set MVEC bit. */\r
+ INTCONbits.MVEC = 1;\r
+ \r
+ /* Finally enable interrupts again. */\r
+ ulStatus |= hwGLOBAL_INTERRUPT_BIT;\r
+ _CP0_SET_STATUS( ulStatus );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvConfigurePeripheralBus( void )\r
+{\r
+unsigned long ulDMAStatus;\r
+__OSCCONbits_t xOSCCONBits;\r
+\r
+ /* Unlock after suspending. */\r
+ ulDMAStatus = DMACONbits.SUSPEND;\r
+ if( ulDMAStatus == 0 )\r
+ {\r
+ DMACONSET = _DMACON_SUSPEND_MASK;\r
+\r
+ /* Wait until actually suspended. */\r
+ while( DMACONbits.SUSPEND == 0 );\r
+ }\r
+\r
+ SYSKEY = 0;\r
+ SYSKEY = hwUNLOCK_KEY_0;\r
+ SYSKEY = hwUNLOCK_KEY_1;\r
+\r
+ /* Read to start in sync. */\r
+ xOSCCONBits.w = OSCCON;\r
+ xOSCCONBits.PBDIV = 0;\r
+ xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;\r
+\r
+ /* Write back. */\r
+ OSCCON = xOSCCONBits.w;\r
+\r
+ /* Ensure the write occurred. */\r
+ xOSCCONBits.w = OSCCON;\r
+\r
+ /* Lock again. */\r
+ SYSKEY = hwLOCK_KEY;\r
+\r
+ /* Resume DMA activity. */\r
+ if( ulDMAStatus == 0 )\r
+ {\r
+ DMACONCLR=_DMACON_SUSPEND_MASK;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvConfigureWaitStates( void )\r
+{\r
+unsigned long ulInterruptStatus, ulSystemClock = configCPU_CLOCK_HZ - 1;\r
+unsigned long ulWaitStates, ulCHECONVal;\r
+\r
+ /* 1 wait state for every hwMAX_FLASH_SPEED MHz. */\r
+ ulWaitStates = 0;\r
+\r
+ while( ulSystemClock > hwMAX_FLASH_SPEED )\r
+ {\r
+ ulWaitStates++;\r
+ ulSystemClock -= hwMAX_FLASH_SPEED;\r
+ }\r
+\r
+ /* Obtain current CHECON value. */\r
+ ulCHECONVal = CHECON;\r
+\r
+ /* Clear the wait state bits, then set the calculated wait state bits. */\r
+ ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;\r
+ ulCHECONVal |= ulWaitStates;\r
+\r
+ /* Write back the new value. */\r
+ CHECON = ulWaitStates;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )\r
+{\r
+unsigned long ulValue;\r
+\r
+ __asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );\r
+ ulValue = ( ulValue & ~0x07) | 0x03;\r
+ __asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );\r
+}\r
+\r
+\r