Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:

- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2284 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
index 965d304f55a0fd2cc9a5e59b4b230d6341919aa0..81e16b4cd62279cbb55db8f44d0016f9ca97535a 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -139,10 +139,6 @@ uint32_t ulPortInterruptNesting = 0UL;
 \r
 /*-----------------------------------------------------------*/\r
 \r
-#warning What about branch distance in asm file.\r
-#warning Does not support flop use in ISRs.\r
-#warning Level interrupts must be cleared in their handling function.\r
-\r
 /*\r
  * See header file for description.\r
  */\r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
index fe6c74579e6a76fcccd10e7d46dcbc3512f04857..8aa8a12cd2ef1d4214fee905699b729c9ae6b458 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -99,9 +99,6 @@ portSAVE_CONTEXT macro
 \r
 portRESTORE_CONTEXT macro\r
 \r
-       ; Switch to system mode\r
-       CPS             #SYS_MODE\r
-\r
        ; Set the SP to point to the stack of the task being restored.\r
        LDR             R0, =pxCurrentTCB\r
        LDR             R1, [R0]\r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
index c66146964e3981eb5de7f63e48a2687a4b3ca5cd..1bfca7fc2b4ecec616811668f4d1eb18a16a6053 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -73,7 +73,7 @@ IRQ_MODE                      EQU             0x12
        INCLUDE portASM.h\r
 \r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-; SVC handler is used to start the scheduler and yield a task.\r
+; SVC handler is used to yield a task.\r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 FreeRTOS_SWI_Handler\r
 \r
@@ -83,11 +83,16 @@ FreeRTOS_SWI_Handler
        portSAVE_CONTEXT\r
        LDR R0, =vTaskSwitchContext\r
        BLX     R0\r
+       portRESTORE_CONTEXT\r
 \r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+; vPortRestoreTaskContext is used to start the scheduler.\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 vPortRestoreTaskContext\r
+       ; Switch to system mode\r
+       CPS             #SYS_MODE\r
        portRESTORE_CONTEXT\r
 \r
-\r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
 ; IRQ interrupt handler used when individual priorities cannot be masked\r
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
@@ -121,11 +126,14 @@ FreeRTOS_IRQ_Handler
        AND             r2, r2, #4\r
        SUB             sp, sp, r2\r
 \r
-       ; Call the interrupt handler\r
+       ; Obtain the address of the interrupt handler, then call it.\r
        PUSH    {r0-r3, lr}\r
        LDR             r1, =configINTERRUPT_VECTOR_ADDRESS\r
        LDR             r0, [r1]\r
-       STR             r1, [r1] ; Write to IVR in case protect mode is being used.\r
+       STR             r1, [r1] ; [SAMA5] Write to IVR in case protect mode is being used.\r
+       DSB\r
+       ISB\r
+       CPSIE   i\r
        BLX             r0\r
        POP             {r0-r3, lr}\r
        ADD             sp, sp, r2\r

diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
index ce6b83c09eb84e61f629bef844485a67c8984655..8db2506ca872f72ff31cbdc56c4437f5615af4e3 100644 (file)
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -124,7 +124,7 @@
        }\r
 \r
        #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-       #define portYIELD() __asm( "SWI 0" );\r
+       #define portYIELD() __asm( "SWI 0" ); __ISB()\r
 \r
 \r
        /*-----------------------------------------------------------\r
@@ -138,9 +138,9 @@
 \r
        #define portENTER_CRITICAL()            vPortEnterCritical();\r
        #define portEXIT_CRITICAL()                     vPortExitCritical();\r
-       #define portDISABLE_INTERRUPTS()        __disable_irq() /* No priority mask register so global disable is used. */\r
+       #define portDISABLE_INTERRUPTS()        __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */\r
        #define portENABLE_INTERRUPTS()         __enable_irq()\r
-       #define portSET_INTERRUPT_MASK_FROM_ISR()               __get_interrupt_state()\r
+       #define portSET_INTERRUPT_MASK_FROM_ISR()               __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */\r
        #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    __set_interrupt_state(x)\r
 \r
        /*-----------------------------------------------------------*/\r