<tool id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base.1942793763" name="GNU ARM C Linker" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.base">\r
<option id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.nostdlibs.1238746537" name="No startup or default libs (-nostdlib)" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.nostdlibs" value="false" valueType="boolean"/>\r
<option id="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.printffloat.1689266799" name="Printf float" superClass="com.silabs.ide.si32.gcc.cdt.managedbuild.tool.gnu.c.linker.printffloat" value="true" valueType="boolean"/>\r
- <option id="gnu.c.link.option.libs.1846704343" name="Libraries (-l)" superClass="gnu.c.link.option.libs" valueType="libs"/>\r
+ <option id="gnu.c.link.option.libs.1846704343" name="Libraries (-l)" superClass="gnu.c.link.option.libs"/>\r
<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.301647948" superClass="cdt.managedbuild.tool.gnu.c.linker.input">\r
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
<additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
</toolChain>\r
</folderInfo>\r
<sourceEntries>\r
- <entry excluding="Source/RTT|Source/SilLabs_Code/kits/bsp/bsp_dk_mcuboard.c|Source/SilLabs_Code/kits/bsp/bsp_dk_leds.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3201.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3200.c|Source/SilLabs_Code/kits/bsp/bsp_bcc.c|Source/SilLabs_Code/Device/SiliconLabs/EFM32GG/Source|CMSIS/efm32gg/startup_iar_efm32gg.s|FreeRTOS/efm32gg/port_iar.c|FreeRTOS/efm32gg/portasm.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
+ <entry excluding="Source/low_power_tick_management.c|Source/RTT|Source/SilLabs_Code/kits/bsp/bsp_dk_mcuboard.c|Source/SilLabs_Code/kits/bsp/bsp_dk_leds.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3201.c|Source/SilLabs_Code/kits/bsp/bsp_dk_3200.c|Source/SilLabs_Code/kits/bsp/bsp_bcc.c|Source/SilLabs_Code/Device/SiliconLabs/EFM32GG/Source|CMSIS/efm32gg/startup_iar_efm32gg.s|FreeRTOS/efm32gg/port_iar.c|FreeRTOS/efm32gg/portasm.s" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
</sourceEntries>\r
</configuration>\r
</storageModule>\r
/*\r
- * FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
- *\r
- * FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT\r
- * http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
- *\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS tutorial books are available in pdf and paperback. *\r
- * Complete, revised, and edited pdf reference manuals are also *\r
- * available. *\r
- * *\r
- * Purchasing FreeRTOS documentation will not only help you, by *\r
- * ensuring you get running as quickly as possible and with an *\r
- * in-depth knowledge of how to use FreeRTOS, it will also help *\r
- * the FreeRTOS project to continue with its mission of providing *\r
- * professional grade, cross platform, de facto standard solutions *\r
- * for microcontrollers - completely free of charge! *\r
- * *\r
- * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
- * *\r
- * Thank you for using FreeRTOS, and thank you for your support! *\r
- * *\r
- ***************************************************************************\r
- *\r
- *\r
- * This file is part of the FreeRTOS distribution.\r
- *\r
- * FreeRTOS is free software; you can redistribute it and/or modify it under\r
- * the terms of the GNU General Public License (version 2) as published by the\r
- * Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
- *\r
- * >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
- * distribute a combined work that includes FreeRTOS without being obliged to\r
- * provide the source code for proprietary components outside of the FreeRTOS\r
- * kernel.\r
- *\r
- * FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\r
- * details. You should have received a copy of the GNU General Public License\r
- * and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
- * viewed here: http://www.freertos.org/a00114.html and also obtained by\r
- * writing to Real Time Engineers Ltd., contact details for whom are available\r
- * on the FreeRTOS WEB site.\r
- *\r
- * 1 tab == 4 spaces!\r
- *\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
- *\r
- *\r
- * http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- * license and Real Time Engineers Ltd. contact details.\r
- *\r
- * http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- * including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
- * fully thread aware and reentrant UDP/IP stack.\r
- *\r
- * http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- * Integrity Systems, who sell the code with commercial support,\r
- * indemnification and middleware, under the OpenRTOS brand.\r
- *\r
- * http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- * engineered and independently SIL3 certified version for use in safety and\r
- * mission critical applications that require provable dependability.\r
- */\r
+ FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.\r
+ All rights reserved\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
+\r
+ ***************************************************************************\r
+ >>! NOTE: The modification to the GPL is included to allow you to !<<\r
+ >>! distribute a combined work that includes FreeRTOS without being !<<\r
+ >>! obliged to provide the source code for proprietary components !<<\r
+ >>! outside of the FreeRTOS kernel. !<<\r
+ ***************************************************************************\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available on the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that is more than just the market leader, it *\r
+ * is the industry's de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly while simultaneously helping *\r
+ * to support the FreeRTOS project by purchasing a FreeRTOS *\r
+ * tutorial book, reference manual, or both: *\r
+ * http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading\r
+ the FAQ page "My application does not run, what could be wrong?". Have you\r
+ defined configASSERT()?\r
+\r
+ http://www.FreeRTOS.org/support - In return for receiving this top quality\r
+ embedded software for free we request you assist our global community by\r
+ participating in the support forum.\r
+\r
+ http://www.FreeRTOS.org/training - Investing in training allows your team to\r
+ be as productive as possible as early as possible. Now you can receive\r
+ FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
+ Ltd, and the world's leading authority on the world's leading RTOS.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
+ Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
+ Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and commercial middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
\r
#ifndef FREERTOS_CONFIG_H\r
#define FREERTOS_CONFIG_H\r
\r
-#include "em_assert.h"\r
-\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
-/********************** Configuration of FreeRTOS ****************************/\r
-\r
-/* Implement FreeRTOS configASSERT as emlib assert */\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* Modes of operations of operation system*/\r
-#define configUSE_PREEMPTION ( 1 )\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
\r
-/* Energy saving modes */\r
-#define configUSE_TICKLESS_IDLE ( 0 )\r
/* Available options when configUSE_TICKLESS_IDLE set to 1\r
* or configUSE_SLEEP_MODE_IN_IDLE set to 1 :\r
* 1 - EM1, 2 - EM2, 3 - EM3, timer in EM3 is not very accurate*/\r
-#define configSLEEP_MODE ( 2 )\r
-\r
-/* Definition used only if configUSE_TICKLESS_IDLE == 0 */\r
-#define configUSE_SLEEP_MODE_IN_IDLE ( 0 )\r
-\r
-\r
-/* EM1 use systick as system clock*/\r
-/* EM2 use crystal 32768Hz and RTC Component as system clock\r
- * We use 2 times divider of this clock to reduce energy consumtion\r
- * You can also in this mode choose crystal oscillator to get more preccision in\r
- * time measurement or RC oscillator for more energy reduction.*/\r
-/* EM3 use 2kHz RC and BURTC Component as system clock*/\r
-#if ( ( configSLEEP_MODE == 2 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )\r
-/* Choose source of clock for RTC (system tick)\r
- * if configCRYSTAL_IN_EM2 set to 1 then Crystal oscillator is used,\r
- * when 0 RC oscillator */\r
-#define configCRYSTAL_IN_EM2 ( 1 )\r
-#endif\r
-#if ( (configSLEEP_MODE == 2 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )\r
-/* When we use EM2 or EM3 System clock has got low frequency,\r
- * so we reduce Tick rate to 100 Hz and 40 Hz, which give more clock cycles between ticks*/\r
-#define configTICK_RATE_HZ ( 100 )\r
-#elif ( ( configSLEEP_MODE == 3 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )\r
-#define configTICK_RATE_HZ ( 40 )\r
-#else\r
-#define configTICK_RATE_HZ ( 1000 )\r
-#endif\r
-\r
-/* Definition used by Keil to replace default system clock source when we use EM2 or EM3 mode. */\r
-#if ( ( configSLEEP_MODE == 2 || configSLEEP_MODE == 3 ) && ( configUSE_TICKLESS_IDLE == 1 || configUSE_SLEEP_MODE_IN_IDLE == 1 ) )\r
-#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION ( 1 )\r
-#endif\r
+#define configSLEEP_MODE ( 2 )\r
\r
/* Main functions*/\r
-#define configMAX_PRIORITIES ( 6 )\r
+#define configUSE_PREEMPTION ( 1 )\r
+#define configUSE_TICKLESS_IDLE ( 1 )\r
#define configUSE_PORT_OPTIMISED_TASK_SELECTION ( 1 )\r
-#define configMINIMAL_STACK_SIZE (( unsigned short ) 140)\r
-#define configTOTAL_HEAP_SIZE (( size_t )(40000))\r
-#define configMAX_TASK_NAME_LEN ( 10 )\r
-#define configUSE_TRACE_FACILITY ( 0 )\r
-#define configUSE_16_BIT_TICKS ( 0 )\r
-#define configIDLE_SHOULD_YIELD ( 0 )\r
-#define configUSE_MUTEXES ( 1 )\r
-#define configUSE_RECURSIVE_MUTEXES ( 1 )\r
-#define configUSE_COUNTING_SEMAPHORES ( 1 )\r
-#define configUSE_ALTERNATIVE_API ( 0 )/* Deprecated! */\r
-#define configQUEUE_REGISTRY_SIZE ( 10 )\r
-#define configUSE_QUEUE_SETS ( 0 )\r
+#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)\r
+#define configMAX_PRIORITIES ( 6 )\r
+#define configTICK_RATE_HZ ( 1000 )\r
+#define configMINIMAL_STACK_SIZE (( unsigned short ) 140)\r
+#define configTOTAL_HEAP_SIZE (( size_t )(40000))\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY ( 0 )\r
+#define configUSE_16_BIT_TICKS ( 0 )\r
+#define configIDLE_SHOULD_YIELD ( 0 )\r
+#define configUSE_MUTEXES ( 1 )\r
+#define configUSE_RECURSIVE_MUTEXES ( 1 )\r
+#define configUSE_COUNTING_SEMAPHORES ( 1 )\r
+#define configUSE_ALTERNATIVE_API ( 0 )/* Deprecated! */\r
+#define configQUEUE_REGISTRY_SIZE ( 10 )\r
+#define configUSE_QUEUE_SETS ( 0 )\r
\r
/* Hook function related definitions. */\r
-#define configUSE_TICK_HOOK ( 1 )\r
-#define configCHECK_FOR_STACK_OVERFLOW ( 2 )\r
-#define configUSE_MALLOC_FAILED_HOOK ( 1 )\r
+#define configUSE_TICK_HOOK ( 1 )\r
+#define configCHECK_FOR_STACK_OVERFLOW ( 2 )\r
+#define configUSE_MALLOC_FAILED_HOOK ( 1 )\r
+#define configUSE_IDLE_HOOK ( 1 )\r
\r
/* Run time stats gathering related definitions. */\r
-#define configGENERATE_RUN_TIME_STATS ( 0 )\r
+#define configGENERATE_RUN_TIME_STATS ( 0 )\r
\r
/* Co-routine related definitions. */\r
-#define configUSE_CO_ROUTINES ( 0 )\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 1 )\r
+#define configUSE_CO_ROUTINES ( 0 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 1 )\r
\r
/* Software timer related definitions. */\r
-#define configUSE_TIMERS ( 1 )\r
-#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* Highest priority */\r
-#define configTIMER_QUEUE_LENGTH ( 10 )\r
-#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+#define configUSE_TIMERS ( 1 )\r
+#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) /* Highest priority */\r
+#define configTIMER_QUEUE_LENGTH ( 10 )\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
\r
/* Interrupt nesting behaviour configuration. */\r
-#define configKERNEL_INTERRUPT_PRIORITY ( 255 )\r
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 191 ) /* equivalent to 0xa0, or priority 5. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( 255 )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 191 ) /* equivalent to 0xa0, or priority 5. */\r
\r
/* Optional functions - most linkers will remove unused functions anyway. */\r
-#define INCLUDE_vTaskPrioritySet ( 1 )\r
-#define INCLUDE_uxTaskPriorityGet ( 1 )\r
-#define INCLUDE_vTaskDelete ( 1 )\r
-#define INCLUDE_vTaskSuspend ( 1 )\r
-#define INCLUDE_xResumeFromISR ( 1 )\r
-#define INCLUDE_vTaskDelayUntil ( 1 )\r
-#define INCLUDE_vTaskDelay ( 1 )\r
-#define INCLUDE_xTaskGetSchedulerState ( 1 )\r
-#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 )\r
-#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )\r
-#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )\r
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )\r
-#define INCLUDE_pcTaskGetTaskName ( 0 )\r
-#define INCLUDE_eTaskGetState ( 1 )\r
-#define INCLUDE_xTimerPendFunctionCall ( 1 )\r
-\r
-/* Default value of CPU clock (RC)*/\r
-#define configCPU_CLOCK_HZ (( unsigned long ) 14000000)\r
-\r
-/* Defines used in energy modes */\r
-#if ( ( configSLEEP_MODE == 2 ) && ( ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) || ( configUSE_TICKLESS_IDLE == 1 ) ) )\r
- #define configSYSTICK_CLOCK_HZ ( 16384 )\r
-#endif\r
-\r
-#if ( ( configSLEEP_MODE == 3 ) && ( ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) || ( configUSE_TICKLESS_IDLE == 1 ) ) )\r
- #define configSYSTICK_CLOCK_HZ ( 2000 )\r
-#endif\r
-\r
-#if ( ( configUSE_TICKLESS_IDLE == 0 ) && ( configUSE_SLEEP_MODE_IN_IDLE == 1 ) )\r
-#define configUSE_IDLE_HOOK ( 1 )\r
-#else\r
-#define configUSE_IDLE_HOOK ( 0 )\r
-#endif\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
+#define INCLUDE_vTaskPrioritySet ( 1 )\r
+#define INCLUDE_uxTaskPriorityGet ( 1 )\r
+#define INCLUDE_vTaskDelete ( 1 )\r
+#define INCLUDE_vTaskSuspend ( 1 )\r
+#define INCLUDE_xResumeFromISR ( 1 )\r
+#define INCLUDE_vTaskDelayUntil ( 1 )\r
+#define INCLUDE_vTaskDelay ( 1 )\r
+#define INCLUDE_xTaskGetSchedulerState ( 1 )\r
+#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 )\r
+#define INCLUDE_uxTaskGetStackHighWaterMark ( 0 )\r
+#define INCLUDE_xTaskGetIdleTaskHandle ( 0 )\r
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle ( 0 )\r
+#define INCLUDE_pcTaskGetTaskName ( 0 )\r
+#define INCLUDE_eTaskGetState ( 1 )\r
+#define INCLUDE_xTimerPendFunctionCall ( 1 )\r
+\r
+/* Stop if an assertion fails. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
\r
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
- * standard names. */\r
-#define vPortSVCHandler SVC_Handler\r
-#define xPortPendSVHandler PendSV_Handler\r
-#define xPortSysTickHandler SysTick_Handler\r
-\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
\r
+/* For the linker. */\r
#define fabs __builtin_fabs\r
\r
#ifdef __cplusplus\r
\r
/* SiLabs includes. */\r
#include "bsp.h"\r
+#include "segmentlcd.h"\r
\r
/* Standard demo application includes. */\r
#include "flop.h"\r
\r
void main_full( void )\r
{\r
+ SegmentLCD_Init( false );\r
+ SegmentLCD_Write( "F'RTOS" );\r
+\r
/* Start all the other standard demo/test tasks. They have no particular\r
functionality, but do demonstrate how to use the FreeRTOS API and test the\r
kernel port. */\r
{\r
/* An error has been detected in one of the tasks - flash the LED\r
at a higher frequency to give visible feedback that something has\r
- gone wrong (it might just be that the loop back connector required\r
- by the comtest tasks has not been fitted). */\r
+ gone wrong. */\r
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD;\r
}\r
\r
\r
/* The rate at which data is sent to the queue. The 200ms value is converted\r
to ticks using the portTICK_PERIOD_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS )\r
+#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 500 )\r
\r
/* The number of items the queue can hold. This is 1 as the receive task\r
will remove items as they are added, meaning the send task should always find\r
static void prvQueueSendTask( void *pvParameters )\r
{\r
TickType_t xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
+const uint32_t ulValueToSend = 100UL;\r
\r
/* Remove compiler warning about unused parameter. */\r
( void ) pvParameters;\r
\r
static void prvQueueReceiveTask( void *pvParameters )\r
{\r
-unsigned long ulReceivedValue;\r
-const unsigned long ulExpectedValue = 100UL;\r
+uint32_t ulReceivedValue;\r
+const uint32_t ulExpectedValue = 100UL;\r
+const TickType_t xShortDelay = pdMS_TO_TICKS( 10 );\r
\r
/* Remove compiler warning about unused parameter. */\r
( void ) pvParameters;\r
is it the expected value? If it is, toggle the LED. */\r
if( ulReceivedValue == ulExpectedValue )\r
{\r
- BSP_LedToggle( mainTASK_LED );\r
+ /* Turn the LED on for a brief time only so it doens't distort the\r
+ enerty reading. */\r
+ BSP_LedSet( mainTASK_LED );\r
+ vTaskDelay( xShortDelay );\r
+ BSP_LedClear( mainTASK_LED );\r
ulReceivedValue = 0U;\r
}\r
}\r
+++ /dev/null
-/* ----------------------------------------------------------------------\r
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
-*\r
-* $Date: 12. March 2014\r
-* $Revision: V1.4.4\r
-*\r
-* Project: CMSIS DSP Library\r
-* Title: arm_math.h\r
-*\r
-* Description: Public header file for CMSIS DSP Library\r
-*\r
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\r
-*\r
-* Redistribution and use in source and binary forms, with or without\r
-* modification, are permitted provided that the following conditions\r
-* are met:\r
-* - Redistributions of source code must retain the above copyright\r
-* notice, this list of conditions and the following disclaimer.\r
-* - Redistributions in binary form must reproduce the above copyright\r
-* notice, this list of conditions and the following disclaimer in\r
-* the documentation and/or other materials provided with the\r
-* distribution.\r
-* - Neither the name of ARM LIMITED nor the names of its contributors\r
-* may be used to endorse or promote products derived from this\r
-* software without specific prior written permission.\r
-*\r
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
-* POSSIBILITY OF SUCH DAMAGE.\r
- * -------------------------------------------------------------------- */\r
-\r
-/**\r
- \mainpage CMSIS DSP Software Library\r
- *\r
- * Introduction\r
- * ------------\r
- *\r
- * This user manual describes the CMSIS DSP software library,\r
- * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
- *\r
- * The library is divided into a number of functions each covering a specific category:\r
- * - Basic math functions\r
- * - Fast math functions\r
- * - Complex math functions\r
- * - Filters\r
- * - Matrix functions\r
- * - Transforms\r
- * - Motor control functions\r
- * - Statistical functions\r
- * - Support functions\r
- * - Interpolation functions\r
- *\r
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
- * 32-bit integer and 32-bit floating-point values.\r
- *\r
- * Using the Library\r
- * ------------\r
- *\r
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
- * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\r
- * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\r
- * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\r
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\r
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\r
- *\r
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
- * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
- *\r
- * Examples\r
- * --------\r
- *\r
- * The library ships with a number of examples which demonstrate how to use the library functions.\r
- *\r
- * Toolchain Support\r
- * ------------\r
- *\r
- * The library has been developed and tested with MDK-ARM version 4.60.\r
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
- *\r
- * Building the Library\r
- * ------------\r
- *\r
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
- * - arm_cortexM_math.uvproj\r
- *\r
- *\r
- * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\r
- *\r
- * Pre-processor Macros\r
- * ------------\r
- *\r
- * Each library project have differant pre-processor macros.\r
- *\r
- * - UNALIGNED_SUPPORT_DISABLE:\r
- *\r
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
- *\r
- * - ARM_MATH_BIG_ENDIAN:\r
- *\r
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
- *\r
- * - ARM_MATH_MATRIX_CHECK:\r
- *\r
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
- *\r
- * - ARM_MATH_ROUNDING:\r
- *\r
- * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
- *\r
- * - ARM_MATH_CMx:\r
- *\r
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
- * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.\r
- *\r
- * - __FPU_PRESENT:\r
- *\r
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\r
- *\r
- * <hr>\r
- * CMSIS-DSP in ARM::CMSIS Pack\r
- * -----------------------------\r
- * \r
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
- * |File/Folder |Content |\r
- * |------------------------------|------------------------------------------------------------------------|\r
- * |\b CMSIS\\Documentation\\DSP | This documentation |\r
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
- * \r
- * <hr>\r
- * Revision History of CMSIS-DSP\r
- * ------------\r
- * Please refer to \ref ChangeLog_pg.\r
- *\r
- * Copyright Notice\r
- * ------------\r
- *\r
- * Copyright (C) 2010-2014 ARM Limited. All rights reserved.\r
- */\r
-\r
-\r
-/**\r
- * @defgroup groupMath Basic Math Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupFastMath Fast Math Functions\r
- * This set of functions provides a fast approximation to sine, cosine, and square root.\r
- * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
- * operate on individual values and not arrays.\r
- * There are separate functions for Q15, Q31, and floating-point data.\r
- *\r
- */\r
-\r
-/**\r
- * @defgroup groupCmplxMath Complex Math Functions\r
- * This set of functions operates on complex data vectors.\r
- * The data in the complex arrays is stored in an interleaved fashion\r
- * (real, imag, real, imag, ...).\r
- * In the API functions, the number of samples in a complex array refers\r
- * to the number of complex values; the array contains twice this number of\r
- * real values.\r
- */\r
-\r
-/**\r
- * @defgroup groupFilters Filtering Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupMatrix Matrix Functions\r
- *\r
- * This set of functions provides basic matrix math operations.\r
- * The functions operate on matrix data structures. For example,\r
- * the type\r
- * definition for the floating-point matrix structure is shown\r
- * below:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows; // number of rows of the matrix.\r
- * uint16_t numCols; // number of columns of the matrix.\r
- * float32_t *pData; // points to the data of the matrix.\r
- * } arm_matrix_instance_f32;\r
- * </pre>\r
- * There are similar definitions for Q15 and Q31 data types.\r
- *\r
- * The structure specifies the size of the matrix and then points to\r
- * an array of data. The array is of size <code>numRows X numCols</code>\r
- * and the values are arranged in row order. That is, the\r
- * matrix element (i, j) is stored at:\r
- * <pre>\r
- * pData[i*numCols + j]\r
- * </pre>\r
- *\r
- * \par Init Functions\r
- * There is an associated initialization function for each type of matrix\r
- * data structure.\r
- * The initialization function sets the values of the internal structure fields.\r
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
- *\r
- * \par\r
- * Use of the initialization function is optional. However, if initialization function is used\r
- * then the instance structure cannot be placed into a const data section.\r
- * To place the instance structure in a const data\r
- * section, manually initialize the data structure. For example:\r
- * <pre>\r
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
- * </pre>\r
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
- * specifies the number of columns, and <code>pData</code> points to the\r
- * data array.\r
- *\r
- * \par Size Checking\r
- * By default all of the matrix functions perform size checking on the input and\r
- * output matrices. For example, the matrix addition function verifies that the\r
- * two input matrices and the output matrix all have the same number of rows and\r
- * columns. If the size check fails the functions return:\r
- * <pre>\r
- * ARM_MATH_SIZE_MISMATCH\r
- * </pre>\r
- * Otherwise the functions return\r
- * <pre>\r
- * ARM_MATH_SUCCESS\r
- * </pre>\r
- * There is some overhead associated with this matrix size checking.\r
- * The matrix size checking is enabled via the \#define\r
- * <pre>\r
- * ARM_MATH_MATRIX_CHECK\r
- * </pre>\r
- * within the library project settings. By default this macro is defined\r
- * and size checking is enabled. By changing the project settings and\r
- * undefining this macro size checking is eliminated and the functions\r
- * run a bit faster. With size checking disabled the functions always\r
- * return <code>ARM_MATH_SUCCESS</code>.\r
- */\r
-\r
-/**\r
- * @defgroup groupTransforms Transform Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupController Controller Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupStats Statistics Functions\r
- */\r
-/**\r
- * @defgroup groupSupport Support Functions\r
- */\r
-\r
-/**\r
- * @defgroup groupInterpolation Interpolation Functions\r
- * These functions perform 1- and 2-dimensional interpolation of data.\r
- * Linear interpolation is used for 1-dimensional data and\r
- * bilinear interpolation is used for 2-dimensional data.\r
- */\r
-\r
-/**\r
- * @defgroup groupExamples Examples\r
- */\r
-#ifndef _ARM_MATH_H\r
-#define _ARM_MATH_H\r
-\r
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
-\r
-#if defined(ARM_MATH_CM7)\r
- #include "core_cm7.h"\r
-#elif defined (ARM_MATH_CM4)\r
- #include "core_cm4.h"\r
-#elif defined (ARM_MATH_CM3)\r
- #include "core_cm3.h"\r
-#elif defined (ARM_MATH_CM0)\r
- #include "core_cm0.h"\r
-#define ARM_MATH_CM0_FAMILY\r
- #elif defined (ARM_MATH_CM0PLUS)\r
-#include "core_cm0plus.h"\r
- #define ARM_MATH_CM0_FAMILY\r
-#else\r
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"\r
-#endif\r
-\r
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
-#include "string.h"\r
-#include "math.h"\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Macros required for reciprocal calculation in Normalized LMS\r
- */\r
-\r
-#define DELTA_Q31 (0x100)\r
-#define DELTA_Q15 0x5\r
-#define INDEX_MASK 0x0000003F\r
-#ifndef PI\r
-#define PI 3.14159265358979f\r
-#endif\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Fast math approximations\r
- */\r
-\r
-#define FAST_MATH_TABLE_SIZE 512\r
-#define FAST_MATH_Q31_SHIFT (32 - 10)\r
-#define FAST_MATH_Q15_SHIFT (16 - 10)\r
-#define CONTROLLER_Q31_SHIFT (32 - 9)\r
-#define TABLE_SIZE 256\r
-#define TABLE_SPACING_Q31 0x400000\r
-#define TABLE_SPACING_Q15 0x80\r
-\r
- /**\r
- * @brief Macros required for SINE and COSINE Controller functions\r
- */\r
- /* 1.31(q31) Fixed value of 2/360 */\r
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
-#define INPUT_SPACING 0xB60B61\r
-\r
- /**\r
- * @brief Macro for Unaligned Support\r
- */\r
-#ifndef UNALIGNED_SUPPORT_DISABLE\r
- #define ALIGN4\r
-#else\r
- #if defined (__GNUC__)\r
- #define ALIGN4 __attribute__((aligned(4)))\r
- #else\r
- #define ALIGN4 __align(4)\r
- #endif\r
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
-\r
- /**\r
- * @brief Error status returned by some functions in the library.\r
- */\r
-\r
- typedef enum\r
- {\r
- ARM_MATH_SUCCESS = 0, /**< No error */\r
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
- } arm_status;\r
-\r
- /**\r
- * @brief 8-bit fractional data type in 1.7 format.\r
- */\r
- typedef int8_t q7_t;\r
-\r
- /**\r
- * @brief 16-bit fractional data type in 1.15 format.\r
- */\r
- typedef int16_t q15_t;\r
-\r
- /**\r
- * @brief 32-bit fractional data type in 1.31 format.\r
- */\r
- typedef int32_t q31_t;\r
-\r
- /**\r
- * @brief 64-bit fractional data type in 1.63 format.\r
- */\r
- typedef int64_t q63_t;\r
-\r
- /**\r
- * @brief 32-bit floating-point type definition.\r
- */\r
- typedef float float32_t;\r
-\r
- /**\r
- * @brief 64-bit floating-point type definition.\r
- */\r
- typedef double float64_t;\r
-\r
- /**\r
- * @brief definition to read/write two 16 bit values.\r
- */\r
-#if defined __CC_ARM\r
-#define __SIMD32_TYPE int32_t __packed\r
-#define CMSIS_UNUSED __attribute__((unused))\r
-#elif defined __ICCARM__\r
-#define CMSIS_UNUSED\r
-#define __SIMD32_TYPE int32_t __packed\r
-#elif defined __GNUC__\r
-#define __SIMD32_TYPE int32_t\r
-#define CMSIS_UNUSED __attribute__((unused))\r
-#elif defined __CSMC__ /* Cosmic */\r
-#define CMSIS_UNUSED\r
-#define __SIMD32_TYPE int32_t\r
-#else\r
-#error Unknown compiler\r
-#endif\r
-\r
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
-\r
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
-\r
-#define __SIMD64(addr) (*(int64_t **) & (addr))\r
-\r
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
- /**\r
- * @brief definition to pack two 16 bit values.\r
- */\r
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief definition to pack four 8 bit values.\r
- */\r
-#ifndef ARM_MATH_BIG_ENDIAN\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
-#else\r
-\r
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
-\r
-#endif\r
-\r
-\r
- /**\r
- * @brief Clips Q63 to Q31 values.\r
- */\r
- static __INLINE q31_t clip_q63_to_q31(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q63 to Q15 values.\r
- */\r
- static __INLINE q15_t clip_q63_to_q15(\r
- q63_t x)\r
- {\r
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q7 values.\r
- */\r
- static __INLINE q7_t clip_q31_to_q7(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
- }\r
-\r
- /**\r
- * @brief Clips Q31 to Q15 values.\r
- */\r
- static __INLINE q15_t clip_q31_to_q15(\r
- q31_t x)\r
- {\r
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
- }\r
-\r
- /**\r
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
- */\r
-\r
- static __INLINE q63_t mult32x64(\r
- q63_t x,\r
- q31_t y)\r
- {\r
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
- (((q63_t) (x >> 32) * y)));\r
- }\r
-\r
-\r
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )\r
-#define __CLZ __clz\r
-#endif\r
-\r
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
-\r
- static __INLINE uint32_t __CLZ(\r
- q31_t data);\r
-\r
-\r
- static __INLINE uint32_t __CLZ(\r
- q31_t data)\r
- {\r
- uint32_t count = 0;\r
- uint32_t mask = 0x80000000;\r
-\r
- while((data & mask) == 0)\r
- {\r
- count += 1u;\r
- mask = mask >> 1u;\r
- }\r
-\r
- return (count);\r
-\r
- }\r
-\r
-#endif\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
- */\r
-\r
- static __INLINE uint32_t arm_recip_q31(\r
- q31_t in,\r
- q31_t * dst,\r
- q31_t * pRecipTable)\r
- {\r
-\r
- uint32_t out, tempVal;\r
- uint32_t index, i;\r
- uint32_t signBits;\r
-\r
- if(in > 0)\r
- {\r
- signBits = __CLZ(in) - 1;\r
- }\r
- else\r
- {\r
- signBits = __CLZ(-in) - 1;\r
- }\r
-\r
- /* Convert input sample to 1.31 format */\r
- in = in << signBits;\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = (uint32_t) (in >> 24u);\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.31 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0u; i < 2u; i++)\r
- {\r
- tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
- tempVal = 0x7FFFFFFF - tempVal;\r
- /* 1.31 with exp 1 */\r
- //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
- out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1u);\r
-\r
- }\r
-\r
- /**\r
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
- */\r
- static __INLINE uint32_t arm_recip_q15(\r
- q15_t in,\r
- q15_t * dst,\r
- q15_t * pRecipTable)\r
- {\r
-\r
- uint32_t out = 0, tempVal = 0;\r
- uint32_t index = 0, i = 0;\r
- uint32_t signBits = 0;\r
-\r
- if(in > 0)\r
- {\r
- signBits = __CLZ(in) - 17;\r
- }\r
- else\r
- {\r
- signBits = __CLZ(-in) - 17;\r
- }\r
-\r
- /* Convert input sample to 1.15 format */\r
- in = in << signBits;\r
-\r
- /* calculation of index for initial approximated Val */\r
- index = in >> 8;\r
- index = (index & INDEX_MASK);\r
-\r
- /* 1.15 with exp 1 */\r
- out = pRecipTable[index];\r
-\r
- /* calculation of reciprocal value */\r
- /* running approximation for two iterations */\r
- for (i = 0; i < 2; i++)\r
- {\r
- tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
- tempVal = 0x7FFF - tempVal;\r
- /* 1.15 with exp 1 */\r
- out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
- }\r
-\r
- /* write output */\r
- *dst = out;\r
-\r
- /* return num of signbits of out = 1/in value */\r
- return (signBits + 1);\r
-\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinisic function for only M0 processors\r
- */\r
-#if defined(ARM_MATH_CM0_FAMILY)\r
-\r
- static __INLINE q31_t __SSAT(\r
- q31_t x,\r
- uint32_t y)\r
- {\r
- int32_t posMax, negMin;\r
- uint32_t i;\r
-\r
- posMax = 1;\r
- for (i = 0; i < (y - 1); i++)\r
- {\r
- posMax = posMax * 2;\r
- }\r
-\r
- if(x > 0)\r
- {\r
- posMax = (posMax - 1);\r
-\r
- if(x > posMax)\r
- {\r
- x = posMax;\r
- }\r
- }\r
- else\r
- {\r
- negMin = -posMax;\r
-\r
- if(x < negMin)\r
- {\r
- x = negMin;\r
- }\r
- }\r
- return (x);\r
-\r
-\r
- }\r
-\r
-#endif /* end of ARM_MATH_CM0_FAMILY */\r
-\r
-\r
-\r
- /*\r
- * @brief C custom defined intrinsic function for M3 and M0 processors\r
- */\r
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\r
-\r
- /*\r
- * @brief C custom defined QADD8 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QADD8(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q7_t r, s, t, u;\r
-\r
- r = (q7_t) x;\r
- s = (q7_t) y;\r
-\r
- r = __SSAT((q31_t) (r + s), 8);\r
- s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
- t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
- u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
-\r
- sum =\r
- (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
- (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
-\r
- return sum;\r
-\r
- }\r
-\r
- /*\r
- * @brief C custom defined QSUB8 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QSUB8(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s, t, u;\r
-\r
- r = (q7_t) x;\r
- s = (q7_t) y;\r
-\r
- r = __SSAT((r - s), 8);\r
- s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
- t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
- u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
-\r
- sum =\r
- (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &\r
- 0x000000FF);\r
-\r
- return sum;\r
- }\r
-\r
- /*\r
- * @brief C custom defined QADD16 for M3 and M0 processors\r
- */\r
-\r
- /*\r
- * @brief C custom defined QADD16 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QADD16(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = __SSAT(r + s, 16);\r
- s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
-\r
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return sum;\r
-\r
- }\r
-\r
- /*\r
- * @brief C custom defined SHADD16 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SHADD16(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = ((r >> 1) + (s >> 1));\r
- s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
-\r
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return sum;\r
-\r
- }\r
-\r
- /*\r
- * @brief C custom defined QSUB16 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QSUB16(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = __SSAT(r - s, 16);\r
- s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
-\r
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return sum;\r
- }\r
-\r
- /*\r
- * @brief C custom defined SHSUB16 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SHSUB16(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t diff;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = ((r >> 1) - (s >> 1));\r
- s = (((x >> 17) - (y >> 17)) << 16);\r
-\r
- diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return diff;\r
- }\r
-\r
- /*\r
- * @brief C custom defined QASX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QASX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum = 0;\r
-\r
- sum =\r
- ((sum +\r
- clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +\r
- clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));\r
-\r
- return sum;\r
- }\r
-\r
- /*\r
- * @brief C custom defined SHASX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SHASX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = ((r >> 1) - (y >> 17));\r
- s = (((x >> 17) + (s >> 1)) << 16);\r
-\r
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return sum;\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined QSAX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QSAX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum = 0;\r
-\r
- sum =\r
- ((sum +\r
- clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +\r
- clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));\r
-\r
- return sum;\r
- }\r
-\r
- /*\r
- * @brief C custom defined SHSAX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SHSAX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- q31_t sum;\r
- q31_t r, s;\r
-\r
- r = (q15_t) x;\r
- s = (q15_t) y;\r
-\r
- r = ((r >> 1) + (y >> 17));\r
- s = (((x >> 17) - (s >> 1)) << 16);\r
-\r
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
-\r
- return sum;\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUSDX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMUSDX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -\r
- ((q15_t) (x >> 16) * (q15_t) y)));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUADX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMUADX(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +\r
- ((q15_t) (x >> 16) * (q15_t) y)));\r
- }\r
-\r
- /*\r
- * @brief C custom defined QADD for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QADD(\r
- q31_t x,\r
- q31_t y)\r
- {\r
- return clip_q63_to_q31((q63_t) x + y);\r
- }\r
-\r
- /*\r
- * @brief C custom defined QSUB for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __QSUB(\r
- q31_t x,\r
- q31_t y)\r
- {\r
- return clip_q63_to_q31((q63_t) x - y);\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMLAD for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMLAD(\r
- q31_t x,\r
- q31_t y,\r
- q31_t sum)\r
- {\r
-\r
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
- ((q15_t) x * (q15_t) y));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMLADX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMLADX(\r
- q31_t x,\r
- q31_t y,\r
- q31_t sum)\r
- {\r
-\r
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +\r
- ((q15_t) x * (q15_t) (y >> 16)));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMLSDX for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMLSDX(\r
- q31_t x,\r
- q31_t y,\r
- q31_t sum)\r
- {\r
-\r
- return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +\r
- ((q15_t) x * (q15_t) (y >> 16)));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMLALD for M3 and M0 processors\r
- */\r
- static __INLINE q63_t __SMLALD(\r
- q31_t x,\r
- q31_t y,\r
- q63_t sum)\r
- {\r
-\r
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +\r
- ((q15_t) x * (q15_t) y));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMLALDX for M3 and M0 processors\r
- */\r
- static __INLINE q63_t __SMLALDX(\r
- q31_t x,\r
- q31_t y,\r
- q63_t sum)\r
- {\r
-\r
- return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +\r
- ((q15_t) x * (q15_t) (y >> 16));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUAD for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMUAD(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- return (((x >> 16) * (y >> 16)) +\r
- (((x << 16) >> 16) * ((y << 16) >> 16)));\r
- }\r
-\r
- /*\r
- * @brief C custom defined SMUSD for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SMUSD(\r
- q31_t x,\r
- q31_t y)\r
- {\r
-\r
- return (-((x >> 16) * (y >> 16)) +\r
- (((x << 16) >> 16) * ((y << 16) >> 16)));\r
- }\r
-\r
-\r
- /*\r
- * @brief C custom defined SXTB16 for M3 and M0 processors\r
- */\r
- static __INLINE q31_t __SXTB16(\r
- q31_t x)\r
- {\r
-\r
- return ((((x << 24) >> 24) & 0x0000FFFF) |\r
- (((x << 8) >> 8) & 0xFFFF0000));\r
- }\r
-\r
-\r
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q7 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q7;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- } arm_fir_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- } arm_fir_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q7 FIR filter.\r
- * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_q7(\r
- const arm_fir_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q7 FIR filter.\r
- * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed.\r
- * @return none\r
- */\r
- void arm_fir_init_q7(\r
- arm_fir_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR filter.\r
- * @param[in] *S points to an instance of the Q15 FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_fast_q15(\r
- const arm_fir_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR filter.\r
- * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>numTaps</code> is not a supported value.\r
- */\r
-\r
- arm_status arm_fir_init_q15(\r
- arm_fir_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR filter.\r
- * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q31 FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_fast_q31(\r
- const arm_fir_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR filter.\r
- * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return none.\r
- */\r
- void arm_fir_init_q31(\r
- arm_fir_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR filter.\r
- * @param[in] *S points to an instance of the floating-point FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_f32(\r
- const arm_fir_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR filter.\r
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
- * @param[in] numTaps Number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of samples that are processed at a time.\r
- * @return none.\r
- */\r
- void arm_fir_init_f32(\r
- arm_fir_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
-\r
- } arm_biquad_casd_df1_inst_q15;\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
-\r
- } arm_biquad_casd_df1_inst_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Biquad cascade filter.\r
- */\r
- typedef struct\r
- {\r
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
-\r
-\r
- } arm_biquad_casd_df1_inst_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 Biquad cascade filter.\r
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df1_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q15 Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_df1_init_q15(\r
- arm_biquad_casd_df1_inst_q15 * S,\r
- uint8_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int8_t postShift);\r
-\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df1_fast_q15(\r
- const arm_biquad_casd_df1_inst_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 Biquad cascade filter\r
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df1_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df1_fast_q31(\r
- const arm_biquad_casd_df1_inst_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q31 Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_df1_init_q31(\r
- arm_biquad_casd_df1_inst_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int8_t postShift);\r
-\r
- /**\r
- * @brief Processing function for the floating-point Biquad cascade filter.\r
- * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df1_f32(\r
- const arm_biquad_casd_df1_inst_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the floating-point Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_df1_init_f32(\r
- arm_biquad_casd_df1_inst_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float32_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point matrix structure.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- float64_t *pData; /**< points to the data of the matrix. */\r
- } arm_matrix_instance_f64;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 matrix structure.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q15_t *pData; /**< points to the data of the matrix. */\r
-\r
- } arm_matrix_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 matrix structure.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows of the matrix. */\r
- uint16_t numCols; /**< number of columns of the matrix. */\r
- q31_t *pData; /**< points to the data of the matrix. */\r
-\r
- } arm_matrix_instance_q31;\r
-\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix addition.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_add_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
- /**\r
- * @brief Q15 matrix addition.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_add_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
- /**\r
- * @brief Q31 matrix addition.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_add_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
- /**\r
- * @brief Floating-point, complex, matrix multiplication.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_cmplx_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
- /**\r
- * @brief Q15, complex, matrix multiplication.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_cmplx_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pScratch);\r
-\r
- /**\r
- * @brief Q31, complex, matrix multiplication.\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_cmplx_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix transpose.\r
- * @param[in] *pSrc points to the input matrix\r
- * @param[out] *pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_trans_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q15 matrix transpose.\r
- * @param[in] *pSrc points to the input matrix\r
- * @param[out] *pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_trans_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
- /**\r
- * @brief Q31 matrix transpose.\r
- * @param[in] *pSrc points to the input matrix\r
- * @param[out] *pDst points to the output matrix\r
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_trans_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix multiplication\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_mult_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
- /**\r
- * @brief Q15 matrix multiplication\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @param[in] *pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_mult_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
- /**\r
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @param[in] *pState points to the array for storing intermediate results\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_mult_fast_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst,\r
- q15_t * pState);\r
-\r
- /**\r
- * @brief Q31 matrix multiplication\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_mult_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
- /**\r
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_mult_fast_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix subtraction\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_sub_f32(\r
- const arm_matrix_instance_f32 * pSrcA,\r
- const arm_matrix_instance_f32 * pSrcB,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
- /**\r
- * @brief Q15 matrix subtraction\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_sub_q15(\r
- const arm_matrix_instance_q15 * pSrcA,\r
- const arm_matrix_instance_q15 * pSrcB,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
- /**\r
- * @brief Q31 matrix subtraction\r
- * @param[in] *pSrcA points to the first input matrix structure\r
- * @param[in] *pSrcB points to the second input matrix structure\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_sub_q31(\r
- const arm_matrix_instance_q31 * pSrcA,\r
- const arm_matrix_instance_q31 * pSrcB,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
- /**\r
- * @brief Floating-point matrix scaling.\r
- * @param[in] *pSrc points to the input matrix\r
- * @param[in] scale scale factor\r
- * @param[out] *pDst points to the output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_scale_f32(\r
- const arm_matrix_instance_f32 * pSrc,\r
- float32_t scale,\r
- arm_matrix_instance_f32 * pDst);\r
-\r
- /**\r
- * @brief Q15 matrix scaling.\r
- * @param[in] *pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] *pDst points to output matrix\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_scale_q15(\r
- const arm_matrix_instance_q15 * pSrc,\r
- q15_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q15 * pDst);\r
-\r
- /**\r
- * @brief Q31 matrix scaling.\r
- * @param[in] *pSrc points to input matrix\r
- * @param[in] scaleFract fractional portion of the scale factor\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] *pDst points to output matrix structure\r
- * @return The function returns either\r
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
- */\r
-\r
- arm_status arm_mat_scale_q31(\r
- const arm_matrix_instance_q31 * pSrc,\r
- q31_t scaleFract,\r
- int32_t shift,\r
- arm_matrix_instance_q31 * pDst);\r
-\r
-\r
- /**\r
- * @brief Q31 matrix initialization.\r
- * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] *pData points to the matrix data array.\r
- * @return none\r
- */\r
-\r
- void arm_mat_init_q31(\r
- arm_matrix_instance_q31 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q31_t * pData);\r
-\r
- /**\r
- * @brief Q15 matrix initialization.\r
- * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] *pData points to the matrix data array.\r
- * @return none\r
- */\r
-\r
- void arm_mat_init_q15(\r
- arm_matrix_instance_q15 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- q15_t * pData);\r
-\r
- /**\r
- * @brief Floating-point matrix initialization.\r
- * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
- * @param[in] nRows number of rows in the matrix.\r
- * @param[in] nColumns number of columns in the matrix.\r
- * @param[in] *pData points to the matrix data array.\r
- * @return none\r
- */\r
-\r
- void arm_mat_init_f32(\r
- arm_matrix_instance_f32 * S,\r
- uint16_t nRows,\r
- uint16_t nColumns,\r
- float32_t * pData);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
-#ifdef ARM_MATH_CM0_FAMILY\r
- q15_t A1;\r
- q15_t A2;\r
-#else\r
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
-#endif\r
- q15_t state[3]; /**< The state array of length 3. */\r
- q15_t Kp; /**< The proportional gain. */\r
- q15_t Ki; /**< The integral gain. */\r
- q15_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 PID Control.\r
- */\r
- typedef struct\r
- {\r
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- q31_t A2; /**< The derived gain, A2 = Kd . */\r
- q31_t state[3]; /**< The state array of length 3. */\r
- q31_t Kp; /**< The proportional gain. */\r
- q31_t Ki; /**< The integral gain. */\r
- q31_t Kd; /**< The derivative gain. */\r
-\r
- } arm_pid_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point PID Control.\r
- */\r
- typedef struct\r
- {\r
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
- float32_t A2; /**< The derived gain, A2 = Kd . */\r
- float32_t state[3]; /**< The state array of length 3. */\r
- float32_t Kp; /**< The proportional gain. */\r
- float32_t Ki; /**< The integral gain. */\r
- float32_t Kd; /**< The derivative gain. */\r
- } arm_pid_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point PID Control.\r
- * @param[in,out] *S points to an instance of the PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- * @return none.\r
- */\r
- void arm_pid_init_f32(\r
- arm_pid_instance_f32 * S,\r
- int32_t resetStateFlag);\r
-\r
- /**\r
- * @brief Reset function for the floating-point PID Control.\r
- * @param[in,out] *S is an instance of the floating-point PID Control structure\r
- * @return none\r
- */\r
- void arm_pid_reset_f32(\r
- arm_pid_instance_f32 * S);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 PID Control.\r
- * @param[in,out] *S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- * @return none.\r
- */\r
- void arm_pid_init_q31(\r
- arm_pid_instance_q31 * S,\r
- int32_t resetStateFlag);\r
-\r
-\r
- /**\r
- * @brief Reset function for the Q31 PID Control.\r
- * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
- * @return none\r
- */\r
-\r
- void arm_pid_reset_q31(\r
- arm_pid_instance_q31 * S);\r
-\r
- /**\r
- * @brief Initialization function for the Q15 PID Control.\r
- * @param[in,out] *S points to an instance of the Q15 PID structure.\r
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
- * @return none.\r
- */\r
- void arm_pid_init_q15(\r
- arm_pid_instance_q15 * S,\r
- int32_t resetStateFlag);\r
-\r
- /**\r
- * @brief Reset function for the Q15 PID Control.\r
- * @param[in,out] *S points to an instance of the q15 PID Control structure\r
- * @return none\r
- */\r
- void arm_pid_reset_q15(\r
- arm_pid_instance_q15 * S);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point Linear Interpolate function.\r
- */\r
- typedef struct\r
- {\r
- uint32_t nValues; /**< nValues */\r
- float32_t x1; /**< x1 */\r
- float32_t xSpacing; /**< xSpacing */\r
- float32_t *pYData; /**< pointer to the table of Y values */\r
- } arm_linear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point bilinear interpolation function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- float32_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 bilinear interpolation function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q31_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q15_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 bilinear interpolation function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numRows; /**< number of rows in the data table. */\r
- uint16_t numCols; /**< number of columns in the data table. */\r
- q7_t *pData; /**< points to the data table. */\r
- } arm_bilinear_interp_instance_q7;\r
-\r
-\r
- /**\r
- * @brief Q7 vector multiplication.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_mult_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q15 vector multiplication.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_mult_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q31 vector multiplication.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_mult_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Floating-point vector multiplication.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_mult_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q15(\r
- arm_cfft_radix2_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q15(\r
- const arm_cfft_radix2_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q15;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q15(\r
- arm_cfft_radix4_instance_q15 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q15(\r
- const arm_cfft_radix4_instance_q15 * S,\r
- q15_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix2_instance_q31;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_q31(\r
- arm_cfft_radix2_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_q31(\r
- const arm_cfft_radix2_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- } arm_cfft_radix4_instance_q31;\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_q31(\r
- const arm_cfft_radix4_instance_q31 * S,\r
- q31_t * pSrc);\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_q31(\r
- arm_cfft_radix4_instance_q31 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix2_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix2_init_f32(\r
- arm_cfft_radix2_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix2_f32(\r
- const arm_cfft_radix2_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
- float32_t onebyfftLen; /**< value of 1/fftLen. */\r
- } arm_cfft_radix4_instance_f32;\r
-\r
-/* Deprecated */\r
- arm_status arm_cfft_radix4_init_f32(\r
- arm_cfft_radix4_instance_f32 * S,\r
- uint16_t fftLen,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
-/* Deprecated */\r
- void arm_cfft_radix4_f32(\r
- const arm_cfft_radix4_instance_f32 * S,\r
- float32_t * pSrc);\r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q15;\r
-\r
-void arm_cfft_q15( \r
- const arm_cfft_instance_q15 * S, \r
- q15_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag); \r
-\r
- /**\r
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_q31;\r
-\r
-void arm_cfft_q31( \r
- const arm_cfft_instance_q31 * S, \r
- q31_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag); \r
- \r
- /**\r
- * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t fftLen; /**< length of the FFT. */\r
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
- uint16_t bitRevLength; /**< bit reversal table length. */\r
- } arm_cfft_instance_f32;\r
-\r
- void arm_cfft_f32(\r
- const arm_cfft_instance_f32 * S,\r
- float32_t * p1,\r
- uint8_t ifftFlag,\r
- uint8_t bitReverseFlag);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q15;\r
-\r
- arm_status arm_rfft_init_q15(\r
- arm_rfft_instance_q15 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q15(\r
- const arm_rfft_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_q31;\r
-\r
- arm_status arm_rfft_init_q31(\r
- arm_rfft_instance_q31 * S,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_q31(\r
- const arm_rfft_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint32_t fftLenReal; /**< length of the real FFT. */\r
- uint16_t fftLenBy2; /**< length of the complex FFT. */\r
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_rfft_instance_f32;\r
-\r
- arm_status arm_rfft_init_f32(\r
- arm_rfft_instance_f32 * S,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint32_t fftLenReal,\r
- uint32_t ifftFlagR,\r
- uint32_t bitReverseFlag);\r
-\r
- void arm_rfft_f32(\r
- const arm_rfft_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
- */\r
-\r
-typedef struct\r
- {\r
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
- uint16_t fftLenRFFT; /**< length of the real sequence */\r
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
- } arm_rfft_fast_instance_f32 ;\r
-\r
-arm_status arm_rfft_fast_init_f32 (\r
- arm_rfft_fast_instance_f32 * S,\r
- uint16_t fftLen);\r
-\r
-void arm_rfft_fast_f32(\r
- arm_rfft_fast_instance_f32 * S,\r
- float32_t * p, float32_t * pOut,\r
- uint8_t ifftFlag);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- float32_t normalize; /**< normalizing factor. */\r
- float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
- float32_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_f32;\r
-\r
- /**\r
- * @brief Initialization function for the floating-point DCT4/IDCT4.\r
- * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
- * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
- * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
- */\r
-\r
- arm_status arm_dct4_init_f32(\r
- arm_dct4_instance_f32 * S,\r
- arm_rfft_instance_f32 * S_RFFT,\r
- arm_cfft_radix4_instance_f32 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- float32_t normalize);\r
-\r
- /**\r
- * @brief Processing function for the floating-point DCT4/IDCT4.\r
- * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_dct4_f32(\r
- const arm_dct4_instance_f32 * S,\r
- float32_t * pState,\r
- float32_t * pInlineBuffer);\r
-\r
- /**\r
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q31_t normalize; /**< normalizing factor. */\r
- q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q31_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q31;\r
-\r
- /**\r
- * @brief Initialization function for the Q31 DCT4/IDCT4.\r
- * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
- * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
- * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
-\r
- arm_status arm_dct4_init_q31(\r
- arm_dct4_instance_q31 * S,\r
- arm_rfft_instance_q31 * S_RFFT,\r
- arm_cfft_radix4_instance_q31 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q31_t normalize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 DCT4/IDCT4.\r
- * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_dct4_q31(\r
- const arm_dct4_instance_q31 * S,\r
- q31_t * pState,\r
- q31_t * pInlineBuffer);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t N; /**< length of the DCT4. */\r
- uint16_t Nby2; /**< half of the length of the DCT4. */\r
- q15_t normalize; /**< normalizing factor. */\r
- q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
- q15_t *pCosFactor; /**< points to the cosFactor table. */\r
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
- } arm_dct4_instance_q15;\r
-\r
- /**\r
- * @brief Initialization function for the Q15 DCT4/IDCT4.\r
- * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
- * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
- * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
- * @param[in] N length of the DCT4.\r
- * @param[in] Nby2 half of the length of the DCT4.\r
- * @param[in] normalize normalizing factor.\r
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
- */\r
-\r
- arm_status arm_dct4_init_q15(\r
- arm_dct4_instance_q15 * S,\r
- arm_rfft_instance_q15 * S_RFFT,\r
- arm_cfft_radix4_instance_q15 * S_CFFT,\r
- uint16_t N,\r
- uint16_t Nby2,\r
- q15_t normalize);\r
-\r
- /**\r
- * @brief Processing function for the Q15 DCT4/IDCT4.\r
- * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_dct4_q15(\r
- const arm_dct4_instance_q15 * S,\r
- q15_t * pState,\r
- q15_t * pInlineBuffer);\r
-\r
- /**\r
- * @brief Floating-point vector addition.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_add_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q7 vector addition.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_add_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q15 vector addition.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_add_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q31 vector addition.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_add_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Floating-point vector subtraction.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_sub_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q7 vector subtraction.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_sub_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q15 vector subtraction.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_sub_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q31 vector subtraction.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_sub_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Multiplies a floating-point vector by a scalar.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] scale scale factor to be applied\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_scale_f32(\r
- float32_t * pSrc,\r
- float32_t scale,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Multiplies a Q7 vector by a scalar.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_scale_q7(\r
- q7_t * pSrc,\r
- q7_t scaleFract,\r
- int8_t shift,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Multiplies a Q15 vector by a scalar.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_scale_q15(\r
- q15_t * pSrc,\r
- q15_t scaleFract,\r
- int8_t shift,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Multiplies a Q31 vector by a scalar.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] scaleFract fractional portion of the scale value\r
- * @param[in] shift number of bits to shift the result by\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_scale_q31(\r
- q31_t * pSrc,\r
- q31_t scaleFract,\r
- int8_t shift,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q7 vector absolute value.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[out] *pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_abs_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Floating-point vector absolute value.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[out] *pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_abs_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q15 vector absolute value.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[out] *pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_abs_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Q31 vector absolute value.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[out] *pDst points to the output buffer\r
- * @param[in] blockSize number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_abs_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Dot product of floating-point vectors.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] *result output result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t blockSize,\r
- float32_t * result);\r
-\r
- /**\r
- * @brief Dot product of Q7 vectors.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] *result output result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_dot_prod_q7(\r
- q7_t * pSrcA,\r
- q7_t * pSrcB,\r
- uint32_t blockSize,\r
- q31_t * result);\r
-\r
- /**\r
- * @brief Dot product of Q15 vectors.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] *result output result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
- /**\r
- * @brief Dot product of Q31 vectors.\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] blockSize number of samples in each vector\r
- * @param[out] *result output result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t blockSize,\r
- q63_t * result);\r
-\r
- /**\r
- * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_shift_q7(\r
- q7_t * pSrc,\r
- int8_t shiftBits,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_shift_q15(\r
- q15_t * pSrc,\r
- int8_t shiftBits,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_shift_q31(\r
- q31_t * pSrc,\r
- int8_t shiftBits,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Adds a constant offset to a floating-point vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_offset_f32(\r
- float32_t * pSrc,\r
- float32_t offset,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q7 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_offset_q7(\r
- q7_t * pSrc,\r
- q7_t offset,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q15 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_offset_q15(\r
- q15_t * pSrc,\r
- q15_t offset,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Adds a constant offset to a Q31 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[in] offset is the offset to be added\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_offset_q31(\r
- q31_t * pSrc,\r
- q31_t offset,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Negates the elements of a floating-point vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_negate_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Negates the elements of a Q7 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_negate_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Negates the elements of a Q15 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_negate_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Negates the elements of a Q31 vector.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] blockSize number of samples in the vector\r
- * @return none.\r
- */\r
-\r
- void arm_negate_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
- /**\r
- * @brief Copies the elements of a floating-point vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_copy_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Copies the elements of a Q7 vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_copy_q7(\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Copies the elements of a Q15 vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_copy_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Copies the elements of a Q31 vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_copy_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
- /**\r
- * @brief Fills a constant value into a floating-point vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_fill_f32(\r
- float32_t value,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Fills a constant value into a Q7 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_fill_q7(\r
- q7_t value,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Fills a constant value into a Q15 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_fill_q15(\r
- q15_t value,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Fills a constant value into a Q31 vector.\r
- * @param[in] value input value to be filled\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_fill_q31(\r
- q31_t value,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-/**\r
- * @brief Convolution of floating-point sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return none.\r
- */\r
-\r
-\r
- void arm_conv_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Convolution of Q15 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return none.\r
- */\r
-\r
- void arm_conv_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return none.\r
- */\r
-\r
- void arm_conv_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-\r
- /**\r
- * @brief Convolution of Q7 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
- * @return none.\r
- */\r
-\r
- void arm_conv_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of floating-point sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Partial convolution of Q15 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
- /**\r
- * @brief Partial convolution of Q7 sequences\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
-/**\r
- * @brief Partial convolution of Q7 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] firstIndex is the first output sample to start with.\r
- * @param[in] numPoints is the number of output points to be computed.\r
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
- */\r
-\r
- arm_status arm_conv_partial_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- uint32_t firstIndex,\r
- uint32_t numPoints);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR decimator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- } arm_fir_decimate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR decimator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
-\r
- } arm_fir_decimate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR decimator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t M; /**< decimation factor. */\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
-\r
- } arm_fir_decimate_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR decimator.\r
- * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none\r
- */\r
-\r
- void arm_fir_decimate_f32(\r
- const arm_fir_decimate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR decimator.\r
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
-\r
- arm_status arm_fir_decimate_init_f32(\r
- arm_fir_decimate_instance_f32 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator.\r
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none\r
- */\r
-\r
- void arm_fir_decimate_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none\r
- */\r
-\r
- void arm_fir_decimate_fast_q15(\r
- const arm_fir_decimate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR decimator.\r
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
-\r
- arm_status arm_fir_decimate_init_q15(\r
- arm_fir_decimate_instance_q15 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator.\r
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none\r
- */\r
-\r
- void arm_fir_decimate_q31(\r
- const arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none\r
- */\r
-\r
- void arm_fir_decimate_fast_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR decimator.\r
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
- * @param[in] numTaps number of coefficients in the filter.\r
- * @param[in] M decimation factor.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * <code>blockSize</code> is not a multiple of <code>M</code>.\r
- */\r
-\r
- arm_status arm_fir_decimate_init_q31(\r
- arm_fir_decimate_instance_q31 * S,\r
- uint16_t numTaps,\r
- uint8_t M,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR interpolator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR interpolator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
- } arm_fir_interpolate_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR interpolator.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t L; /**< upsample factor. */\r
- uint16_t phaseLength; /**< length of each polyphase filter component. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
- } arm_fir_interpolate_instance_f32;\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR interpolator.\r
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_interpolate_q15(\r
- const arm_fir_interpolate_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR interpolator.\r
- * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficient buffer.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
-\r
- arm_status arm_fir_interpolate_init_q15(\r
- arm_fir_interpolate_instance_q15 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR interpolator.\r
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_interpolate_q31(\r
- const arm_fir_interpolate_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR interpolator.\r
- * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficient buffer.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
-\r
- arm_status arm_fir_interpolate_init_q31(\r
- arm_fir_interpolate_instance_q31 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR interpolator.\r
- * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_interpolate_f32(\r
- const arm_fir_interpolate_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the floating-point FIR interpolator.\r
- * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
- * @param[in] L upsample factor.\r
- * @param[in] numTaps number of filter coefficients in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficient buffer.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
- */\r
-\r
- arm_status arm_fir_interpolate_init_f32(\r
- arm_fir_interpolate_instance_f32 * S,\r
- uint8_t L,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
-\r
- } arm_biquad_cas_df1_32x64_ins_q31;\r
-\r
-\r
- /**\r
- * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cas_df1_32x64_q31(\r
- const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cas_df1_32x64_init_q31(\r
- arm_biquad_cas_df1_32x64_ins_q31 * S,\r
- uint8_t numStages,\r
- q31_t * pCoeffs,\r
- q63_t * pState,\r
- uint8_t postShift);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_stereo_df2T_instance_f32;\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
- } arm_biquad_cascade_df2T_instance_f64;\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] *S points to an instance of the filter data structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df2T_f32(\r
- const arm_biquad_cascade_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
- * @param[in] *S points to an instance of the filter data structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_stereo_df2T_f32(\r
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in] *S points to an instance of the filter data structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_biquad_cascade_df2T_f64(\r
- const arm_biquad_cascade_df2T_instance_f64 * S,\r
- float64_t * pSrc,\r
- float64_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_df2T_init_f32(\r
- arm_biquad_cascade_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_stereo_df2T_init_f32(\r
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
- uint8_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
- * @param[in,out] *S points to an instance of the filter data structure.\r
- * @param[in] numStages number of 2nd order stages in the filter.\r
- * @param[in] *pCoeffs points to the filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @return none\r
- */\r
-\r
- void arm_biquad_cascade_df2T_init_f64(\r
- arm_biquad_cascade_df2T_instance_f64 * S,\r
- uint8_t numStages,\r
- float64_t * pCoeffs,\r
- float64_t * pState);\r
-\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q15 FIR lattice filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 FIR lattice filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point FIR lattice filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of filter stages. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
- } arm_fir_lattice_instance_f32;\r
-\r
- /**\r
- * @brief Initialization function for the Q15 FIR lattice filter.\r
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] *pState points to the state buffer. The array is of length numStages.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_lattice_init_q15(\r
- arm_fir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pCoeffs,\r
- q15_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 FIR lattice filter.\r
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
- void arm_fir_lattice_q15(\r
- const arm_fir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q31 FIR lattice filter.\r
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] *pState points to the state buffer. The array is of length numStages.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_lattice_init_q31(\r
- arm_fir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pCoeffs,\r
- q31_t * pState);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 FIR lattice filter.\r
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_lattice_q31(\r
- const arm_fir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-/**\r
- * @brief Initialization function for the floating-point FIR lattice filter.\r
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] numStages number of filter stages.\r
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
- * @param[in] *pState points to the state buffer. The array is of length numStages.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_lattice_init_f32(\r
- arm_fir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pCoeffs,\r
- float32_t * pState);\r
-\r
- /**\r
- * @brief Processing function for the floating-point FIR lattice filter.\r
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_lattice_f32(\r
- const arm_fir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the floating-point IIR lattice filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numStages; /**< number of stages in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
- } arm_iir_lattice_instance_f32;\r
-\r
- /**\r
- * @brief Processing function for the floating-point IIR lattice filter.\r
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_f32(\r
- const arm_iir_lattice_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the floating-point IIR lattice filter.\r
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_init_f32(\r
- arm_iir_lattice_instance_f32 * S,\r
- uint16_t numStages,\r
- float32_t * pkCoeffs,\r
- float32_t * pvCoeffs,\r
- float32_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q31 IIR lattice filter.\r
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_q31(\r
- const arm_iir_lattice_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q31 IIR lattice filter.\r
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_init_q31(\r
- arm_iir_lattice_instance_q31 * S,\r
- uint16_t numStages,\r
- q31_t * pkCoeffs,\r
- q31_t * pvCoeffs,\r
- q31_t * pState,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Processing function for the Q15 IIR lattice filter.\r
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_q15(\r
- const arm_iir_lattice_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-/**\r
- * @brief Initialization function for the Q15 IIR lattice filter.\r
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
- * @param[in] numStages number of stages in the filter.\r
- * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
- * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
- * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
- * @param[in] blockSize number of samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_iir_lattice_init_q15(\r
- arm_iir_lattice_instance_q15 * S,\r
- uint16_t numStages,\r
- q15_t * pkCoeffs,\r
- q15_t * pvCoeffs,\r
- q15_t * pState,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point LMS filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that controls filter coefficient updates. */\r
- } arm_lms_instance_f32;\r
-\r
- /**\r
- * @brief Processing function for floating-point LMS filter.\r
- * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_f32(\r
- const arm_lms_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for floating-point LMS filter.\r
- * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to the coefficient buffer.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_init_f32(\r
- arm_lms_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 LMS filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
- } arm_lms_instance_q15;\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 LMS filter.\r
- * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to the coefficient buffer.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_init_q15(\r
- arm_lms_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
- /**\r
- * @brief Processing function for Q15 LMS filter.\r
- * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_q15(\r
- const arm_lms_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 LMS filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint32_t postShift; /**< bit shift applied to coefficients. */\r
-\r
- } arm_lms_instance_q31;\r
-\r
- /**\r
- * @brief Processing function for Q31 LMS filter.\r
- * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_q31(\r
- const arm_lms_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for Q31 LMS filter.\r
- * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to coefficient buffer.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_init_q31(\r
- arm_lms_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint32_t postShift);\r
-\r
- /**\r
- * @brief Instance structure for the floating-point normalized LMS filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- float32_t mu; /**< step size that control filter coefficient updates. */\r
- float32_t energy; /**< saves previous frame energy. */\r
- float32_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_f32;\r
-\r
- /**\r
- * @brief Processing function for floating-point normalized LMS filter.\r
- * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pRef,\r
- float32_t * pOut,\r
- float32_t * pErr,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for floating-point normalized LMS filter.\r
- * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to coefficient buffer.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_init_f32(\r
- arm_lms_norm_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- float32_t mu,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the Q31 normalized LMS filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q31_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
- q31_t energy; /**< saves previous frame energy. */\r
- q31_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q31;\r
-\r
- /**\r
- * @brief Processing function for Q31 normalized LMS filter.\r
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pRef,\r
- q31_t * pOut,\r
- q31_t * pErr,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for Q31 normalized LMS filter.\r
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to coefficient buffer.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_init_q31(\r
- arm_lms_norm_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- q31_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
- /**\r
- * @brief Instance structure for the Q15 normalized LMS filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< Number of coefficients in the filter. */\r
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
- q15_t mu; /**< step size that controls filter coefficient updates. */\r
- uint8_t postShift; /**< bit shift applied to coefficients. */\r
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
- q15_t energy; /**< saves previous frame energy. */\r
- q15_t x0; /**< saves previous input sample. */\r
- } arm_lms_norm_instance_q15;\r
-\r
- /**\r
- * @brief Processing function for Q15 normalized LMS filter.\r
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[in] *pRef points to the block of reference data.\r
- * @param[out] *pOut points to the block of output data.\r
- * @param[out] *pErr points to the block of error data.\r
- * @param[in] blockSize number of samples to process.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pRef,\r
- q15_t * pOut,\r
- q15_t * pErr,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for Q15 normalized LMS filter.\r
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
- * @param[in] numTaps number of filter coefficients.\r
- * @param[in] *pCoeffs points to coefficient buffer.\r
- * @param[in] *pState points to state buffer.\r
- * @param[in] mu step size that controls filter coefficient updates.\r
- * @param[in] blockSize number of samples to process.\r
- * @param[in] postShift bit shift applied to coefficients.\r
- * @return none.\r
- */\r
-\r
- void arm_lms_norm_init_q15(\r
- arm_lms_norm_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- q15_t mu,\r
- uint32_t blockSize,\r
- uint8_t postShift);\r
-\r
- /**\r
- * @brief Correlation of floating-point sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_f32(\r
- float32_t * pSrcA,\r
- uint32_t srcALen,\r
- float32_t * pSrcB,\r
- uint32_t srcBLen,\r
- float32_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @return none.\r
- */\r
- void arm_correlate_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_fast_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst);\r
-\r
-\r
-\r
- /**\r
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_fast_opt_q15(\r
- q15_t * pSrcA,\r
- uint32_t srcALen,\r
- q15_t * pSrcB,\r
- uint32_t srcBLen,\r
- q15_t * pDst,\r
- q15_t * pScratch);\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
- /**\r
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_fast_q31(\r
- q31_t * pSrcA,\r
- uint32_t srcALen,\r
- q31_t * pSrcB,\r
- uint32_t srcBLen,\r
- q31_t * pDst);\r
-\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_opt_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst,\r
- q15_t * pScratch1,\r
- q15_t * pScratch2);\r
-\r
-\r
- /**\r
- * @brief Correlation of Q7 sequences.\r
- * @param[in] *pSrcA points to the first input sequence.\r
- * @param[in] srcALen length of the first input sequence.\r
- * @param[in] *pSrcB points to the second input sequence.\r
- * @param[in] srcBLen length of the second input sequence.\r
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
- * @return none.\r
- */\r
-\r
- void arm_correlate_q7(\r
- q7_t * pSrcA,\r
- uint32_t srcALen,\r
- q7_t * pSrcB,\r
- uint32_t srcBLen,\r
- q7_t * pDst);\r
-\r
-\r
- /**\r
- * @brief Instance structure for the floating-point sparse FIR filter.\r
- */\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_f32;\r
-\r
- /**\r
- * @brief Instance structure for the Q31 sparse FIR filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q31;\r
-\r
- /**\r
- * @brief Instance structure for the Q15 sparse FIR filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q15;\r
-\r
- /**\r
- * @brief Instance structure for the Q7 sparse FIR filter.\r
- */\r
-\r
- typedef struct\r
- {\r
- uint16_t numTaps; /**< number of coefficients in the filter. */\r
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
- } arm_fir_sparse_instance_q7;\r
-\r
- /**\r
- * @brief Processing function for the floating-point sparse FIR filter.\r
- * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_sparse_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- float32_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the floating-point sparse FIR filter.\r
- * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] *pCoeffs points to the array of filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] *pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- * @return none\r
- */\r
-\r
- void arm_fir_sparse_init_f32(\r
- arm_fir_sparse_instance_f32 * S,\r
- uint16_t numTaps,\r
- float32_t * pCoeffs,\r
- float32_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q31 sparse FIR filter.\r
- * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_sparse_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- q31_t * pScratchIn,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q31 sparse FIR filter.\r
- * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] *pCoeffs points to the array of filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] *pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- * @return none\r
- */\r
-\r
- void arm_fir_sparse_init_q31(\r
- arm_fir_sparse_instance_q31 * S,\r
- uint16_t numTaps,\r
- q31_t * pCoeffs,\r
- q31_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q15 sparse FIR filter.\r
- * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_sparse_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- q15_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Initialization function for the Q15 sparse FIR filter.\r
- * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] *pCoeffs points to the array of filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] *pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- * @return none\r
- */\r
-\r
- void arm_fir_sparse_init_q15(\r
- arm_fir_sparse_instance_q15 * S,\r
- uint16_t numTaps,\r
- q15_t * pCoeffs,\r
- q15_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Processing function for the Q7 sparse FIR filter.\r
- * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] *pSrc points to the block of input data.\r
- * @param[out] *pDst points to the block of output data\r
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
- * @param[in] blockSize number of input samples to process per call.\r
- * @return none.\r
- */\r
-\r
- void arm_fir_sparse_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- q7_t * pSrc,\r
- q7_t * pDst,\r
- q7_t * pScratchIn,\r
- q31_t * pScratchOut,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Initialization function for the Q7 sparse FIR filter.\r
- * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
- * @param[in] numTaps number of nonzero coefficients in the filter.\r
- * @param[in] *pCoeffs points to the array of filter coefficients.\r
- * @param[in] *pState points to the state buffer.\r
- * @param[in] *pTapDelay points to the array of offset times.\r
- * @param[in] maxDelay maximum offset time supported.\r
- * @param[in] blockSize number of samples that will be processed per block.\r
- * @return none\r
- */\r
-\r
- void arm_fir_sparse_init_q7(\r
- arm_fir_sparse_instance_q7 * S,\r
- uint16_t numTaps,\r
- q7_t * pCoeffs,\r
- q7_t * pState,\r
- int32_t * pTapDelay,\r
- uint16_t maxDelay,\r
- uint32_t blockSize);\r
-\r
-\r
- /*\r
- * @brief Floating-point sin_cos function.\r
- * @param[in] theta input value in degrees\r
- * @param[out] *pSinVal points to the processed sine output.\r
- * @param[out] *pCosVal points to the processed cos output.\r
- * @return none.\r
- */\r
-\r
- void arm_sin_cos_f32(\r
- float32_t theta,\r
- float32_t * pSinVal,\r
- float32_t * pCcosVal);\r
-\r
- /*\r
- * @brief Q31 sin_cos function.\r
- * @param[in] theta scaled input value in degrees\r
- * @param[out] *pSinVal points to the processed sine output.\r
- * @param[out] *pCosVal points to the processed cosine output.\r
- * @return none.\r
- */\r
-\r
- void arm_sin_cos_q31(\r
- q31_t theta,\r
- q31_t * pSinVal,\r
- q31_t * pCosVal);\r
-\r
-\r
- /**\r
- * @brief Floating-point complex conjugate.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_conj_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex conjugate.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_conj_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q15 complex conjugate.\r
- * @param[in] *pSrc points to the input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_conj_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
-\r
- /**\r
- * @brief Floating-point complex magnitude squared\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_squared_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex magnitude squared\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_squared_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q15 complex magnitude squared\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_squared_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup PID PID Motor Control\r
- *\r
- * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
- * loop mechanism widely used in industrial control systems.\r
- * A PID controller is the most commonly used type of feedback controller.\r
- *\r
- * This set of functions implements (PID) controllers\r
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
- * of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
- * is the input sample value. The functions return the output value.\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
- * A0 = Kp + Ki + Kd\r
- * A1 = (-Kp ) - (2 * Kd )\r
- * A2 = Kd </pre>\r
- *\r
- * \par\r
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
- *\r
- * \par\r
- * \image html PID.gif "Proportional Integral Derivative Controller"\r
- *\r
- * \par\r
- * The PID controller calculates an "error" value as the difference between\r
- * the measured output and the reference input.\r
- * The controller attempts to minimize the error by adjusting the process control inputs.\r
- * The proportional value determines the reaction to the current error,\r
- * the integral value determines the reaction based on the sum of recent errors,\r
- * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
- *\r
- * \par Instance Structure\r
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
- * A separate instance structure must be defined for each PID Controller.\r
- * There are separate instance structure declarations for each of the 3 supported data types.\r
- *\r
- * \par Reset Functions\r
- * There is also an associated reset function for each data type which clears the state array.\r
- *\r
- * \par Initialization Functions\r
- * There is also an associated initialization function for each data type.\r
- * The initialization function performs the following operations:\r
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
- * - Zeros out the values in the state buffer.\r
- *\r
- * \par\r
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
- *\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup PID\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point PID Control.\r
- * @param[in,out] *S is an instance of the floating-point PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- */\r
-\r
-\r
- static __INLINE float32_t arm_pid_f32(\r
- arm_pid_instance_f32 * S,\r
- float32_t in)\r
- {\r
- float32_t out;\r
-\r
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
- out = (S->A0 * in) +\r
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @brief Process function for the Q31 PID Control.\r
- * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 64-bit accumulator.\r
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
- * Thus, if the accumulator result overflows it wraps around rather than clip.\r
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
- */\r
-\r
- static __INLINE q31_t arm_pid_q31(\r
- arm_pid_instance_q31 * S,\r
- q31_t in)\r
- {\r
- q63_t acc;\r
- q31_t out;\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q63_t) S->A0 * in;\r
-\r
- /* acc += A1 * x[n-1] */\r
- acc += (q63_t) S->A1 * S->state[0];\r
-\r
- /* acc += A2 * x[n-2] */\r
- acc += (q63_t) S->A2 * S->state[1];\r
-\r
- /* convert output to 1.31 format to add y[n-1] */\r
- out = (q31_t) (acc >> 31u);\r
-\r
- /* out += y[n-1] */\r
- out += S->state[2];\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @brief Process function for the Q15 PID Control.\r
- * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
- * @param[in] in input sample to process\r
- * @return out processed output sample.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using a 64-bit internal accumulator.\r
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
- */\r
-\r
- static __INLINE q15_t arm_pid_q15(\r
- arm_pid_instance_q15 * S,\r
- q15_t in)\r
- {\r
- q63_t acc;\r
- q15_t out;\r
-\r
-#ifndef ARM_MATH_CM0_FAMILY\r
- __SIMD32_TYPE *vstate;\r
-\r
- /* Implementation of PID controller */\r
-\r
- /* acc = A0 * x[n] */\r
- acc = (q31_t) __SMUAD(S->A0, in);\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- vstate = __SIMD32_CONST(S->state);\r
- acc = __SMLALD(S->A1, (q31_t) *vstate, acc);\r
-\r
-#else\r
- /* acc = A0 * x[n] */\r
- acc = ((q31_t) S->A0) * in;\r
-\r
- /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
- acc += (q31_t) S->A1 * S->state[0];\r
- acc += (q31_t) S->A2 * S->state[1];\r
-\r
-#endif\r
-\r
- /* acc += y[n-1] */\r
- acc += (q31_t) S->state[2] << 15;\r
-\r
- /* saturate the output */\r
- out = (q15_t) (__SSAT((acc >> 15), 16));\r
-\r
- /* Update state */\r
- S->state[1] = S->state[0];\r
- S->state[0] = in;\r
- S->state[2] = out;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- * @} end of PID group\r
- */\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] *src points to the instance of the input floating-point matrix structure.\r
- * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
-\r
- arm_status arm_mat_inverse_f32(\r
- const arm_matrix_instance_f32 * src,\r
- arm_matrix_instance_f32 * dst);\r
-\r
-\r
- /**\r
- * @brief Floating-point matrix inverse.\r
- * @param[in] *src points to the instance of the input floating-point matrix structure.\r
- * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
- */\r
-\r
- arm_status arm_mat_inverse_f64(\r
- const arm_matrix_instance_f64 * src,\r
- arm_matrix_instance_f64 * dst);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
-\r
- /**\r
- * @defgroup clarke Vector Clarke Transform\r
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
- * \image html clarke.gif Stator current space vector and its components in (a,b).\r
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeFormula.gif\r
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup clarke\r
- * @{\r
- */\r
-\r
- /**\r
- *\r
- * @brief Floating-point Clarke transform\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
- * @return none.\r
- */\r
-\r
- static __INLINE void arm_clarke_f32(\r
- float32_t Ia,\r
- float32_t Ib,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
- *pIbeta =\r
- ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
-\r
- }\r
-\r
- /**\r
- * @brief Clarke transform for Q31 version\r
- * @param[in] Ia input three-phase coordinate <code>a</code>\r
- * @param[in] Ib input three-phase coordinate <code>b</code>\r
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
- * @return none.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
-\r
- static __INLINE void arm_clarke_q31(\r
- q31_t Ia,\r
- q31_t Ib,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
- *pIalpha = Ia;\r
-\r
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
-\r
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
-\r
- /* pIbeta is calculated by adding the intermediate products */\r
- *pIbeta = __QADD(product1, product2);\r
- }\r
-\r
- /**\r
- * @} end of clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q31 vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_q7_to_q31(\r
- q7_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_clarke Vector Inverse Clarke Transform\r
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html clarkeInvFormula.gif\r
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Clarke transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_clarke\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Clarke transform\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
- * @return none.\r
- */\r
-\r
-\r
- static __INLINE void arm_inv_clarke_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pIa,\r
- float32_t * pIb)\r
- {\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
- *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
-\r
- }\r
-\r
- /**\r
- * @brief Inverse Clarke transform for Q31 version\r
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
- * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
- * @return none.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the subtraction, hence there is no risk of overflow.\r
- */\r
-\r
- static __INLINE void arm_inv_clarke_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pIa,\r
- q31_t * pIb)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
-\r
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
- *pIa = Ialpha;\r
-\r
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
-\r
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
-\r
- /* pIb is calculated by subtracting the products */\r
- *pIb = __QSUB(product2, product1);\r
-\r
- }\r
-\r
- /**\r
- * @} end of inv_clarke group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to Q15 vector.\r
- * @param[in] *pSrc input pointer\r
- * @param[out] *pDst output pointer\r
- * @param[in] blockSize number of samples to process\r
- * @return none.\r
- */\r
- void arm_q7_to_q15(\r
- q7_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup park Vector Park Transform\r
- *\r
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
- * from the stationary to the moving reference frame and control the spatial relationship between\r
- * the stator vector current and rotor flux vector.\r
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
- * current vector and the relationship from the two reference frames:\r
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkFormula.gif\r
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Park transform\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] *pId points to output rotor reference frame d\r
- * @param[out] *pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- * @return none.\r
- *\r
- * The function implements the forward Park transform.\r
- *\r
- */\r
-\r
- static __INLINE void arm_park_f32(\r
- float32_t Ialpha,\r
- float32_t Ibeta,\r
- float32_t * pId,\r
- float32_t * pIq,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
- *pId = Ialpha * cosVal + Ibeta * sinVal;\r
-\r
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
-\r
- }\r
-\r
- /**\r
- * @brief Park transform for Q31 version\r
- * @param[in] Ialpha input two-phase vector coordinate alpha\r
- * @param[in] Ibeta input two-phase vector coordinate beta\r
- * @param[out] *pId points to output rotor reference frame d\r
- * @param[out] *pIq points to output rotor reference frame q\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- * @return none.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
- */\r
-\r
-\r
- static __INLINE void arm_park_q31(\r
- q31_t Ialpha,\r
- q31_t Ibeta,\r
- q31_t * pId,\r
- q31_t * pIq,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Ialpha * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Ialpha * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Ibeta * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
-\r
- /* Calculate pId by adding the two intermediate products 1 and 2 */\r
- *pId = __QADD(product1, product2);\r
-\r
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
- *pIq = __QSUB(product4, product3);\r
- }\r
-\r
- /**\r
- * @} end of park group\r
- */\r
-\r
- /**\r
- * @brief Converts the elements of the Q7 vector to floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q7_to_float(\r
- q7_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupController\r
- */\r
-\r
- /**\r
- * @defgroup inv_park Vector Inverse Park transform\r
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
- *\r
- * The function operates on a single sample of data and each call to the function returns the processed output.\r
- * The library provides separate functions for Q31 and floating-point data types.\r
- * \par Algorithm\r
- * \image html parkInvFormula.gif\r
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
- * cosine and sine values of theta (rotor flux position).\r
- * \par Fixed-Point Behavior\r
- * Care must be taken when using the Q31 version of the Park transform.\r
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
- * Refer to the function specific documentation below for usage guidelines.\r
- */\r
-\r
- /**\r
- * @addtogroup inv_park\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point Inverse Park transform\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- * @return none.\r
- */\r
-\r
- static __INLINE void arm_inv_park_f32(\r
- float32_t Id,\r
- float32_t Iq,\r
- float32_t * pIalpha,\r
- float32_t * pIbeta,\r
- float32_t sinVal,\r
- float32_t cosVal)\r
- {\r
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
- *pIalpha = Id * cosVal - Iq * sinVal;\r
-\r
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
- *pIbeta = Id * sinVal + Iq * cosVal;\r
-\r
- }\r
-\r
-\r
- /**\r
- * @brief Inverse Park transform for Q31 version\r
- * @param[in] Id input coordinate of rotor reference frame d\r
- * @param[in] Iq input coordinate of rotor reference frame q\r
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
- * @param[in] sinVal sine value of rotation angle theta\r
- * @param[in] cosVal cosine value of rotation angle theta\r
- * @return none.\r
- *\r
- * <b>Scaling and Overflow Behavior:</b>\r
- * \par\r
- * The function is implemented using an internal 32-bit accumulator.\r
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
- * There is saturation on the addition, hence there is no risk of overflow.\r
- */\r
-\r
-\r
- static __INLINE void arm_inv_park_q31(\r
- q31_t Id,\r
- q31_t Iq,\r
- q31_t * pIalpha,\r
- q31_t * pIbeta,\r
- q31_t sinVal,\r
- q31_t cosVal)\r
- {\r
- q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
- q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
-\r
- /* Intermediate product is calculated by (Id * cosVal) */\r
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * sinVal) */\r
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
-\r
-\r
- /* Intermediate product is calculated by (Id * sinVal) */\r
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
-\r
- /* Intermediate product is calculated by (Iq * cosVal) */\r
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
-\r
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
- *pIalpha = __QSUB(product1, product2);\r
-\r
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
- *pIbeta = __QADD(product4, product3);\r
-\r
- }\r
-\r
- /**\r
- * @} end of Inverse park group\r
- */\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q31_to_float(\r
- q31_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup LinearInterpolate Linear Interpolation\r
- *\r
- * Linear interpolation is a method of curve fitting using linear polynomials.\r
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
- *\r
- * \par\r
- * \image html LinearInterp.gif "Linear interpolation"\r
- *\r
- * \par\r
- * A Linear Interpolate function calculates an output value(y), for the input(x)\r
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
- *\r
- * \par Algorithm:\r
- * <pre>\r
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
- * where x0, x1 are nearest values of input x\r
- * y0, y1 are nearest values to output y\r
- * </pre>\r
- *\r
- * \par\r
- * This set of functions implements Linear interpolation process\r
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
- * sample of data and each call to the function returns a single processed value.\r
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
- * <code>x</code> is the input sample value. The functions returns the output value.\r
- *\r
- * \par\r
- * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
- * if x is below input range and returns last value of table if x is above range.\r
- */\r
-\r
- /**\r
- * @addtogroup LinearInterpolate\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Process function for the floating-point Linear Interpolation Function.\r
- * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
- * @param[in] x input sample to process\r
- * @return y processed output sample.\r
- *\r
- */\r
-\r
- static __INLINE float32_t arm_linear_interp_f32(\r
- arm_linear_interp_instance_f32 * S,\r
- float32_t x)\r
- {\r
-\r
- float32_t y;\r
- float32_t x0, x1; /* Nearest input values */\r
- float32_t y0, y1; /* Nearest output values */\r
- float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
- int32_t i; /* Index variable */\r
- float32_t *pYData = S->pYData; /* pointer to output table */\r
-\r
- /* Calculation of index */\r
- i = (int32_t) ((x - S->x1) / xSpacing);\r
-\r
- if(i < 0)\r
- {\r
- /* Iniatilize output for below specified range as least output value of table */\r
- y = pYData[0];\r
- }\r
- else if((uint32_t)i >= S->nValues)\r
- {\r
- /* Iniatilize output for above specified range as last output value of table */\r
- y = pYData[S->nValues - 1];\r
- }\r
- else\r
- {\r
- /* Calculation of nearest input values */\r
- x0 = S->x1 + i * xSpacing;\r
- x1 = S->x1 + (i + 1) * xSpacing;\r
-\r
- /* Read of nearest output values */\r
- y0 = pYData[i];\r
- y1 = pYData[i + 1];\r
-\r
- /* Calculation of output */\r
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
-\r
- }\r
-\r
- /* returns output value */\r
- return (y);\r
- }\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q31 Linear Interpolation Function.\r
- * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
-\r
-\r
- static __INLINE q31_t arm_linear_interp_q31(\r
- q31_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q31_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & 0xFFF00000) >> 20);\r
-\r
- if(index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if(index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left by 11 to keep fract in 1.31 format */\r
- fract = (x & 0x000FFFFF) << 11;\r
-\r
- /* Read two nearest output values from the index in 1.31(q31) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1u];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
-\r
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
-\r
- /* Convert y to 1.31 format */\r
- return (y << 1u);\r
-\r
- }\r
-\r
- }\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q15 Linear Interpolation Function.\r
- * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- *\r
- */\r
-\r
-\r
- static __INLINE q15_t arm_linear_interp_q15(\r
- q15_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q63_t y; /* output */\r
- q15_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- int32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- index = ((x & 0xFFF00000) >> 20u);\r
-\r
- if(index >= (int32_t)(nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else if(index < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- else\r
- {\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1u];\r
-\r
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
- y = ((q63_t) y0 * (0xFFFFF - fract));\r
-\r
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
- y += ((q63_t) y1 * (fract));\r
-\r
- /* convert y to 1.15 format */\r
- return (y >> 20);\r
- }\r
-\r
-\r
- }\r
-\r
- /**\r
- *\r
- * @brief Process function for the Q7 Linear Interpolation Function.\r
- * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
- * @param[in] x input sample to process\r
- * @param[in] nValues number of table values\r
- * @return y processed output sample.\r
- *\r
- * \par\r
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
- * This function can support maximum of table size 2^12.\r
- */\r
-\r
-\r
- static __INLINE q7_t arm_linear_interp_q7(\r
- q7_t * pYData,\r
- q31_t x,\r
- uint32_t nValues)\r
- {\r
- q31_t y; /* output */\r
- q7_t y0, y1; /* Nearest output values */\r
- q31_t fract; /* fractional part */\r
- uint32_t index; /* Index to read nearest output values */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- if (x < 0)\r
- {\r
- return (pYData[0]);\r
- }\r
- index = (x >> 20) & 0xfff;\r
-\r
-\r
- if(index >= (nValues - 1))\r
- {\r
- return (pYData[nValues - 1]);\r
- }\r
- else\r
- {\r
-\r
- /* 20 bits for the fractional part */\r
- /* fract is in 12.20 format */\r
- fract = (x & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index and are in 1.7(q7) format */\r
- y0 = pYData[index];\r
- y1 = pYData[index + 1u];\r
-\r
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
- y = ((y0 * (0xFFFFF - fract)));\r
-\r
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
- y += (y1 * fract);\r
-\r
- /* convert y to 1.7(q7) format */\r
- return (y >> 20u);\r
-\r
- }\r
-\r
- }\r
- /**\r
- * @} end of LinearInterpolate group\r
- */\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return sin(x).\r
- */\r
-\r
- float32_t arm_sin_f32(\r
- float32_t x);\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
-\r
- q31_t arm_sin_q31(\r
- q31_t x);\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return sin(x).\r
- */\r
-\r
- q15_t arm_sin_q15(\r
- q15_t x);\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
- * @param[in] x input value in radians.\r
- * @return cos(x).\r
- */\r
-\r
- float32_t arm_cos_f32(\r
- float32_t x);\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
-\r
- q31_t arm_cos_q31(\r
- q31_t x);\r
-\r
- /**\r
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
- * @param[in] x Scaled input value in radians.\r
- * @return cos(x).\r
- */\r
-\r
- q15_t arm_cos_q15(\r
- q15_t x);\r
-\r
-\r
- /**\r
- * @ingroup groupFastMath\r
- */\r
-\r
-\r
- /**\r
- * @defgroup SQRT Square Root\r
- *\r
- * Computes the square root of a number.\r
- * There are separate functions for Q15, Q31, and floating-point data types.\r
- * The square root function is computed using the Newton-Raphson algorithm.\r
- * This is an iterative algorithm of the form:\r
- * <pre>\r
- * x1 = x0 - f(x0)/f'(x0)\r
- * </pre>\r
- * where <code>x1</code> is the current estimate,\r
- * <code>x0</code> is the previous estimate, and\r
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
- * For the square root function, the algorithm reduces to:\r
- * <pre>\r
- * x0 = in/2 [initial guess]\r
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
- * </pre>\r
- */\r
-\r
-\r
- /**\r
- * @addtogroup SQRT\r
- * @{\r
- */\r
-\r
- /**\r
- * @brief Floating-point square root function.\r
- * @param[in] in input value.\r
- * @param[out] *pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
-\r
- static __INLINE arm_status arm_sqrt_f32(\r
- float32_t in,\r
- float32_t * pOut)\r
- {\r
- if(in > 0)\r
- {\r
-\r
-// #if __FPU_USED\r
-#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
- *pOut = __sqrtf(in);\r
-#else\r
- *pOut = sqrtf(in);\r
-#endif\r
-\r
- return (ARM_MATH_SUCCESS);\r
- }\r
- else\r
- {\r
- *pOut = 0.0f;\r
- return (ARM_MATH_ARGUMENT_ERROR);\r
- }\r
-\r
- }\r
-\r
-\r
- /**\r
- * @brief Q31 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
- * @param[out] *pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q31(\r
- q31_t in,\r
- q31_t * pOut);\r
-\r
- /**\r
- * @brief Q15 square root function.\r
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
- * @param[out] *pOut square root of input value.\r
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
- * <code>in</code> is negative value and returns zero output for negative values.\r
- */\r
- arm_status arm_sqrt_q15(\r
- q15_t in,\r
- q15_t * pOut);\r
-\r
- /**\r
- * @} end of SQRT group\r
- */\r
-\r
-\r
-\r
-\r
-\r
-\r
- /**\r
- * @brief floating-point Circular write function.\r
- */\r
-\r
- static __INLINE void arm_circularWrite_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const int32_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief floating-point Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_f32(\r
- int32_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- int32_t * dst,\r
- int32_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (int32_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
- /**\r
- * @brief Q15 Circular write function.\r
- */\r
-\r
- static __INLINE void arm_circularWrite_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q15_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief Q15 Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_q15(\r
- q15_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q15_t * dst,\r
- q15_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (q15_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Q7 Circular write function.\r
- */\r
-\r
- static __INLINE void arm_circularWrite_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- uint16_t * writeOffset,\r
- int32_t bufferInc,\r
- const q7_t * src,\r
- int32_t srcInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0u;\r
- int32_t wOffset;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location where the input samples to be copied */\r
- wOffset = *writeOffset;\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the input sample to the circular buffer */\r
- circBuffer[wOffset] = *src;\r
-\r
- /* Update the input pointer */\r
- src += srcInc;\r
-\r
- /* Circularly update wOffset. Watch out for positive and negative value */\r
- wOffset += bufferInc;\r
- if(wOffset >= L)\r
- wOffset -= L;\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *writeOffset = wOffset;\r
- }\r
-\r
-\r
-\r
- /**\r
- * @brief Q7 Circular Read function.\r
- */\r
- static __INLINE void arm_circularRead_q7(\r
- q7_t * circBuffer,\r
- int32_t L,\r
- int32_t * readOffset,\r
- int32_t bufferInc,\r
- q7_t * dst,\r
- q7_t * dst_base,\r
- int32_t dst_length,\r
- int32_t dstInc,\r
- uint32_t blockSize)\r
- {\r
- uint32_t i = 0;\r
- int32_t rOffset, dst_end;\r
-\r
- /* Copy the value of Index pointer that points\r
- * to the current location from where the input samples to be read */\r
- rOffset = *readOffset;\r
-\r
- dst_end = (int32_t) (dst_base + dst_length);\r
-\r
- /* Loop over the blockSize */\r
- i = blockSize;\r
-\r
- while(i > 0u)\r
- {\r
- /* copy the sample from the circular buffer to the destination buffer */\r
- *dst = circBuffer[rOffset];\r
-\r
- /* Update the input pointer */\r
- dst += dstInc;\r
-\r
- if(dst == (q7_t *) dst_end)\r
- {\r
- dst = dst_base;\r
- }\r
-\r
- /* Circularly update rOffset. Watch out for positive and negative value */\r
- rOffset += bufferInc;\r
-\r
- if(rOffset >= L)\r
- {\r
- rOffset -= L;\r
- }\r
-\r
- /* Decrement the loop counter */\r
- i--;\r
- }\r
-\r
- /* Update the index pointer */\r
- *readOffset = rOffset;\r
- }\r
-\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_power_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_power_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_power_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q63_t * pResult);\r
-\r
- /**\r
- * @brief Sum of the squares of the elements of a Q7 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_power_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
- /**\r
- * @brief Mean value of a Q7 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_mean_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult);\r
-\r
- /**\r
- * @brief Mean value of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
- void arm_mean_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
- /**\r
- * @brief Mean value of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
- void arm_mean_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
- /**\r
- * @brief Mean value of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
- void arm_mean_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
- /**\r
- * @brief Variance of the elements of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_var_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
- /**\r
- * @brief Variance of the elements of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_var_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
- /**\r
- * @brief Variance of the elements of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_var_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_rms_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_rms_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
- /**\r
- * @brief Root Mean Square of the elements of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_rms_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_std_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult);\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_std_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult);\r
-\r
- /**\r
- * @brief Standard deviation of the elements of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output value.\r
- * @return none.\r
- */\r
-\r
- void arm_std_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult);\r
-\r
- /**\r
- * @brief Floating-point complex magnitude\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_f32(\r
- float32_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex magnitude\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_q31(\r
- q31_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q15 complex magnitude\r
- * @param[in] *pSrc points to the complex input vector\r
- * @param[out] *pDst points to the real output vector\r
- * @param[in] numSamples number of complex samples in the input vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mag_q15(\r
- q15_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q15 complex dot product\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] *realResult real part of the result returned here\r
- * @param[out] *imagResult imaginary part of the result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_dot_prod_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- uint32_t numSamples,\r
- q31_t * realResult,\r
- q31_t * imagResult);\r
-\r
- /**\r
- * @brief Q31 complex dot product\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] *realResult real part of the result returned here\r
- * @param[out] *imagResult imaginary part of the result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_dot_prod_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- uint32_t numSamples,\r
- q63_t * realResult,\r
- q63_t * imagResult);\r
-\r
- /**\r
- * @brief Floating-point complex dot product\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @param[out] *realResult real part of the result returned here\r
- * @param[out] *imagResult imaginary part of the result returned here\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_dot_prod_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- uint32_t numSamples,\r
- float32_t * realResult,\r
- float32_t * imagResult);\r
-\r
- /**\r
- * @brief Q15 complex-by-real multiplication\r
- * @param[in] *pSrcCmplx points to the complex input vector\r
- * @param[in] *pSrcReal points to the real input vector\r
- * @param[out] *pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_real_q15(\r
- q15_t * pSrcCmplx,\r
- q15_t * pSrcReal,\r
- q15_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex-by-real multiplication\r
- * @param[in] *pSrcCmplx points to the complex input vector\r
- * @param[in] *pSrcReal points to the real input vector\r
- * @param[out] *pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_real_q31(\r
- q31_t * pSrcCmplx,\r
- q31_t * pSrcReal,\r
- q31_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Floating-point complex-by-real multiplication\r
- * @param[in] *pSrcCmplx points to the complex input vector\r
- * @param[in] *pSrcReal points to the real input vector\r
- * @param[out] *pCmplxDst points to the complex output vector\r
- * @param[in] numSamples number of samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_real_f32(\r
- float32_t * pSrcCmplx,\r
- float32_t * pSrcReal,\r
- float32_t * pCmplxDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Minimum value of a Q7 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *result is output pointer\r
- * @param[in] index is the array index of the minimum value in the input buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_min_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * result,\r
- uint32_t * index);\r
-\r
- /**\r
- * @brief Minimum value of a Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output pointer\r
- * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_min_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
- /**\r
- * @brief Minimum value of a Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output pointer\r
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
- * @return none.\r
- */\r
- void arm_min_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
- /**\r
- * @brief Minimum value of a floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @param[out] *pResult is output pointer\r
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
- * @return none.\r
- */\r
-\r
- void arm_min_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-/**\r
- * @brief Maximum value of a Q7 vector.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] *pResult maximum value returned here\r
- * @param[out] *pIndex index of maximum value returned here\r
- * @return none.\r
- */\r
-\r
- void arm_max_q7(\r
- q7_t * pSrc,\r
- uint32_t blockSize,\r
- q7_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-/**\r
- * @brief Maximum value of a Q15 vector.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] *pResult maximum value returned here\r
- * @param[out] *pIndex index of maximum value returned here\r
- * @return none.\r
- */\r
-\r
- void arm_max_q15(\r
- q15_t * pSrc,\r
- uint32_t blockSize,\r
- q15_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-/**\r
- * @brief Maximum value of a Q31 vector.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] *pResult maximum value returned here\r
- * @param[out] *pIndex index of maximum value returned here\r
- * @return none.\r
- */\r
-\r
- void arm_max_q31(\r
- q31_t * pSrc,\r
- uint32_t blockSize,\r
- q31_t * pResult,\r
- uint32_t * pIndex);\r
-\r
-/**\r
- * @brief Maximum value of a floating-point vector.\r
- * @param[in] *pSrc points to the input buffer\r
- * @param[in] blockSize length of the input vector\r
- * @param[out] *pResult maximum value returned here\r
- * @param[out] *pIndex index of maximum value returned here\r
- * @return none.\r
- */\r
-\r
- void arm_max_f32(\r
- float32_t * pSrc,\r
- uint32_t blockSize,\r
- float32_t * pResult,\r
- uint32_t * pIndex);\r
-\r
- /**\r
- * @brief Q15 complex-by-complex multiplication\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_cmplx_q15(\r
- q15_t * pSrcA,\r
- q15_t * pSrcB,\r
- q15_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Q31 complex-by-complex multiplication\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_cmplx_q31(\r
- q31_t * pSrcA,\r
- q31_t * pSrcB,\r
- q31_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Floating-point complex-by-complex multiplication\r
- * @param[in] *pSrcA points to the first input vector\r
- * @param[in] *pSrcB points to the second input vector\r
- * @param[out] *pDst points to the output vector\r
- * @param[in] numSamples number of complex samples in each vector\r
- * @return none.\r
- */\r
-\r
- void arm_cmplx_mult_cmplx_f32(\r
- float32_t * pSrcA,\r
- float32_t * pSrcB,\r
- float32_t * pDst,\r
- uint32_t numSamples);\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q31 vector.\r
- * @param[in] *pSrc points to the floating-point input vector\r
- * @param[out] *pDst points to the Q31 output vector\r
- * @param[in] blockSize length of the input vector\r
- * @return none.\r
- */\r
- void arm_float_to_q31(\r
- float32_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q15 vector.\r
- * @param[in] *pSrc points to the floating-point input vector\r
- * @param[out] *pDst points to the Q15 output vector\r
- * @param[in] blockSize length of the input vector\r
- * @return none\r
- */\r
- void arm_float_to_q15(\r
- float32_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Converts the elements of the floating-point vector to Q7 vector.\r
- * @param[in] *pSrc points to the floating-point input vector\r
- * @param[out] *pDst points to the Q7 output vector\r
- * @param[in] blockSize length of the input vector\r
- * @return none\r
- */\r
- void arm_float_to_q7(\r
- float32_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q15 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q31_to_q15(\r
- q31_t * pSrc,\r
- q15_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Converts the elements of the Q31 vector to Q7 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q31_to_q7(\r
- q31_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to floating-point vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q15_to_float(\r
- q15_t * pSrc,\r
- float32_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q31 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q15_to_q31(\r
- q15_t * pSrc,\r
- q31_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @brief Converts the elements of the Q15 vector to Q7 vector.\r
- * @param[in] *pSrc is input pointer\r
- * @param[out] *pDst is output pointer\r
- * @param[in] blockSize is the number of samples to process\r
- * @return none.\r
- */\r
- void arm_q15_to_q7(\r
- q15_t * pSrc,\r
- q7_t * pDst,\r
- uint32_t blockSize);\r
-\r
-\r
- /**\r
- * @ingroup groupInterpolation\r
- */\r
-\r
- /**\r
- * @defgroup BilinearInterpolate Bilinear Interpolation\r
- *\r
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
- * determines values between the grid points.\r
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
- * Bilinear interpolation is often used in image processing to rescale images.\r
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
- *\r
- * <b>Algorithm</b>\r
- * \par\r
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
- * For floating-point, the instance structure is defined as:\r
- * <pre>\r
- * typedef struct\r
- * {\r
- * uint16_t numRows;\r
- * uint16_t numCols;\r
- * float32_t *pData;\r
- * } arm_bilinear_interp_instance_f32;\r
- * </pre>\r
- *\r
- * \par\r
- * where <code>numRows</code> specifies the number of rows in the table;\r
- * <code>numCols</code> specifies the number of columns in the table;\r
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
- *\r
- * \par\r
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
- * <pre>\r
- * XF = floor(x)\r
- * YF = floor(y)\r
- * </pre>\r
- * \par\r
- * The interpolated output point is computed as:\r
- * <pre>\r
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
- * </pre>\r
- * Note that the coordinates (x, y) contain integer and fractional components.\r
- * The integer components specify which portion of the table to use while the\r
- * fractional components control the interpolation processor.\r
- *\r
- * \par\r
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
- */\r
-\r
- /**\r
- * @addtogroup BilinearInterpolate\r
- * @{\r
- */\r
-\r
- /**\r
- *\r
- * @brief Floating-point bilinear interpolation.\r
- * @param[in,out] *S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate.\r
- * @param[in] Y interpolation coordinate.\r
- * @return out interpolated value.\r
- */\r
-\r
-\r
- static __INLINE float32_t arm_bilinear_interp_f32(\r
- const arm_bilinear_interp_instance_f32 * S,\r
- float32_t X,\r
- float32_t Y)\r
- {\r
- float32_t out;\r
- float32_t f00, f01, f10, f11;\r
- float32_t *pData = S->pData;\r
- int32_t xIndex, yIndex, index;\r
- float32_t xdiff, ydiff;\r
- float32_t b1, b2, b3, b4;\r
-\r
- xIndex = (int32_t) X;\r
- yIndex = (int32_t) Y;\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0\r
- || yIndex > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* Calculation of index for two nearest points in X-direction */\r
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in X-direction */\r
- f00 = pData[index];\r
- f01 = pData[index + 1];\r
-\r
- /* Calculation of index for two nearest points in Y-direction */\r
- index = (xIndex - 1) + (yIndex) * S->numCols;\r
-\r
-\r
- /* Read two nearest points in Y-direction */\r
- f10 = pData[index];\r
- f11 = pData[index + 1];\r
-\r
- /* Calculation of intermediate values */\r
- b1 = f00;\r
- b2 = f01 - f00;\r
- b3 = f10 - f00;\r
- b4 = f00 - f01 - f10 + f11;\r
-\r
- /* Calculation of fractional part in X */\r
- xdiff = X - xIndex;\r
-\r
- /* Calculation of fractional part in Y */\r
- ydiff = Y - yIndex;\r
-\r
- /* Calculation of bi-linear interpolated output */\r
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
-\r
- /* return to application */\r
- return (out);\r
-\r
- }\r
-\r
- /**\r
- *\r
- * @brief Q31 bilinear interpolation.\r
- * @param[in,out] *S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
-\r
- static __INLINE q31_t arm_bilinear_interp_q31(\r
- arm_bilinear_interp_instance_q31 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q31_t out; /* Temporary output */\r
- q31_t acc = 0; /* output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q31_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q31_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & 0xFFF00000) >> 20u);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & 0xFFF00000) >> 20u);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left xfract by 11 to keep 1.31 format */\r
- xfract = (X & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + nCols * (cI)];\r
- x2 = pYData[(rI) + nCols * (cI) + 1u];\r
-\r
- /* 20 bits for the fractional part */\r
- /* shift left yfract by 11 to keep 1.31 format */\r
- yfract = (Y & 0x000FFFFF) << 11u;\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + nCols * (cI + 1)];\r
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
-\r
- /* Convert acc to 1.31(q31) format */\r
- return (acc << 2u);\r
-\r
- }\r
-\r
- /**\r
- * @brief Q15 bilinear interpolation.\r
- * @param[in,out] *S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
-\r
- static __INLINE q15_t arm_bilinear_interp_q15(\r
- arm_bilinear_interp_instance_q15 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q15_t x1, x2, y1, y2; /* Nearest output values */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- int32_t rI, cI; /* Row and column indices */\r
- q15_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & 0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & 0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + nCols * (cI)];\r
- x2 = pYData[(rI) + nCols * (cI) + 1u];\r
-\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + nCols * (cI + 1)];\r
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
-\r
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
- acc = ((q63_t) out * (0xFFFFF - yfract));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
- acc += ((q63_t) out * (xfract));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
- acc += ((q63_t) out * (yfract));\r
-\r
- /* acc is in 13.51 format and down shift acc by 36 times */\r
- /* Convert out to 1.15 format */\r
- return (acc >> 36);\r
-\r
- }\r
-\r
- /**\r
- * @brief Q7 bilinear interpolation.\r
- * @param[in,out] *S points to an instance of the interpolation structure.\r
- * @param[in] X interpolation coordinate in 12.20 format.\r
- * @param[in] Y interpolation coordinate in 12.20 format.\r
- * @return out interpolated value.\r
- */\r
-\r
- static __INLINE q7_t arm_bilinear_interp_q7(\r
- arm_bilinear_interp_instance_q7 * S,\r
- q31_t X,\r
- q31_t Y)\r
- {\r
- q63_t acc = 0; /* output */\r
- q31_t out; /* Temporary output */\r
- q31_t xfract, yfract; /* X, Y fractional parts */\r
- q7_t x1, x2, y1, y2; /* Nearest output values */\r
- int32_t rI, cI; /* Row and column indices */\r
- q7_t *pYData = S->pData; /* pointer to output table values */\r
- uint32_t nCols = S->numCols; /* num of rows */\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- rI = ((X & 0xFFF00000) >> 20);\r
-\r
- /* Input is in 12.20 format */\r
- /* 12 bits for the table index */\r
- /* Index value calculation */\r
- cI = ((Y & 0xFFF00000) >> 20);\r
-\r
- /* Care taken for table outside boundary */\r
- /* Returns zero output when values are outside table boundary */\r
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
- {\r
- return (0);\r
- }\r
-\r
- /* 20 bits for the fractional part */\r
- /* xfract should be in 12.20 format */\r
- xfract = (X & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- x1 = pYData[(rI) + nCols * (cI)];\r
- x2 = pYData[(rI) + nCols * (cI) + 1u];\r
-\r
-\r
- /* 20 bits for the fractional part */\r
- /* yfract should be in 12.20 format */\r
- yfract = (Y & 0x000FFFFF);\r
-\r
- /* Read two nearest output values from the index */\r
- y1 = pYData[(rI) + nCols * (cI + 1)];\r
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
-\r
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
- out = ((x1 * (0xFFFFF - xfract)));\r
- acc = (((q63_t) out * (0xFFFFF - yfract)));\r
-\r
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
- out = ((x2 * (0xFFFFF - yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y1 * (0xFFFFF - xfract)));\r
- acc += (((q63_t) out * (yfract)));\r
-\r
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
- out = ((y2 * (yfract)));\r
- acc += (((q63_t) out * (xfract)));\r
-\r
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
- return (acc >> 40);\r
-\r
- }\r
-\r
- /**\r
- * @} end of BilinearInterpolate group\r
- */\r
- \r
-\r
-//SMMLAR\r
-#define multAcc_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-//SMMLSR\r
-#define multSub_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
-\r
-//SMMULR\r
-#define mult_32x32_keep32_R(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
-\r
-//SMMLA\r
-#define multAcc_32x32_keep32(a, x, y) \\r
- a += (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-//SMMLS\r
-#define multSub_32x32_keep32(a, x, y) \\r
- a -= (q31_t) (((q63_t) x * y) >> 32)\r
-\r
-//SMMUL\r
-#define mult_32x32_keep32(a, x, y) \\r
- a = (q31_t) (((q63_t) x * y ) >> 32)\r
-\r
-\r
-#if defined ( __CC_ARM ) //Keil\r
-\r
-//Enter low optimization region - place directly above function definition\r
- #ifdef ARM_MATH_CM4\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("push") \\r
- _Pragma ("O1")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER \r
- #endif\r
-\r
-//Exit low optimization region - place directly after end of function definition\r
- #ifdef ARM_MATH_CM4\r
- #define LOW_OPTIMIZATION_EXIT \\r
- _Pragma ("pop")\r
- #else\r
- #define LOW_OPTIMIZATION_EXIT \r
- #endif\r
-\r
-//Enter low optimization region - place directly above function definition\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-\r
-//Exit low optimization region - place directly after end of function definition\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__ICCARM__) //IAR\r
-\r
-//Enter low optimization region - place directly above function definition\r
- #ifdef ARM_MATH_CM4\r
- #define LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define LOW_OPTIMIZATION_ENTER \r
- #endif\r
-\r
-//Exit low optimization region - place directly after end of function definition\r
- #define LOW_OPTIMIZATION_EXIT\r
-\r
-//Enter low optimization region - place directly above function definition\r
- #ifdef ARM_MATH_CM4\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
- _Pragma ("optimize=low")\r
- #else\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \r
- #endif\r
-\r
-//Exit low optimization region - place directly after end of function definition\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__GNUC__)\r
-\r
- #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))\r
-\r
- #define LOW_OPTIMIZATION_EXIT\r
-\r
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-\r
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#elif defined(__CSMC__) // Cosmic\r
-\r
-#define LOW_OPTIMIZATION_ENTER\r
-#define LOW_OPTIMIZATION_EXIT\r
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
-\r
-#endif\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* _ARM_MATH_H */\r
-\r
-/**\r
- *\r
- * End of file.\r
- */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm4.h\r
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 22. August 2014\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#endif\r
-\r
-#ifndef __CORE_CM4_H_GENERIC\r
-#define __CORE_CM4_H_GENERIC\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/** \ingroup Cortex_M4\r
- @{\r
- */\r
-\r
-/* CMSIS CM4 definitions */\r
-#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \\r
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __CSMC__ ) /* Cosmic */\r
- #if ( __CSMC__ & 0x400) // FPU present for parser\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-#endif\r
-\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
-#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM4_H_DEPENDANT\r
-#define __CORE_CM4_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM4_REV\r
- #define __CM4_REV 0x0000\r
- #warning "__CM4_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/*@} end of group Cortex_M4 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1];\r
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __O union\r
- {\r
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1];\r
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1];\r
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55];\r
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131];\r
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759];\r
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1];\r
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39];\r
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8];\r
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if (__FPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register */\r
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register */\r
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register */\r
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-#endif\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M4 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1)\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/** \brief Set Priority Grouping\r
-\r
- The function sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/** \brief Get Priority Grouping\r
-\r
- The function reads the priority grouping field from the NVIC Interrupt Controller.\r
-\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
-}\r
-\r
-\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Active Interrupt\r
-\r
- The function reads the active register in NVIC and returns the active bit.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/** \brief Encode Priority\r
-\r
- The function encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/** \brief Decode Priority\r
-\r
- The function decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/** \brief ITM Send Character\r
-\r
- The function transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-\r
- \param [in] ch Character to transmit.\r
-\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Receive Character\r
-\r
- The function inputs a character via the external variable \ref ITM_RxBuffer.\r
-\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Check Character\r
-\r
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM4_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm7.h\r
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
- * @version V4.00\r
- * @date 01. September 2014\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2014 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#endif\r
-\r
-#ifndef __CORE_CM7_H_GENERIC\r
-#define __CORE_CM7_H_GENERIC\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/** \ingroup Cortex_M7\r
- @{\r
- */\r
-\r
-/* CMSIS CM7 definitions */\r
-#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \\r
- __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x07) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __CSMC__ )\r
- #define __packed\r
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
- #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not.\r
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
-*/\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __TMS470__ )\r
- #if defined __TI_VFP_SUPPORT__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-\r
-#elif defined ( __CSMC__ ) /* Cosmic */\r
- #if ( __CSMC__ & 0x400) // FPU present for parser\r
- #if (__FPU_PRESENT == 1)\r
- #define __FPU_USED 1\r
- #else\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #define __FPU_USED 0\r
- #endif\r
- #else\r
- #define __FPU_USED 0\r
- #endif\r
-#endif\r
-\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
-#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM7_H_DEPENDANT\r
-#define __CORE_CM7_H_DEPENDANT\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM7_REV\r
- #define __CM7_REV 0x0000\r
- #warning "__CM7_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __FPU_PRESENT\r
- #define __FPU_PRESENT 0\r
- #warning "__FPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0\r
- #warning "__MPU_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __ICACHE_PRESENT\r
- #define __ICACHE_PRESENT 0\r
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DCACHE_PRESENT\r
- #define __DCACHE_PRESENT 0\r
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __DTCM_PRESENT\r
- #define __DTCM_PRESENT 0\r
- #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/*@} end of group Cortex_M7 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- - Core Debug Register\r
- - Core MPU Register\r
- - Core FPU Register\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
-#if (__CORTEX_M != 0x07)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x07)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[1];\r
- __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
- __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
- __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
- __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
- uint32_t RESERVED3[93];\r
- __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
- uint32_t RESERVED4[15];\r
- __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
- __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
- __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
- uint32_t RESERVED5[1];\r
- __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
- uint32_t RESERVED6[1];\r
- __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
- __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
- __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
- __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
- __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
- __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
- __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
- __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
- uint32_t RESERVED7[6];\r
- __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
- __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
- __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
- __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
- __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
- uint32_t RESERVED8[1];\r
- __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Vector Table Offset Register Definitions */\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */\r
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
-\r
-#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */\r
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
-\r
-#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */\r
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
-\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-\r
-/* Cache Level ID register */\r
-#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */\r
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
-\r
-#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */\r
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */\r
-\r
-/* Cache Type register */\r
-#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */\r
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
-\r
-#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */\r
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
-\r
-#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */\r
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
-\r
-#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */\r
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
-\r
-#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */\r
-#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */\r
-\r
-/* Cache Size ID Register */\r
-#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */\r
-#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
-\r
-#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */\r
-#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
-\r
-#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */\r
-#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
-\r
-#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */\r
-#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
-\r
-#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */\r
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
-\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */\r
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
-\r
-#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */\r
-#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */\r
-\r
-/* Cache Size Selection Register */\r
-#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */\r
-#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
-\r
-#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */\r
-#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */\r
-\r
-/* SCB Software Triggered Interrupt Register */\r
-#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */\r
-#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */\r
-\r
-/* Instruction Tightly-Coupled Memory Control Register*/\r
-#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */\r
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
-\r
-#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */\r
-#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
-\r
-#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */\r
-#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
-\r
-#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */\r
-#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */\r
-\r
-/* Data Tightly-Coupled Memory Control Registers */\r
-#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */\r
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
-\r
-#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */\r
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
-\r
-#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */\r
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
-\r
-#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */\r
-#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */\r
-\r
-/* AHBP Control Register */\r
-#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */\r
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
-\r
-#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */\r
-#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */\r
-\r
-/* L1 Cache Control Register */\r
-#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */\r
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
-\r
-#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */\r
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
-\r
-#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */\r
-#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */\r
-\r
-/* AHBS control register */\r
-#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */\r
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
-\r
-#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */\r
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
-\r
-#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/\r
-#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */\r
-\r
-/* Auxiliary Bus Fault Status Register */\r
-#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/\r
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
-\r
-#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/\r
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
-\r
-#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/\r
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
-\r
-#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/\r
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
-\r
-#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/\r
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
-\r
-#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/\r
-#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1];\r
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
-} SCnSCB_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */\r
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
-\r
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */\r
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
-\r
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */\r
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
-\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
-\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
-\r
-/*@} end of group CMSIS_SCnotSCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
- */\r
-typedef struct\r
-{\r
- __O union\r
- {\r
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_ITM */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1];\r
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1];\r
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
- uint32_t RESERVED3[981];\r
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
-} DWT_Type;\r
-\r
-/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
-\r
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
-\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
-\r
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
-\r
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
-\r
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
-\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
-\r
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
-\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
-\r
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
-\r
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
-\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
-\r
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
-\r
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
-\r
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
-\r
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
-\r
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
-\r
-/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
-\r
-/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
-\r
-/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
-\r
-/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
-\r
-/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
-\r
-/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
-\r
-/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
-\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
-\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
-\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
-\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
-\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
-\r
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_DWT */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55];\r
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131];\r
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759];\r
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1];\r
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39];\r
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8];\r
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
-} TPI_Type;\r
-\r
-/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
-\r
-/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
-\r
-/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
-\r
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
-\r
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
-\r
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
-\r
-/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
-\r
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
-\r
-/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
-\r
-/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
-\r
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
-\r
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
-\r
-/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
-\r
-/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
-\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
-\r
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
-\r
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
-\r
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
-\r
-/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
-\r
-/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
-\r
-/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
-\r
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
-\r
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
-\r
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
-\r
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
-\r
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
-\r
-/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_TPI */\r
-\r
-\r
-#if (__MPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Memory Protection Unit (MPU).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
-\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@} end of group CMSIS_MPU */\r
-#endif\r
-\r
-\r
-#if (__FPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
- \brief Type definitions for the Floating Point Unit (FPU)\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Floating Point Unit (FPU).\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
- __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
-} FPU_Type;\r
-\r
-/* Floating-Point Context Control Register */\r
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
-\r
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
-\r
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
-\r
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
-\r
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
-\r
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
-\r
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
-\r
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
-\r
-/* Floating-Point Context Address Register */\r
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
-\r
-/* Floating-Point Default Status Control Register */\r
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
-\r
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
-\r
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
-\r
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
-\r
-/* Media and FP Feature Register 0 */\r
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
-\r
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
-\r
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
-\r
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
-\r
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
-\r
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
-\r
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
-\r
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
-\r
-/* Media and FP Feature Register 1 */\r
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
-\r
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
-\r
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
-\r
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
-\r
-/* Media and FP Feature Register 2 */\r
-\r
-/*@} end of group CMSIS_FPU */\r
-#endif\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M4 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-#if (__FPU_PRESENT == 1)\r
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
-#endif\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Debug Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/** \brief Set Priority Grouping\r
-\r
- The function sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Priority grouping field.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-\r
-/** \brief Get Priority Grouping\r
-\r
- The function reads the priority grouping field from the NVIC Interrupt Controller.\r
-\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
-}\r
-\r
-\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-\r
-/** \brief Get Active Interrupt\r
-\r
- The function reads the active register in NVIC and returns the active bit.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/** \brief Encode Priority\r
-\r
- The function encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
- */\r
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/** \brief Decode Priority\r
-\r
- The function decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
-\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
- */\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-/* ########################## Cache functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
- \brief Functions that configure Instruction and Data cache.\r
- @{\r
- */\r
-\r
-/* Cache Size ID Register Macros */\r
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
-#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )\r
-\r
-\r
-/** \brief Enable I-Cache\r
-\r
- The function turns on I-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableICache(void)\r
-{\r
- #if (__ICACHE_PRESENT == 1)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0; // invalidate I-Cache\r
- SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Disable I-Cache\r
-\r
- The function turns off I-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableICache(void)\r
-{\r
- #if (__ICACHE_PRESENT == 1)\r
- __DSB();\r
- __ISB();\r
- SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache\r
- SCB->ICIALLU = 0; // invalidate I-Cache\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Invalidate I-Cache\r
-\r
- The function invalidates I-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateICache(void)\r
-{\r
- #if (__ICACHE_PRESENT == 1)\r
- __DSB();\r
- __ISB();\r
- SCB->ICIALLU = 0;\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Enable D-Cache\r
-\r
- The function turns on D-Cache\r
- */\r
-__STATIC_INLINE void SCB_EnableDCache(void)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- uint32_t ccsidr, sshift, wshift, sw;\r
- uint32_t sets, ways;\r
-\r
- ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
-\r
- __DSB();\r
-\r
- do { // invalidate D-Cache\r
- int32_t tmpways = ways;\r
- do {\r
- sw = ((tmpways << wshift) | (sets << sshift));\r
- SCB->DCISW = sw;\r
- } while(tmpways--);\r
- } while(sets--);\r
- __DSB();\r
-\r
- SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Disable D-Cache\r
-\r
- The function turns off D-Cache\r
- */\r
-__STATIC_INLINE void SCB_DisableDCache(void)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- uint32_t ccsidr, sshift, wshift, sw;\r
- uint32_t sets, ways;\r
-\r
- ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
-\r
- __DSB();\r
-\r
- SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache\r
-\r
- do { // clean & invalidate D-Cache\r
- int32_t tmpways = ways;\r
- do {\r
- sw = ((tmpways << wshift) | (sets << sshift));\r
- SCB->DCCISW = sw;\r
- } while(tmpways--);\r
- } while(sets--);\r
-\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Invalidate D-Cache\r
-\r
- The function invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_InvalidateDCache(void)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- uint32_t ccsidr, sshift, wshift, sw;\r
- uint32_t sets, ways;\r
-\r
- ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
-\r
- __DSB();\r
-\r
- do { // invalidate D-Cache\r
- int32_t tmpways = ways;\r
- do {\r
- sw = ((tmpways << wshift) | (sets << sshift));\r
- SCB->DCISW = sw;\r
- } while(tmpways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Clean D-Cache\r
-\r
- The function cleans D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanDCache(void)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- uint32_t ccsidr, sshift, wshift, sw;\r
- uint32_t sets, ways;\r
-\r
- ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
-\r
- __DSB();\r
-\r
- do { // clean D-Cache\r
- int32_t tmpways = ways;\r
- do {\r
- sw = ((tmpways << wshift) | (sets << sshift));\r
- SCB->DCCSW = sw;\r
- } while(tmpways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/** \brief Clean & Invalidate D-Cache\r
-\r
- The function cleans and Invalidates D-Cache\r
- */\r
-__STATIC_INLINE void SCB_CleanInvalidateDCache(void)\r
-{\r
- #if (__DCACHE_PRESENT == 1)\r
- uint32_t ccsidr, sshift, wshift, sw;\r
- uint32_t sets, ways;\r
-\r
- ccsidr = SCB->CCSIDR;\r
- sets = CCSIDR_SETS(ccsidr);\r
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;\r
- ways = CCSIDR_WAYS(ccsidr);\r
- wshift = __CLZ(ways) & 0x1f;\r
-\r
- __DSB();\r
-\r
- do { // clean & invalidate D-Cache\r
- int32_t tmpways = ways;\r
- do {\r
- sw = ((tmpways << wshift) | (sets << sshift));\r
- SCB->DCCISW = sw;\r
- } while(tmpways--);\r
- } while(sets--);\r
-\r
- __DSB();\r
- __ISB();\r
- #endif\r
-}\r
-\r
-\r
-/*@} end of CMSIS_Core_CacheFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
- @{\r
- */\r
-\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/** \brief ITM Send Character\r
-\r
- The function transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
-\r
- \param [in] ch Character to transmit.\r
-\r
- \returns Character to transmit.\r
- */\r
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Receive Character\r
-\r
- The function inputs a character via the external variable \ref ITM_RxBuffer.\r
-\r
- \return Received character.\r
- \return -1 No character pending.\r
- */\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
- int32_t ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/** \brief ITM Check Character\r
-\r
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-\r
- \return 0 No character available.\r
- \return 1 Character available.\r
- */\r
-__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@} end of CMSIS_core_DebugFunctions */\r
-\r
-\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CM7_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg230f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG230F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG230F1024_H__\r
-#define __SILICON_LABS_EFM32GG230F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024 EFM32GG230F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_Core EFM32GG230F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG230F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG230F1024_Part EFM32GG230F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG230F1024)\r
-#define EFM32GG230F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG230F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG230F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG230F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_Peripheral_TypeDefs EFM32GG230F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_DMA EFM32GG230F1024 DMA\r
- * @{\r
- * @brief EFM32GG230F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_CMU EFM32GG230F1024 CMU\r
- * @{\r
- * @brief EFM32GG230F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_PRS EFM32GG230F1024 PRS\r
- * @{\r
- * @brief EFM32GG230F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG230F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_Peripheral_Base EFM32GG230F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG230F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_Peripheral_Declaration EFM32GG230F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG230F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_BitFields EFM32GG230F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG230F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG230F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_DMA_BitFields EFM32GG230F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG230F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_CMU_BitFields EFM32GG230F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG230F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_PRS_BitFields EFM32GG230F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG230F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_UNLOCK EFM32GG230F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG230F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG230F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F1024_Alternate_Function EFM32GG230F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG230F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG230F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG230F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg230f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG230F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG230F512_H__\r
-#define __SILICON_LABS_EFM32GG230F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512 EFM32GG230F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_Core EFM32GG230F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG230F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG230F512_Part EFM32GG230F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG230F512)\r
-#define EFM32GG230F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG230F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG230F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG230F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_Peripheral_TypeDefs EFM32GG230F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_DMA EFM32GG230F512 DMA\r
- * @{\r
- * @brief EFM32GG230F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_CMU EFM32GG230F512 CMU\r
- * @{\r
- * @brief EFM32GG230F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_PRS EFM32GG230F512 PRS\r
- * @{\r
- * @brief EFM32GG230F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG230F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_Peripheral_Base EFM32GG230F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG230F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_Peripheral_Declaration EFM32GG230F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG230F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_BitFields EFM32GG230F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG230F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG230F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_DMA_BitFields EFM32GG230F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG230F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_CMU_BitFields EFM32GG230F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG230F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_PRS_BitFields EFM32GG230F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG230F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_UNLOCK EFM32GG230F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG230F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG230F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG230F512_Alternate_Function EFM32GG230F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG230F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG230F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG230F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg232f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG232F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG232F1024_H__\r
-#define __SILICON_LABS_EFM32GG232F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024 EFM32GG232F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_Core EFM32GG232F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG232F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG232F1024_Part EFM32GG232F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG232F1024)\r
-#define EFM32GG232F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG232F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG232F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG232F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_Peripheral_TypeDefs EFM32GG232F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_DMA EFM32GG232F1024 DMA\r
- * @{\r
- * @brief EFM32GG232F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_CMU EFM32GG232F1024 CMU\r
- * @{\r
- * @brief EFM32GG232F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_PRS EFM32GG232F1024 PRS\r
- * @{\r
- * @brief EFM32GG232F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG232F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_Peripheral_Base EFM32GG232F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG232F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_Peripheral_Declaration EFM32GG232F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG232F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_BitFields EFM32GG232F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG232F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG232F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_DMA_BitFields EFM32GG232F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG232F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_CMU_BitFields EFM32GG232F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG232F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_PRS_BitFields EFM32GG232F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG232F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_UNLOCK EFM32GG232F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG232F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG232F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F1024_Alternate_Function EFM32GG232F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG232F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG232F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG232F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg232f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG232F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG232F512_H__\r
-#define __SILICON_LABS_EFM32GG232F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512 EFM32GG232F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_Core EFM32GG232F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG232F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG232F512_Part EFM32GG232F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG232F512)\r
-#define EFM32GG232F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG232F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG232F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG232F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_Peripheral_TypeDefs EFM32GG232F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_DMA EFM32GG232F512 DMA\r
- * @{\r
- * @brief EFM32GG232F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_CMU EFM32GG232F512 CMU\r
- * @{\r
- * @brief EFM32GG232F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_PRS EFM32GG232F512 PRS\r
- * @{\r
- * @brief EFM32GG232F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG232F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_Peripheral_Base EFM32GG232F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG232F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_Peripheral_Declaration EFM32GG232F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG232F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_BitFields EFM32GG232F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG232F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG232F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_DMA_BitFields EFM32GG232F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG232F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_CMU_BitFields EFM32GG232F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG232F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_PRS_BitFields EFM32GG232F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG232F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_UNLOCK EFM32GG232F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG232F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG232F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG232F512_Alternate_Function EFM32GG232F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG232F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG232F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG232F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg280f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG280F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG280F1024_H__\r
-#define __SILICON_LABS_EFM32GG280F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024 EFM32GG280F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_Core EFM32GG280F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG280F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG280F1024_Part EFM32GG280F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG280F1024)\r
-#define EFM32GG280F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG280F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG280F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG280F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_Peripheral_TypeDefs EFM32GG280F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_CMU EFM32GG280F1024 CMU\r
- * @{\r
- * @brief EFM32GG280F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_PRS EFM32GG280F1024 PRS\r
- * @{\r
- * @brief EFM32GG280F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG280F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_Peripheral_Base EFM32GG280F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG280F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_Peripheral_Declaration EFM32GG280F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG280F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_BitFields EFM32GG280F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG280F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG280F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_CMU_BitFields EFM32GG280F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG280F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_PRS_BitFields EFM32GG280F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG280F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_UNLOCK EFM32GG280F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG280F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG280F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F1024_Alternate_Function EFM32GG280F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG280F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG280F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG280F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg280f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG280F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG280F512_H__\r
-#define __SILICON_LABS_EFM32GG280F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512 EFM32GG280F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_Core EFM32GG280F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG280F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG280F512_Part EFM32GG280F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG280F512)\r
-#define EFM32GG280F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG280F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG280F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG280F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_Peripheral_TypeDefs EFM32GG280F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_CMU EFM32GG280F512 CMU\r
- * @{\r
- * @brief EFM32GG280F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_PRS EFM32GG280F512 PRS\r
- * @{\r
- * @brief EFM32GG280F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG280F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_Peripheral_Base EFM32GG280F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG280F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_Peripheral_Declaration EFM32GG280F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG280F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_BitFields EFM32GG280F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG280F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG280F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_CMU_BitFields EFM32GG280F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG280F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_PRS_BitFields EFM32GG280F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG280F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_UNLOCK EFM32GG280F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG280F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG280F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG280F512_Alternate_Function EFM32GG280F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG280F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG280F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG280F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg290f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG290F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG290F1024_H__\r
-#define __SILICON_LABS_EFM32GG290F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024 EFM32GG290F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_Core EFM32GG290F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG290F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG290F1024_Part EFM32GG290F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG290F1024)\r
-#define EFM32GG290F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG290F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG290F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG290F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_Peripheral_TypeDefs EFM32GG290F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_CMU EFM32GG290F1024 CMU\r
- * @{\r
- * @brief EFM32GG290F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_PRS EFM32GG290F1024 PRS\r
- * @{\r
- * @brief EFM32GG290F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG290F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_Peripheral_Base EFM32GG290F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG290F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_Peripheral_Declaration EFM32GG290F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG290F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_BitFields EFM32GG290F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG290F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG290F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_CMU_BitFields EFM32GG290F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG290F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_PRS_BitFields EFM32GG290F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG290F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_UNLOCK EFM32GG290F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG290F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG290F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F1024_Alternate_Function EFM32GG290F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG290F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG290F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG290F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg290f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG290F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG290F512_H__\r
-#define __SILICON_LABS_EFM32GG290F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512 EFM32GG290F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_Core EFM32GG290F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG290F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG290F512_Part EFM32GG290F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG290F512)\r
-#define EFM32GG290F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG290F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG290F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG290F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_Peripheral_TypeDefs EFM32GG290F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_CMU EFM32GG290F512 CMU\r
- * @{\r
- * @brief EFM32GG290F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_PRS EFM32GG290F512 PRS\r
- * @{\r
- * @brief EFM32GG290F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG290F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_Peripheral_Base EFM32GG290F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG290F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_Peripheral_Declaration EFM32GG290F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG290F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_BitFields EFM32GG290F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG290F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG290F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_CMU_BitFields EFM32GG290F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG290F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_PRS_BitFields EFM32GG290F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG290F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_UNLOCK EFM32GG290F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG290F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG290F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG290F512_Alternate_Function EFM32GG290F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG290F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG290F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG290F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg295f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG295F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG295F1024_H__\r
-#define __SILICON_LABS_EFM32GG295F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024 EFM32GG295F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_Core EFM32GG295F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG295F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG295F1024_Part EFM32GG295F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG295F1024)\r
-#define EFM32GG295F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG295F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG295F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG295F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_Peripheral_TypeDefs EFM32GG295F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_CMU EFM32GG295F1024 CMU\r
- * @{\r
- * @brief EFM32GG295F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_PRS EFM32GG295F1024 PRS\r
- * @{\r
- * @brief EFM32GG295F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG295F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_Peripheral_Base EFM32GG295F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG295F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_Peripheral_Declaration EFM32GG295F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG295F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_BitFields EFM32GG295F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG295F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG295F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_CMU_BitFields EFM32GG295F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG295F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_PRS_BitFields EFM32GG295F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG295F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_UNLOCK EFM32GG295F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG295F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG295F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F1024_Alternate_Function EFM32GG295F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG295F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG295F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG295F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg295f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG295F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG295F512_H__\r
-#define __SILICON_LABS_EFM32GG295F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512 EFM32GG295F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_Core EFM32GG295F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG295F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG295F512_Part EFM32GG295F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG295F512)\r
-#define EFM32GG295F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG295F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG295F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG295F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_Peripheral_TypeDefs EFM32GG295F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_CMU EFM32GG295F512 CMU\r
- * @{\r
- * @brief EFM32GG295F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_PRS EFM32GG295F512 PRS\r
- * @{\r
- * @brief EFM32GG295F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG295F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_Peripheral_Base EFM32GG295F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG295F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_Peripheral_Declaration EFM32GG295F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG295F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_BitFields EFM32GG295F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG295F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG295F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_CMU_BitFields EFM32GG295F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG295F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_PRS_BitFields EFM32GG295F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG295F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_UNLOCK EFM32GG295F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG295F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG295F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG295F512_Alternate_Function EFM32GG295F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG295F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG295F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG295F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg330f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG330F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG330F1024_H__\r
-#define __SILICON_LABS_EFM32GG330F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024 EFM32GG330F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_Core EFM32GG330F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG330F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG330F1024_Part EFM32GG330F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG330F1024)\r
-#define EFM32GG330F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG330F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG330F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG330F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_Peripheral_TypeDefs EFM32GG330F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_DMA EFM32GG330F1024 DMA\r
- * @{\r
- * @brief EFM32GG330F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_CMU EFM32GG330F1024 CMU\r
- * @{\r
- * @brief EFM32GG330F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_PRS EFM32GG330F1024 PRS\r
- * @{\r
- * @brief EFM32GG330F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG330F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_Peripheral_Base EFM32GG330F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG330F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_Peripheral_Declaration EFM32GG330F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG330F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_BitFields EFM32GG330F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG330F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG330F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_DMA_BitFields EFM32GG330F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG330F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_CMU_BitFields EFM32GG330F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG330F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_PRS_BitFields EFM32GG330F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG330F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_UNLOCK EFM32GG330F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG330F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG330F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F1024_Alternate_Function EFM32GG330F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG330F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG330F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG330F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg330f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG330F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG330F512_H__\r
-#define __SILICON_LABS_EFM32GG330F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512 EFM32GG330F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_Core EFM32GG330F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG330F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG330F512_Part EFM32GG330F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG330F512)\r
-#define EFM32GG330F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG330F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG330F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG330F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_Peripheral_TypeDefs EFM32GG330F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_DMA EFM32GG330F512 DMA\r
- * @{\r
- * @brief EFM32GG330F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_CMU EFM32GG330F512 CMU\r
- * @{\r
- * @brief EFM32GG330F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_PRS EFM32GG330F512 PRS\r
- * @{\r
- * @brief EFM32GG330F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG330F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_Peripheral_Base EFM32GG330F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG330F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_Peripheral_Declaration EFM32GG330F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG330F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_BitFields EFM32GG330F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG330F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG330F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_DMA_BitFields EFM32GG330F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG330F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_CMU_BitFields EFM32GG330F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG330F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_PRS_BitFields EFM32GG330F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG330F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_UNLOCK EFM32GG330F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG330F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG330F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG330F512_Alternate_Function EFM32GG330F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG330F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG330F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG330F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg332f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG332F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG332F1024_H__\r
-#define __SILICON_LABS_EFM32GG332F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024 EFM32GG332F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_Core EFM32GG332F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG332F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG332F1024_Part EFM32GG332F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG332F1024)\r
-#define EFM32GG332F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG332F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG332F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG332F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_Peripheral_TypeDefs EFM32GG332F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_DMA EFM32GG332F1024 DMA\r
- * @{\r
- * @brief EFM32GG332F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_CMU EFM32GG332F1024 CMU\r
- * @{\r
- * @brief EFM32GG332F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_PRS EFM32GG332F1024 PRS\r
- * @{\r
- * @brief EFM32GG332F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG332F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_Peripheral_Base EFM32GG332F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG332F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_Peripheral_Declaration EFM32GG332F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG332F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_BitFields EFM32GG332F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG332F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG332F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_DMA_BitFields EFM32GG332F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG332F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_CMU_BitFields EFM32GG332F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG332F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_PRS_BitFields EFM32GG332F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG332F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_UNLOCK EFM32GG332F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG332F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG332F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F1024_Alternate_Function EFM32GG332F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG332F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG332F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG332F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg332f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG332F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG332F512_H__\r
-#define __SILICON_LABS_EFM32GG332F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512 EFM32GG332F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_Core EFM32GG332F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG332F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG332F512_Part EFM32GG332F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG332F512)\r
-#define EFM32GG332F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG332F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG332F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG332F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_Peripheral_TypeDefs EFM32GG332F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_DMA EFM32GG332F512 DMA\r
- * @{\r
- * @brief EFM32GG332F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_CMU EFM32GG332F512 CMU\r
- * @{\r
- * @brief EFM32GG332F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_PRS EFM32GG332F512 PRS\r
- * @{\r
- * @brief EFM32GG332F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG332F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_Peripheral_Base EFM32GG332F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG332F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_Peripheral_Declaration EFM32GG332F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG332F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_BitFields EFM32GG332F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG332F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG332F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_DMA_BitFields EFM32GG332F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG332F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_CMU_BitFields EFM32GG332F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG332F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_PRS_BitFields EFM32GG332F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG332F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_UNLOCK EFM32GG332F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG332F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG332F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG332F512_Alternate_Function EFM32GG332F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG332F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG332F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG332F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg380f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG380F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG380F1024_H__\r
-#define __SILICON_LABS_EFM32GG380F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024 EFM32GG380F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_Core EFM32GG380F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG380F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG380F1024_Part EFM32GG380F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG380F1024)\r
-#define EFM32GG380F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG380F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG380F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG380F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_Peripheral_TypeDefs EFM32GG380F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_CMU EFM32GG380F1024 CMU\r
- * @{\r
- * @brief EFM32GG380F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG380F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_Peripheral_Base EFM32GG380F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG380F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_Peripheral_Declaration EFM32GG380F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG380F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_BitFields EFM32GG380F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_CMU_BitFields EFM32GG380F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG380F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_UNLOCK EFM32GG380F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG380F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG380F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F1024_Alternate_Function EFM32GG380F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG380F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG380F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG380F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg380f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG380F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG380F512_H__\r
-#define __SILICON_LABS_EFM32GG380F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512 EFM32GG380F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_Core EFM32GG380F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG380F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG380F512_Part EFM32GG380F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG380F512)\r
-#define EFM32GG380F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG380F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG380F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG380F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_Peripheral_TypeDefs EFM32GG380F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_CMU EFM32GG380F512 CMU\r
- * @{\r
- * @brief EFM32GG380F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG380F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_Peripheral_Base EFM32GG380F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG380F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_Peripheral_Declaration EFM32GG380F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG380F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_BitFields EFM32GG380F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_CMU_BitFields EFM32GG380F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG380F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_UNLOCK EFM32GG380F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG380F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG380F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG380F512_Alternate_Function EFM32GG380F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG380F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG380F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG380F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg390f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG390F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG390F1024_H__\r
-#define __SILICON_LABS_EFM32GG390F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024 EFM32GG390F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_Core EFM32GG390F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG390F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG390F1024_Part EFM32GG390F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG390F1024)\r
-#define EFM32GG390F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG390F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG390F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG390F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_Peripheral_TypeDefs EFM32GG390F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_CMU EFM32GG390F1024 CMU\r
- * @{\r
- * @brief EFM32GG390F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG390F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_Peripheral_Base EFM32GG390F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG390F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_Peripheral_Declaration EFM32GG390F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG390F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_BitFields EFM32GG390F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_CMU_BitFields EFM32GG390F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG390F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_UNLOCK EFM32GG390F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG390F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG390F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F1024_Alternate_Function EFM32GG390F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG390F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG390F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG390F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg390f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG390F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG390F512_H__\r
-#define __SILICON_LABS_EFM32GG390F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512 EFM32GG390F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_Core EFM32GG390F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG390F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG390F512_Part EFM32GG390F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG390F512)\r
-#define EFM32GG390F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG390F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG390F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG390F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_Peripheral_TypeDefs EFM32GG390F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_CMU EFM32GG390F512 CMU\r
- * @{\r
- * @brief EFM32GG390F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG390F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_Peripheral_Base EFM32GG390F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG390F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_Peripheral_Declaration EFM32GG390F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG390F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_BitFields EFM32GG390F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_CMU_BitFields EFM32GG390F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG390F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_UNLOCK EFM32GG390F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG390F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG390F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG390F512_Alternate_Function EFM32GG390F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG390F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG390F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG390F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg395f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG395F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG395F1024_H__\r
-#define __SILICON_LABS_EFM32GG395F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024 EFM32GG395F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_Core EFM32GG395F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG395F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG395F1024_Part EFM32GG395F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG395F1024)\r
-#define EFM32GG395F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG395F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG395F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG395F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_Peripheral_TypeDefs EFM32GG395F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_CMU EFM32GG395F1024 CMU\r
- * @{\r
- * @brief EFM32GG395F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG395F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_Peripheral_Base EFM32GG395F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG395F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_Peripheral_Declaration EFM32GG395F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG395F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_BitFields EFM32GG395F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_CMU_BitFields EFM32GG395F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG395F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_UNLOCK EFM32GG395F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG395F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG395F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F1024_Alternate_Function EFM32GG395F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG395F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG395F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG395F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg395f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG395F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG395F512_H__\r
-#define __SILICON_LABS_EFM32GG395F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512 EFM32GG395F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_Core EFM32GG395F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG395F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG395F512_Part EFM32GG395F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG395F512)\r
-#define EFM32GG395F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG395F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG395F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG395F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_Peripheral_TypeDefs EFM32GG395F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_CMU EFM32GG395F512 CMU\r
- * @{\r
- * @brief EFM32GG395F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
-\r
- uint32_t RESERVED5[1]; /**< Reserved for future use **/\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG395F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_Peripheral_Base EFM32GG395F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG395F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_Peripheral_Declaration EFM32GG395F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG395F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_BitFields EFM32GG395F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_CMU_BitFields EFM32GG395F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG395F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_UNLOCK EFM32GG395F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG395F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG395F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG395F512_Alternate_Function EFM32GG395F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG395F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG395F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG395F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg840f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG840F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG840F1024_H__\r
-#define __SILICON_LABS_EFM32GG840F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024 EFM32GG840F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_Core EFM32GG840F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG840F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG840F1024_Part EFM32GG840F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG840F1024)\r
-#define EFM32GG840F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG840F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG840F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG840F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_Peripheral_TypeDefs EFM32GG840F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_DMA EFM32GG840F1024 DMA\r
- * @{\r
- * @brief EFM32GG840F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_CMU EFM32GG840F1024 CMU\r
- * @{\r
- * @brief EFM32GG840F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_PRS EFM32GG840F1024 PRS\r
- * @{\r
- * @brief EFM32GG840F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG840F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_Peripheral_Base EFM32GG840F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG840F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_Peripheral_Declaration EFM32GG840F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG840F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_BitFields EFM32GG840F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG840F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG840F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_DMA_BitFields EFM32GG840F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG840F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_CMU_BitFields EFM32GG840F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG840F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_PRS_BitFields EFM32GG840F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG840F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_UNLOCK EFM32GG840F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG840F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG840F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F1024_Alternate_Function EFM32GG840F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG840F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG840F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG840F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg840f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG840F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG840F512_H__\r
-#define __SILICON_LABS_EFM32GG840F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512 EFM32GG840F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_Core EFM32GG840F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG840F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG840F512_Part EFM32GG840F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG840F512)\r
-#define EFM32GG840F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG840F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG840F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG840F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_Peripheral_TypeDefs EFM32GG840F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_DMA EFM32GG840F512 DMA\r
- * @{\r
- * @brief EFM32GG840F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_CMU EFM32GG840F512 CMU\r
- * @{\r
- * @brief EFM32GG840F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_PRS EFM32GG840F512 PRS\r
- * @{\r
- * @brief EFM32GG840F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG840F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_Peripheral_Base EFM32GG840F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG840F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_Peripheral_Declaration EFM32GG840F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG840F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_BitFields EFM32GG840F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG840F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG840F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_DMA_BitFields EFM32GG840F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG840F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_CMU_BitFields EFM32GG840F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG840F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_PRS_BitFields EFM32GG840F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG840F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_UNLOCK EFM32GG840F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG840F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG840F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG840F512_Alternate_Function EFM32GG840F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG840F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG840F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG840F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg842f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG842F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG842F1024_H__\r
-#define __SILICON_LABS_EFM32GG842F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024 EFM32GG842F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_Core EFM32GG842F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG842F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG842F1024_Part EFM32GG842F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG842F1024)\r
-#define EFM32GG842F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG842F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG842F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG842F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_Peripheral_TypeDefs EFM32GG842F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_DMA EFM32GG842F1024 DMA\r
- * @{\r
- * @brief EFM32GG842F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_CMU EFM32GG842F1024 CMU\r
- * @{\r
- * @brief EFM32GG842F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_PRS EFM32GG842F1024 PRS\r
- * @{\r
- * @brief EFM32GG842F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG842F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_Peripheral_Base EFM32GG842F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG842F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_Peripheral_Declaration EFM32GG842F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG842F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_BitFields EFM32GG842F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG842F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG842F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_DMA_BitFields EFM32GG842F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG842F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_CMU_BitFields EFM32GG842F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG842F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_PRS_BitFields EFM32GG842F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG842F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_UNLOCK EFM32GG842F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG842F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG842F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F1024_Alternate_Function EFM32GG842F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG842F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG842F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG842F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg842f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG842F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG842F512_H__\r
-#define __SILICON_LABS_EFM32GG842F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512 EFM32GG842F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_Core EFM32GG842F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG842F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG842F512_Part EFM32GG842F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG842F512)\r
-#define EFM32GG842F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG842F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG842F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG842F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_Peripheral_TypeDefs EFM32GG842F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_DMA EFM32GG842F512 DMA\r
- * @{\r
- * @brief EFM32GG842F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_CMU EFM32GG842F512 CMU\r
- * @{\r
- * @brief EFM32GG842F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_PRS EFM32GG842F512 PRS\r
- * @{\r
- * @brief EFM32GG842F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG842F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_Peripheral_Base EFM32GG842F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG842F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_Peripheral_Declaration EFM32GG842F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG842F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_BitFields EFM32GG842F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG842F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG842F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_DMA_BitFields EFM32GG842F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG842F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_CMU_BitFields EFM32GG842F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG842F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_PRS_BitFields EFM32GG842F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG842F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_UNLOCK EFM32GG842F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG842F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG842F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG842F512_Alternate_Function EFM32GG842F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG842F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG842F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG842F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg880f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG880F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG880F1024_H__\r
-#define __SILICON_LABS_EFM32GG880F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024 EFM32GG880F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_Core EFM32GG880F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG880F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG880F1024_Part EFM32GG880F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG880F1024)\r
-#define EFM32GG880F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG880F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG880F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG880F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_Peripheral_TypeDefs EFM32GG880F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_CMU EFM32GG880F1024 CMU\r
- * @{\r
- * @brief EFM32GG880F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_PRS EFM32GG880F1024 PRS\r
- * @{\r
- * @brief EFM32GG880F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG880F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_Peripheral_Base EFM32GG880F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG880F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_Peripheral_Declaration EFM32GG880F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG880F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_BitFields EFM32GG880F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG880F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG880F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_CMU_BitFields EFM32GG880F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG880F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_PRS_BitFields EFM32GG880F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG880F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_UNLOCK EFM32GG880F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG880F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG880F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F1024_Alternate_Function EFM32GG880F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG880F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG880F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG880F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg880f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG880F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG880F512_H__\r
-#define __SILICON_LABS_EFM32GG880F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512 EFM32GG880F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_Core EFM32GG880F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG880F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG880F512_Part EFM32GG880F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG880F512)\r
-#define EFM32GG880F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG880F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG880F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG880F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_Peripheral_TypeDefs EFM32GG880F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_CMU EFM32GG880F512 CMU\r
- * @{\r
- * @brief EFM32GG880F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_PRS EFM32GG880F512 PRS\r
- * @{\r
- * @brief EFM32GG880F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG880F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_Peripheral_Base EFM32GG880F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG880F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_Peripheral_Declaration EFM32GG880F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG880F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_BitFields EFM32GG880F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG880F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG880F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_CMU_BitFields EFM32GG880F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG880F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_PRS_BitFields EFM32GG880F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG880F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_UNLOCK EFM32GG880F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG880F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG880F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG880F512_Alternate_Function EFM32GG880F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG880F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG880F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG880F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg890f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG890F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG890F1024_H__\r
-#define __SILICON_LABS_EFM32GG890F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024 EFM32GG890F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_Core EFM32GG890F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG890F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG890F1024_Part EFM32GG890F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG890F1024)\r
-#define EFM32GG890F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG890F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG890F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG890F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_Peripheral_TypeDefs EFM32GG890F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_CMU EFM32GG890F1024 CMU\r
- * @{\r
- * @brief EFM32GG890F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_PRS EFM32GG890F1024 PRS\r
- * @{\r
- * @brief EFM32GG890F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG890F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_Peripheral_Base EFM32GG890F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG890F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_Peripheral_Declaration EFM32GG890F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG890F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_BitFields EFM32GG890F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG890F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG890F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_CMU_BitFields EFM32GG890F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG890F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_PRS_BitFields EFM32GG890F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG890F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_UNLOCK EFM32GG890F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG890F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG890F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F1024_Alternate_Function EFM32GG890F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG890F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG890F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG890F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg890f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG890F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG890F512_H__\r
-#define __SILICON_LABS_EFM32GG890F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512 EFM32GG890F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_Core EFM32GG890F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG890F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG890F512_Part EFM32GG890F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG890F512)\r
-#define EFM32GG890F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG890F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG890F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG890F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_Peripheral_TypeDefs EFM32GG890F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_CMU EFM32GG890F512 CMU\r
- * @{\r
- * @brief EFM32GG890F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_PRS EFM32GG890F512 PRS\r
- * @{\r
- * @brief EFM32GG890F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG890F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_Peripheral_Base EFM32GG890F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG890F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_Peripheral_Declaration EFM32GG890F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG890F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_BitFields EFM32GG890F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG890F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG890F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_CMU_BitFields EFM32GG890F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG890F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_PRS_BitFields EFM32GG890F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG890F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_UNLOCK EFM32GG890F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG890F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG890F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG890F512_Alternate_Function EFM32GG890F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG890F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG890F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG890F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg895f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG895F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG895F1024_H__\r
-#define __SILICON_LABS_EFM32GG895F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024 EFM32GG895F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_Core EFM32GG895F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG895F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG895F1024_Part EFM32GG895F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG895F1024)\r
-#define EFM32GG895F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG895F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG895F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG895F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_Peripheral_TypeDefs EFM32GG895F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_CMU EFM32GG895F1024 CMU\r
- * @{\r
- * @brief EFM32GG895F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_PRS EFM32GG895F1024 PRS\r
- * @{\r
- * @brief EFM32GG895F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG895F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_Peripheral_Base EFM32GG895F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG895F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_Peripheral_Declaration EFM32GG895F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG895F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_BitFields EFM32GG895F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG895F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG895F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_CMU_BitFields EFM32GG895F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG895F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_PRS_BitFields EFM32GG895F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG895F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_UNLOCK EFM32GG895F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG895F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG895F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F1024_Alternate_Function EFM32GG895F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG895F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG895F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG895F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg895f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG895F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG895F512_H__\r
-#define __SILICON_LABS_EFM32GG895F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512 EFM32GG895F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_Core EFM32GG895F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG895F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG895F512_Part EFM32GG895F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG895F512)\r
-#define EFM32GG895F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG895F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG895F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG895F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_Peripheral_TypeDefs EFM32GG895F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_CMU EFM32GG895F512 CMU\r
- * @{\r
- * @brief EFM32GG895F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_PRS EFM32GG895F512 PRS\r
- * @{\r
- * @brief EFM32GG895F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG895F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_Peripheral_Base EFM32GG895F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG895F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_Peripheral_Declaration EFM32GG895F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG895F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_BitFields EFM32GG895F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG895F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_UART1_TXC ((42 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_UART1_RXDATAV ((42 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG895F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_CMU_BitFields EFM32GG895F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x00000033UL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */\r
-#define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */\r
-#define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */\r
-#define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG895F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_PRS_BitFields EFM32GG895F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL /**< Mode UART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL /**< Mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) /**< Shifted mode UART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL /**< Mode UART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG895F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_UNLOCK EFM32GG895F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG895F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG895F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG895F512_Alternate_Function EFM32GG895F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG895F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG895F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG895F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg900f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG900F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG900F1024_H__\r
-#define __SILICON_LABS_EFM32GG900F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024 EFM32GG900F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_Core EFM32GG900F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG900F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG900F1024_Part EFM32GG900F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG900F1024)\r
-#define EFM32GG900F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG900F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG900F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG900F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_Peripheral_TypeDefs EFM32GG900F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG900F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_Peripheral_Base EFM32GG900F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG900F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_Peripheral_Declaration EFM32GG900F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG900F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_BitFields EFM32GG900F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_UNLOCK EFM32GG900F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG900F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG900F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F1024_Alternate_Function EFM32GG900F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG900F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG900F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG900F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg900f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG900F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG900F512_H__\r
-#define __SILICON_LABS_EFM32GG900F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512 EFM32GG900F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_Core EFM32GG900F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG900F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG900F512_Part EFM32GG900F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG900F512)\r
-#define EFM32GG900F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG900F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG900F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG900F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_Peripheral_TypeDefs EFM32GG900F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG900F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_Peripheral_Base EFM32GG900F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG900F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_Peripheral_Declaration EFM32GG900F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG900F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_BitFields EFM32GG900F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_UNLOCK EFM32GG900F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG900F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG900F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG900F512_Alternate_Function EFM32GG900F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG900F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG900F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG900F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg940f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG940F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG940F1024_H__\r
-#define __SILICON_LABS_EFM32GG940F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024 EFM32GG940F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_Core EFM32GG940F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG940F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG940F1024_Part EFM32GG940F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG940F1024)\r
-#define EFM32GG940F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG940F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG940F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG940F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_Peripheral_TypeDefs EFM32GG940F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_DMA EFM32GG940F1024 DMA\r
- * @{\r
- * @brief EFM32GG940F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_CMU EFM32GG940F1024 CMU\r
- * @{\r
- * @brief EFM32GG940F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_PRS EFM32GG940F1024 PRS\r
- * @{\r
- * @brief EFM32GG940F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG940F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_Peripheral_Base EFM32GG940F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG940F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_Peripheral_Declaration EFM32GG940F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG940F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_BitFields EFM32GG940F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG940F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG940F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_DMA_BitFields EFM32GG940F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG940F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_CMU_BitFields EFM32GG940F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG940F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_PRS_BitFields EFM32GG940F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG940F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_UNLOCK EFM32GG940F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG940F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG940F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F1024_Alternate_Function EFM32GG940F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG940F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG940F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG940F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg940f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG940F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG940F512_H__\r
-#define __SILICON_LABS_EFM32GG940F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512 EFM32GG940F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_Core EFM32GG940F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG940F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG940F512_Part EFM32GG940F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG940F512)\r
-#define EFM32GG940F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG940F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG940F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG940F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_Peripheral_TypeDefs EFM32GG940F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_DMA EFM32GG940F512 DMA\r
- * @{\r
- * @brief EFM32GG940F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_CMU EFM32GG940F512 CMU\r
- * @{\r
- * @brief EFM32GG940F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_PRS EFM32GG940F512 PRS\r
- * @{\r
- * @brief EFM32GG940F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG940F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_Peripheral_Base EFM32GG940F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG940F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_Peripheral_Declaration EFM32GG940F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG940F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_BitFields EFM32GG940F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG940F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG940F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_DMA_BitFields EFM32GG940F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG940F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_CMU_BitFields EFM32GG940F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG940F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_PRS_BitFields EFM32GG940F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG940F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_UNLOCK EFM32GG940F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG940F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG940F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG940F512_Alternate_Function EFM32GG940F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG940F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG940F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG940F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg942f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG942F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG942F1024_H__\r
-#define __SILICON_LABS_EFM32GG942F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024 EFM32GG942F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_Core EFM32GG942F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG942F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG942F1024_Part EFM32GG942F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG942F1024)\r
-#define EFM32GG942F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG942F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG942F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG942F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_Peripheral_TypeDefs EFM32GG942F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_DMA EFM32GG942F1024 DMA\r
- * @{\r
- * @brief EFM32GG942F1024_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_CMU EFM32GG942F1024 CMU\r
- * @{\r
- * @brief EFM32GG942F1024_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_PRS EFM32GG942F1024 PRS\r
- * @{\r
- * @brief EFM32GG942F1024_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG942F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_Peripheral_Base EFM32GG942F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG942F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_Peripheral_Declaration EFM32GG942F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG942F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_BitFields EFM32GG942F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG942F1024_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG942F1024_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_DMA_BitFields EFM32GG942F1024_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG942F1024_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_CMU_BitFields EFM32GG942F1024_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG942F1024_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_PRS_BitFields EFM32GG942F1024_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG942F1024_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_UNLOCK EFM32GG942F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG942F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG942F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F1024_Alternate_Function EFM32GG942F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG942F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG942F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG942F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg942f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG942F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG942F512_H__\r
-#define __SILICON_LABS_EFM32GG942F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512 EFM32GG942F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_Core EFM32GG942F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG942F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG942F512_Part EFM32GG942F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG942F512)\r
-#define EFM32GG942F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG942F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG942F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG942F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_Peripheral_TypeDefs EFM32GG942F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_DMA EFM32GG942F512 DMA\r
- * @{\r
- * @brief EFM32GG942F512_DMA Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __I uint32_t STATUS; /**< DMA Status Registers */\r
- __O uint32_t CONFIG; /**< DMA Configuration Register */\r
- __IO uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */\r
- __I uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */\r
- __I uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */\r
- __O uint32_t CHSWREQ; /**< Channel Software Request Register */\r
- __IO uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */\r
- __O uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */\r
- __IO uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */\r
- __O uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */\r
- __IO uint32_t CHENS; /**< Channel Enable Set Register */\r
- __O uint32_t CHENC; /**< Channel Enable Clear Register */\r
- __IO uint32_t CHALTS; /**< Channel Alternate Set Register */\r
- __O uint32_t CHALTC; /**< Channel Alternate Clear Register */\r
- __IO uint32_t CHPRIS; /**< Channel Priority Set Register */\r
- __O uint32_t CHPRIC; /**< Channel Priority Clear Register */\r
- uint32_t RESERVED0[3]; /**< Reserved for future use **/\r
- __IO uint32_t ERRORC; /**< Bus Error Clear Register */\r
-\r
- uint32_t RESERVED1[880]; /**< Reserved for future use **/\r
- __I uint32_t CHREQSTATUS; /**< Channel Request Status */\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __I uint32_t CHSREQSTATUS; /**< Channel Single Request Status */\r
-\r
- uint32_t RESERVED3[121]; /**< Reserved for future use **/\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable register */\r
- __IO uint32_t CTRL; /**< DMA Control Register */\r
- __IO uint32_t RDS; /**< DMA Retain Descriptor State */\r
-\r
- uint32_t RESERVED4[2]; /**< Reserved for future use **/\r
- __IO uint32_t LOOP0; /**< Channel 0 Loop Register */\r
- __IO uint32_t LOOP1; /**< Channel 1 Loop Register */\r
- uint32_t RESERVED5[14]; /**< Reserved for future use **/\r
- __IO uint32_t RECT0; /**< Channel 0 Rectangle Register */\r
-\r
- uint32_t RESERVED6[39]; /**< Reserved registers */\r
- DMA_CH_TypeDef CH[12]; /**< Channel registers */\r
-} DMA_TypeDef; /** @} */\r
-\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_CMU EFM32GG942F512 CMU\r
- * @{\r
- * @brief EFM32GG942F512_CMU Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /**< CMU Control Register */\r
- __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */\r
- __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */\r
- __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */\r
- __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */\r
- __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */\r
- __IO uint32_t CALCTRL; /**< Calibration Control Register */\r
- __IO uint32_t CALCNT; /**< Calibration Counter Register */\r
- __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */\r
- __IO uint32_t CMD; /**< Command Register */\r
- __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */\r
- __I uint32_t STATUS; /**< Status Register */\r
- __I uint32_t IF; /**< Interrupt Flag Register */\r
- __IO uint32_t IFS; /**< Interrupt Flag Set Register */\r
- __IO uint32_t IFC; /**< Interrupt Flag Clear Register */\r
- __IO uint32_t IEN; /**< Interrupt Enable Register */\r
- __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */\r
- __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */\r
- uint32_t RESERVED0[2]; /**< Reserved for future use **/\r
- __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */\r
- __IO uint32_t FREEZE; /**< Freeze Register */\r
- __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */\r
- uint32_t RESERVED1[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */\r
-\r
- uint32_t RESERVED2[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED3[1]; /**< Reserved for future use **/\r
- __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */\r
- uint32_t RESERVED4[1]; /**< Reserved for future use **/\r
- __IO uint32_t PCNTCTRL; /**< PCNT Control Register */\r
- __IO uint32_t LCDCTRL; /**< LCD Control Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
- __IO uint32_t LOCK; /**< Configuration Lock Register */\r
-} CMU_TypeDef; /** @} */\r
-\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_PRS EFM32GG942F512 PRS\r
- * @{\r
- * @brief EFM32GG942F512_PRS Register Declaration\r
- *****************************************************************************/\r
-typedef struct\r
-{\r
- __IO uint32_t SWPULSE; /**< Software Pulse Register */\r
- __IO uint32_t SWLEVEL; /**< Software Level Register */\r
- __IO uint32_t ROUTE; /**< I/O Routing Register */\r
-\r
- uint32_t RESERVED0[1]; /**< Reserved registers */\r
- PRS_CH_TypeDef CH[12]; /**< Channel registers */\r
-} PRS_TypeDef; /** @} */\r
-\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG942F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_Peripheral_Base EFM32GG942F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG942F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_Peripheral_Declaration EFM32GG942F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG942F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_BitFields EFM32GG942F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @addtogroup EFM32GG942F512_PRS_Signals\r
- * @{\r
- * @brief PRS Signal names\r
- *****************************************************************************/\r
-#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */\r
-#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */\r
-#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */\r
-#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */\r
-#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */\r
-#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */\r
-#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */\r
-#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */\r
-#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */\r
-#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */\r
-#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */\r
-#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */\r
-#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */\r
-#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */\r
-#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */\r
-#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */\r
-#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */\r
-#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */\r
-#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */\r
-#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */\r
-#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */\r
-#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */\r
-#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */\r
-#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */\r
-#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */\r
-#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */\r
-#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */\r
-#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */\r
-#define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */\r
-#define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */\r
-#define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */\r
-#define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */\r
-#define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */\r
-#define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */\r
-#define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */\r
-#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */\r
-#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */\r
-#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */\r
-#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */\r
-#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */\r
-#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */\r
-#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */\r
-#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */\r
-#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */\r
-#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */\r
-#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */\r
-#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */\r
-#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */\r
-#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */\r
-#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */\r
-#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */\r
-#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */\r
-#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */\r
-#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */\r
-#define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */\r
-#define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */\r
-#define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */\r
-#define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */\r
-#define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */\r
-#define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */\r
-#define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */\r
-#define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */\r
-#define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */\r
-#define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */\r
-#define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */\r
-#define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */\r
-#define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */\r
-#define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */\r
-#define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */\r
-#define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */\r
-#define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */\r
-#define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */\r
-#define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */\r
-#define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */\r
-#define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */\r
-#define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */\r
-#define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */\r
-\r
-/** @} End of group EFM32GG942F512_PRS */\r
-\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_DMA_BitFields EFM32GG942F512_DMA Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for DMA STATUS */\r
-#define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */\r
-#define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */\r
-#define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */\r
-#define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */\r
-#define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */\r
-#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */\r
-#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */\r
-#define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */\r
-#define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */\r
-#define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */\r
-#define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */\r
-#define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */\r
-#define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */\r
-#define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */\r
-\r
-/* Bit fields for DMA CONFIG */\r
-#define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */\r
-#define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */\r
-#define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */\r
-#define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */\r
-#define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */\r
-#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */\r
-#define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */\r
-#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */\r
-#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */\r
-\r
-/* Bit fields for DMA CTRLBASE */\r
-#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */\r
-#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */\r
-#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */\r
-\r
-/* Bit fields for DMA ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */\r
-#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */\r
-#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */\r
-\r
-/* Bit fields for DMA CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */\r
-#define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */\r
-#define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */\r
-\r
-/* Bit fields for DMA CHSWREQ */\r
-#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */\r
-#define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */\r
-#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */\r
-#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */\r
-#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */\r
-#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */\r
-#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */\r
-#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */\r
-#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */\r
-#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */\r
-#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */\r
-#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */\r
-#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */\r
-#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */\r
-#define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */\r
-#define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */\r
-#define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */\r
-#define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */\r
-#define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */\r
-#define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */\r
-#define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */\r
-#define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */\r
-#define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */\r
-#define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */\r
-#define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */\r
-#define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */\r
-#define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */\r
-\r
-/* Bit fields for DMA CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */\r
-#define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */\r
-#define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */\r
-\r
-/* Bit fields for DMA CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */\r
-#define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */\r
-#define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */\r
-#define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */\r
-\r
-/* Bit fields for DMA CHREQMASKS */\r
-#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */\r
-#define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */\r
-#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */\r
-#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */\r
-#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */\r
-#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */\r
-#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */\r
-#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */\r
-#define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */\r
-#define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */\r
-#define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */\r
-#define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */\r
-#define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */\r
-#define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */\r
-#define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */\r
-\r
-/* Bit fields for DMA CHREQMASKC */\r
-#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */\r
-#define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */\r
-#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */\r
-#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */\r
-#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */\r
-#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */\r
-#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */\r
-#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */\r
-#define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */\r
-#define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */\r
-#define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */\r
-#define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */\r
-#define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */\r
-#define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */\r
-#define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */\r
-\r
-/* Bit fields for DMA CHENS */\r
-#define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */\r
-#define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */\r
-#define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */\r
-#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */\r
-#define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */\r
-#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */\r
-#define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */\r
-#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */\r
-#define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */\r
-#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */\r
-#define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */\r
-#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */\r
-#define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */\r
-#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */\r
-#define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */\r
-#define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */\r
-#define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */\r
-#define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */\r
-#define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */\r
-#define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */\r
-#define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */\r
-#define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */\r
-#define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */\r
-#define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */\r
-#define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */\r
-#define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */\r
-#define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */\r
-\r
-/* Bit fields for DMA CHENC */\r
-#define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */\r
-#define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */\r
-#define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */\r
-#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */\r
-#define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */\r
-#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */\r
-#define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */\r
-#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */\r
-#define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */\r
-#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */\r
-#define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */\r
-#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */\r
-#define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */\r
-#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */\r
-#define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */\r
-#define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */\r
-#define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */\r
-#define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */\r
-#define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */\r
-#define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */\r
-#define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */\r
-#define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */\r
-#define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */\r
-#define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */\r
-#define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */\r
-#define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */\r
-#define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */\r
-\r
-/* Bit fields for DMA CHALTS */\r
-#define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */\r
-#define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */\r
-#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */\r
-#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */\r
-#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */\r
-#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */\r
-#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */\r
-#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */\r
-#define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */\r
-#define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */\r
-#define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */\r
-#define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */\r
-#define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */\r
-#define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */\r
-#define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */\r
-#define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */\r
-\r
-/* Bit fields for DMA CHALTC */\r
-#define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */\r
-#define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */\r
-#define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */\r
-#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */\r
-#define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */\r
-#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */\r
-#define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */\r
-#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */\r
-#define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */\r
-#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */\r
-#define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */\r
-#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */\r
-#define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */\r
-#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */\r
-#define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */\r
-#define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */\r
-#define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */\r
-#define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */\r
-#define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */\r
-#define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */\r
-#define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */\r
-#define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */\r
-#define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */\r
-#define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */\r
-#define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */\r
-#define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */\r
-#define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */\r
-\r
-/* Bit fields for DMA CHPRIS */\r
-#define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */\r
-#define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */\r
-#define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */\r
-#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */\r
-#define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */\r
-#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */\r
-#define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */\r
-#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */\r
-#define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */\r
-#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */\r
-#define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */\r
-#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */\r
-#define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */\r
-#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */\r
-#define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */\r
-#define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */\r
-#define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */\r
-#define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */\r
-#define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */\r
-#define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */\r
-#define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */\r
-#define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */\r
-#define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */\r
-#define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */\r
-#define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */\r
-#define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */\r
-#define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */\r
-\r
-/* Bit fields for DMA CHPRIC */\r
-#define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */\r
-#define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */\r
-#define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */\r
-#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */\r
-#define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */\r
-#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */\r
-#define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */\r
-#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */\r
-#define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */\r
-#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */\r
-#define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */\r
-#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */\r
-#define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */\r
-#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */\r
-#define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */\r
-#define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */\r
-#define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */\r
-#define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */\r
-#define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */\r
-#define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */\r
-#define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */\r
-#define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */\r
-#define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */\r
-#define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */\r
-#define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */\r
-#define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */\r
-#define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */\r
-\r
-/* Bit fields for DMA ERRORC */\r
-#define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */\r
-#define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */\r
-#define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */\r
-#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */\r
-#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */\r
-\r
-/* Bit fields for DMA CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */\r
-#define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */\r
-#define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */\r
-#define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */\r
-\r
-/* Bit fields for DMA CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */\r
-#define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */\r
-#define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */\r
-\r
-/* Bit fields for DMA IF */\r
-#define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */\r
-#define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */\r
-#define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */\r
-#define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */\r
-#define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */\r
-#define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */\r
-#define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */\r
-#define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */\r
-#define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */\r
-#define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */\r
-#define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */\r
-#define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */\r
-#define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */\r
-#define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */\r
-#define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */\r
-#define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */\r
-#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */\r
-\r
-/* Bit fields for DMA IFS */\r
-#define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */\r
-#define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */\r
-#define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */\r
-#define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */\r
-#define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */\r
-#define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */\r
-\r
-/* Bit fields for DMA IFC */\r
-#define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */\r
-#define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */\r
-#define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */\r
-#define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */\r
-#define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */\r
-#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */\r
-\r
-/* Bit fields for DMA IEN */\r
-#define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */\r
-#define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */\r
-#define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */\r
-#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */\r
-#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */\r
-#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */\r
-#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */\r
-#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */\r
-#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */\r
-#define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */\r
-#define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */\r
-#define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */\r
-#define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */\r
-#define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */\r
-#define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */\r
-#define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */\r
-#define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */\r
-#define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */\r
-#define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */\r
-#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */\r
-\r
-/* Bit fields for DMA CTRL */\r
-#define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */\r
-#define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */\r
-#define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */\r
-#define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */\r
-#define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */\r
-#define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */\r
-#define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */\r
-\r
-/* Bit fields for DMA RDS */\r
-#define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */\r
-#define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */\r
-#define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */\r
-#define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */\r
-#define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */\r
-#define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */\r
-#define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */\r
-#define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */\r
-#define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */\r
-#define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */\r
-#define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */\r
-#define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */\r
-#define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */\r
-#define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */\r
-#define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */\r
-#define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */\r
-#define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */\r
-\r
-/* Bit fields for DMA LOOP0 */\r
-#define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */\r
-#define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */\r
-#define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */\r
-#define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */\r
-#define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */\r
-\r
-/* Bit fields for DMA LOOP1 */\r
-#define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */\r
-#define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */\r
-#define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */\r
-#define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */\r
-#define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */\r
-#define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */\r
-#define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */\r
-#define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */\r
-\r
-/* Bit fields for DMA RECT0 */\r
-#define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */\r
-#define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */\r
-#define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */\r
-#define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */\r
-#define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-#define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */\r
-#define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */\r
-#define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */\r
-\r
-/* Bit fields for DMA CH_CTRL */\r
-#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */\r
-#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */\r
-#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */\r
-#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG942F512_DMA */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_CMU_BitFields EFM32GG942F512_CMU Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for CMU CTRL */\r
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */\r
-#define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */\r
-#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */\r
-#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */\r
-#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */\r
-#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */\r
-#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */\r
-#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */\r
-#define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */\r
-#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */\r
-#define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */\r
-#define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */\r
-#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */\r
-#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */\r
-#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */\r
-#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */\r
-#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */\r
-#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */\r
-#define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */\r
-#define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */\r
-#define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */\r
-#define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */\r
-#define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */\r
-#define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */\r
-#define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */\r
-#define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */\r
-\r
-/* Bit fields for CMU HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */\r
-#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */\r
-#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */\r
-\r
-/* Bit fields for CMU HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */\r
-#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */\r
-#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */\r
-\r
-/* Bit fields for CMU HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */\r
-#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */\r
-#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */\r
-#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */\r
-\r
-/* Bit fields for CMU LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */\r
-#define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */\r
-#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */\r
-\r
-/* Bit fields for CMU AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */\r
-#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */\r
-#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */\r
-#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */\r
-\r
-/* Bit fields for CMU CALCTRL */\r
-#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */\r
-#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */\r
-#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */\r
-#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */\r
-#define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */\r
-#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */\r
-#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */\r
-\r
-/* Bit fields for CMU CALCNT */\r
-#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */\r
-#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */\r
-#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */\r
-#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */\r
-\r
-/* Bit fields for CMU OSCENCMD */\r
-#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */\r
-#define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */\r
-#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */\r
-#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */\r
-#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */\r
-#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */\r
-#define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */\r
-#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */\r
-#define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */\r
-#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */\r
-#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */\r
-#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */\r
-#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */\r
-#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */\r
-#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */\r
-#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */\r
-#define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */\r
-#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */\r
-#define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */\r
-#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */\r
-#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */\r
-\r
-/* Bit fields for CMU CMD */\r
-#define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */\r
-#define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */\r
-#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */\r
-#define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */\r
-#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */\r
-#define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */\r
-#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */\r
-#define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */\r
-#define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */\r
-#define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */\r
-\r
-/* Bit fields for CMU LFCLKSEL */\r
-#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */\r
-#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */\r
-#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */\r
-#define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */\r
-#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */\r
-#define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */\r
-#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */\r
-#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */\r
-#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */\r
-\r
-/* Bit fields for CMU STATUS */\r
-#define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */\r
-#define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */\r
-#define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */\r
-#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */\r
-#define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */\r
-#define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */\r
-#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */\r
-#define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */\r
-#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */\r
-#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */\r
-#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */\r
-#define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */\r
-#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */\r
-#define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */\r
-#define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */\r
-#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */\r
-#define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */\r
-#define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */\r
-#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */\r
-#define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */\r
-#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */\r
-#define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */\r
-#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */\r
-#define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */\r
-#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */\r
-#define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */\r
-#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */\r
-#define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */\r
-#define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */\r
-#define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */\r
-#define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */\r
-#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */\r
-#define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */\r
-\r
-/* Bit fields for CMU IF */\r
-#define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */\r
-#define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */\r
-#define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */\r
-#define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */\r
-#define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */\r
-#define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */\r
-#define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */\r
-#define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */\r
-#define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */\r
-#define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */\r
-\r
-/* Bit fields for CMU IFS */\r
-#define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */\r
-#define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */\r
-#define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */\r
-#define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */\r
-#define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */\r
-#define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */\r
-#define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */\r
-\r
-/* Bit fields for CMU IFC */\r
-#define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */\r
-#define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */\r
-#define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */\r
-#define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */\r
-#define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */\r
-#define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */\r
-\r
-/* Bit fields for CMU IEN */\r
-#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */\r
-#define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */\r
-#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */\r
-#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */\r
-#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */\r
-#define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */\r
-#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */\r
-#define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */\r
-#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */\r
-#define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */\r
-#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */\r
-#define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */\r
-#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */\r
-#define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */\r
-#define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */\r
-#define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */\r
-\r
-/* Bit fields for CMU HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */\r
-#define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */\r
-#define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */\r
-#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */\r
-#define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */\r
-#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */\r
-#define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */\r
-#define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */\r
-#define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */\r
-#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */\r
-#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */\r
-\r
-/* Bit fields for CMU HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */\r
-#define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */\r
-#define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */\r
-#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */\r
-#define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */\r
-#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */\r
-#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */\r
-#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */\r
-#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */\r
-#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */\r
-#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */\r
-#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */\r
-#define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */\r
-#define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */\r
-#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */\r
-#define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */\r
-#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */\r
-#define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */\r
-#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */\r
-#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */\r
-#define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */\r
-#define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */\r
-#define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */\r
-\r
-/* Bit fields for CMU SYNCBUSY */\r
-#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */\r
-#define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */\r
-#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */\r
-#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */\r
-#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */\r
-#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */\r
-#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */\r
-\r
-/* Bit fields for CMU FREEZE */\r
-#define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */\r
-#define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */\r
-#define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */\r
-#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */\r
-#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */\r
-\r
-/* Bit fields for CMU LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */\r
-#define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */\r
-#define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */\r
-#define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */\r
-#define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */\r
-#define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */\r
-#define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */\r
-\r
-/* Bit fields for CMU LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */\r
-#define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */\r
-#define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */\r
-#define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */\r
-\r
-/* Bit fields for CMU LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */\r
-#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */\r
-#define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */\r
-#define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */\r
-#define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */\r
-\r
-/* Bit fields for CMU LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */\r
-#define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */\r
-#define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */\r
-\r
-/* Bit fields for CMU PCNTCTRL */\r
-#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */\r
-#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */\r
-#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */\r
-#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */\r
-\r
-/* Bit fields for CMU LCDCTRL */\r
-#define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */\r
-#define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */\r
-#define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */\r
-#define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */\r
-#define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */\r
-#define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */\r
-\r
-/* Bit fields for CMU ROUTE */\r
-#define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */\r
-#define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */\r
-#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */\r
-#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */\r
-#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */\r
-#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */\r
-#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */\r
-#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */\r
-\r
-/* Bit fields for CMU LOCK */\r
-#define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */\r
-#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */\r
-#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */\r
-#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */\r
-#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */\r
-\r
-/** @} End of group EFM32GG942F512_CMU */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_PRS_BitFields EFM32GG942F512_PRS Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-/* Bit fields for PRS SWPULSE */\r
-#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */\r
-#define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */\r
-#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */\r
-#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */\r
-#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */\r
-#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */\r
-#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */\r
-#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */\r
-#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */\r
-#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */\r
-#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */\r
-#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */\r
-#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */\r
-#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */\r
-#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */\r
-#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */\r
-#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */\r
-#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */\r
-#define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */\r
-#define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */\r
-#define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */\r
-#define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */\r
-#define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */\r
-#define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */\r
-#define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */\r
-#define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */\r
-#define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */\r
-\r
-/* Bit fields for PRS SWLEVEL */\r
-#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */\r
-#define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */\r
-#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */\r
-#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */\r
-#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */\r
-#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */\r
-#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */\r
-#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */\r
-#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */\r
-#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */\r
-#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */\r
-#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */\r
-#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */\r
-#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */\r
-#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */\r
-#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */\r
-#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */\r
-#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */\r
-#define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */\r
-#define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */\r
-#define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */\r
-#define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */\r
-#define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */\r
-#define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */\r
-#define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */\r
-#define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */\r
-#define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */\r
-\r
-/* Bit fields for PRS ROUTE */\r
-#define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */\r
-#define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */\r
-#define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */\r
-#define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */\r
-#define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */\r
-#define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */\r
-#define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */\r
-#define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */\r
-#define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */\r
-#define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */\r
-#define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */\r
-#define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */\r
-#define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */\r
-\r
-/* Bit fields for PRS CH_CTRL */\r
-#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */\r
-#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */\r
-#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */\r
-#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */\r
-#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */\r
-#define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */\r
-#define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */\r
-#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */\r
-\r
-/** @} End of group EFM32GG942F512_PRS */\r
-\r
-\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_UNLOCK EFM32GG942F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG942F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG942F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG942F512_Alternate_Function EFM32GG942F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG942F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG942F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG942F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg980f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG980F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG980F1024_H__\r
-#define __SILICON_LABS_EFM32GG980F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024 EFM32GG980F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_Core EFM32GG980F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG980F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG980F1024_Part EFM32GG980F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG980F1024)\r
-#define EFM32GG980F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG980F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG980F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG980F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_Peripheral_TypeDefs EFM32GG980F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG980F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_Peripheral_Base EFM32GG980F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG980F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_Peripheral_Declaration EFM32GG980F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG980F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_BitFields EFM32GG980F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_UNLOCK EFM32GG980F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG980F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG980F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F1024_Alternate_Function EFM32GG980F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG980F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG980F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG980F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg980f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG980F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG980F512_H__\r
-#define __SILICON_LABS_EFM32GG980F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512 EFM32GG980F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_Core EFM32GG980F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG980F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG980F512_Part EFM32GG980F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG980F512)\r
-#define EFM32GG980F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG980F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG980F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG980F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_Peripheral_TypeDefs EFM32GG980F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG980F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_Peripheral_Base EFM32GG980F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG980F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_Peripheral_Declaration EFM32GG980F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG980F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_BitFields EFM32GG980F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_UNLOCK EFM32GG980F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG980F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG980F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG980F512_Alternate_Function EFM32GG980F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG980F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG980F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG980F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg990f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG990F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG990F512_H__\r
-#define __SILICON_LABS_EFM32GG990F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512 EFM32GG990F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_Core EFM32GG990F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG990F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG990F512_Part EFM32GG990F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG990F512)\r
-#define EFM32GG990F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG990F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG990F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG990F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_Peripheral_TypeDefs EFM32GG990F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG990F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_Peripheral_Base EFM32GG990F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG990F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_Peripheral_Declaration EFM32GG990F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG990F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_BitFields EFM32GG990F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_UNLOCK EFM32GG990F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG990F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG990F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG990F512_Alternate_Function EFM32GG990F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG990F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG990F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG990F512_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg995f1024.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG995F1024\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG995F1024_H__\r
-#define __SILICON_LABS_EFM32GG995F1024_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024 EFM32GG995F1024\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_Core EFM32GG995F1024 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG995F1024_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG995F1024_Part EFM32GG995F1024 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG995F1024)\r
-#define EFM32GG995F1024 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG995F1024" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG995F1024 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG995F1024_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_Peripheral_TypeDefs EFM32GG995F1024 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG995F1024_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_Peripheral_Base EFM32GG995F1024 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG995F1024_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_Peripheral_Declaration EFM32GG995F1024 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG995F1024_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_BitFields EFM32GG995F1024 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_UNLOCK EFM32GG995F1024 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG995F1024_UNLOCK */\r
-\r
-/** @} End of group EFM32GG995F1024_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F1024_Alternate_Function EFM32GG995F1024 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG995F1024_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG995F1024 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG995F1024_H__ */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file efm32gg995f512.h\r
- * @brief CMSIS Cortex-M Peripheral Access Layer Header File\r
- * for EFM32GG995F512\r
- * @version 4.0.0\r
- ******************************************************************************\r
- * @section License\r
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>\r
- ******************************************************************************\r
- *\r
- * Permission is granted to anyone to use this software for any purpose,\r
- * including commercial applications, and to alter it and redistribute it\r
- * freely, subject to the following restrictions:\r
- *\r
- * 1. The origin of this software must not be misrepresented; you must not\r
- * claim that you wrote the original software.@n\r
- * 2. Altered source versions must be plainly marked as such, and must not be\r
- * misrepresented as being the original software.@n\r
- * 3. This notice may not be removed or altered from any source distribution.\r
- *\r
- * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.\r
- * has no obligation to support this Software. Silicon Laboratories, Inc. is\r
- * providing the Software "AS IS", with no express or implied warranties of any\r
- * kind, including, but not limited to, any implied warranties of\r
- * merchantability or fitness for any particular purpose or warranties against\r
- * infringement of any proprietary rights of a third party.\r
- *\r
- * Silicon Laboratories, Inc. will not be liable for any consequential,\r
- * incidental, or special damages, or any other relief, or for any claim by\r
- * any third party, arising from your use of this Software.\r
- *\r
- *****************************************************************************/\r
-\r
-#ifndef __SILICON_LABS_EFM32GG995F512_H__\r
-#define __SILICON_LABS_EFM32GG995F512_H__\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-/**************************************************************************//**\r
- * @addtogroup Parts\r
- * @{\r
- *****************************************************************************/\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512 EFM32GG995F512\r
- * @{\r
- *****************************************************************************/\r
-\r
-/** Interrupt Number Definition */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers *******************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */\r
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** EFM32G Peripheral Interrupt Numbers **********************************************/\r
- DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */\r
- GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */\r
- TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */\r
- USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */\r
- USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */\r
- USB_IRQn = 5, /*!< 16+5 EFM32 USB Interrupt */\r
- ACMP0_IRQn = 6, /*!< 16+6 EFM32 ACMP0 Interrupt */\r
- ADC0_IRQn = 7, /*!< 16+7 EFM32 ADC0 Interrupt */\r
- DAC0_IRQn = 8, /*!< 16+8 EFM32 DAC0 Interrupt */\r
- I2C0_IRQn = 9, /*!< 16+9 EFM32 I2C0 Interrupt */\r
- I2C1_IRQn = 10, /*!< 16+10 EFM32 I2C1 Interrupt */\r
- GPIO_ODD_IRQn = 11, /*!< 16+11 EFM32 GPIO_ODD Interrupt */\r
- TIMER1_IRQn = 12, /*!< 16+12 EFM32 TIMER1 Interrupt */\r
- TIMER2_IRQn = 13, /*!< 16+13 EFM32 TIMER2 Interrupt */\r
- TIMER3_IRQn = 14, /*!< 16+14 EFM32 TIMER3 Interrupt */\r
- USART1_RX_IRQn = 15, /*!< 16+15 EFM32 USART1_RX Interrupt */\r
- USART1_TX_IRQn = 16, /*!< 16+16 EFM32 USART1_TX Interrupt */\r
- LESENSE_IRQn = 17, /*!< 16+17 EFM32 LESENSE Interrupt */\r
- USART2_RX_IRQn = 18, /*!< 16+18 EFM32 USART2_RX Interrupt */\r
- USART2_TX_IRQn = 19, /*!< 16+19 EFM32 USART2_TX Interrupt */\r
- UART0_RX_IRQn = 20, /*!< 16+20 EFM32 UART0_RX Interrupt */\r
- UART0_TX_IRQn = 21, /*!< 16+21 EFM32 UART0_TX Interrupt */\r
- UART1_RX_IRQn = 22, /*!< 16+22 EFM32 UART1_RX Interrupt */\r
- UART1_TX_IRQn = 23, /*!< 16+23 EFM32 UART1_TX Interrupt */\r
- LEUART0_IRQn = 24, /*!< 16+24 EFM32 LEUART0 Interrupt */\r
- LEUART1_IRQn = 25, /*!< 16+25 EFM32 LEUART1 Interrupt */\r
- LETIMER0_IRQn = 26, /*!< 16+26 EFM32 LETIMER0 Interrupt */\r
- PCNT0_IRQn = 27, /*!< 16+27 EFM32 PCNT0 Interrupt */\r
- PCNT1_IRQn = 28, /*!< 16+28 EFM32 PCNT1 Interrupt */\r
- PCNT2_IRQn = 29, /*!< 16+29 EFM32 PCNT2 Interrupt */\r
- RTC_IRQn = 30, /*!< 16+30 EFM32 RTC Interrupt */\r
- BURTC_IRQn = 31, /*!< 16+31 EFM32 BURTC Interrupt */\r
- CMU_IRQn = 32, /*!< 16+32 EFM32 CMU Interrupt */\r
- VCMP_IRQn = 33, /*!< 16+33 EFM32 VCMP Interrupt */\r
- LCD_IRQn = 34, /*!< 16+34 EFM32 LCD Interrupt */\r
- MSC_IRQn = 35, /*!< 16+35 EFM32 MSC Interrupt */\r
- AES_IRQn = 36, /*!< 16+36 EFM32 AES Interrupt */\r
- EBI_IRQn = 37, /*!< 16+37 EFM32 EBI Interrupt */\r
- EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */\r
-} IRQn_Type;\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_Core EFM32GG995F512 Core\r
- * @{\r
- * @brief Processor and Core Peripheral Section\r
- *****************************************************************************/\r
-#define __MPU_PRESENT 1 /**< Presence of MPU */\r
-#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */\r
-#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */\r
-\r
-/** @} End of group EFM32GG995F512_Core */\r
-\r
-/**************************************************************************//**\r
-* @defgroup EFM32GG995F512_Part EFM32GG995F512 Part\r
-* @{\r
-******************************************************************************/\r
-\r
-/** Part family */\r
-#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */\r
-#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */\r
-#define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */\r
-#define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */\r
-\r
-/* If part number is not defined as compiler option, define it */\r
-#if !defined(EFM32GG995F512)\r
-#define EFM32GG995F512 1 /**< Giant/Leopard Gecko Part */\r
-#endif\r
-\r
-/** Configure part number */\r
-#define PART_NUMBER "EFM32GG995F512" /**< Part Number */\r
-\r
-/** Memory Base addresses and limits */\r
-#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */\r
-#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */\r
-#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */\r
-#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */\r
-#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */\r
-#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */\r
-#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */\r
-#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */\r
-#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */\r
-#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */\r
-#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */\r
-#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */\r
-#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */\r
-#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */\r
-#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */\r
-#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */\r
-#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */\r
-#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */\r
-#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */\r
-#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */\r
-#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */\r
-#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */\r
-#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */\r
-#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */\r
-#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */\r
-#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */\r
-#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */\r
-#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */\r
-#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */\r
-#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */\r
-#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */\r
-#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */\r
-\r
-/** Bit banding area */\r
-#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */\r
-#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */\r
-\r
-/** Flash and SRAM limits for EFM32GG995F512 */\r
-#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */\r
-#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */\r
-#define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */\r
-#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */\r
-#define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */\r
-#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */\r
-#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */\r
-#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */\r
-\r
-/** AF channels connect the different on-chip peripherals with the af-mux */\r
-#define AFCHAN_MAX 163\r
-#define AFCHANLOC_MAX 7\r
-/** Analog AF channels */\r
-#define AFACHAN_MAX 53\r
-\r
-/* Part number capabilities */\r
-\r
-#define LETIMER_PRESENT /**< LETIMER is available in this part */\r
-#define LETIMER_COUNT 1 /**< 1 LETIMERs available */\r
-#define USART_PRESENT /**< USART is available in this part */\r
-#define USART_COUNT 3 /**< 3 USARTs available */\r
-#define UART_PRESENT /**< UART is available in this part */\r
-#define UART_COUNT 2 /**< 2 UARTs available */\r
-#define TIMER_PRESENT /**< TIMER is available in this part */\r
-#define TIMER_COUNT 4 /**< 4 TIMERs available */\r
-#define ACMP_PRESENT /**< ACMP is available in this part */\r
-#define ACMP_COUNT 2 /**< 2 ACMPs available */\r
-#define I2C_PRESENT /**< I2C is available in this part */\r
-#define I2C_COUNT 2 /**< 2 I2Cs available */\r
-#define LEUART_PRESENT /**< LEUART is available in this part */\r
-#define LEUART_COUNT 2 /**< 2 LEUARTs available */\r
-#define PCNT_PRESENT /**< PCNT is available in this part */\r
-#define PCNT_COUNT 3 /**< 3 PCNTs available */\r
-#define ADC_PRESENT /**< ADC is available in this part */\r
-#define ADC_COUNT 1 /**< 1 ADCs available */\r
-#define DAC_PRESENT /**< DAC is available in this part */\r
-#define DAC_COUNT 1 /**< 1 DACs available */\r
-#define DMA_PRESENT\r
-#define DMA_COUNT 1\r
-#define AES_PRESENT\r
-#define AES_COUNT 1\r
-#define USBC_PRESENT\r
-#define USBC_COUNT 1\r
-#define USB_PRESENT\r
-#define USB_COUNT 1\r
-#define LE_PRESENT\r
-#define LE_COUNT 1\r
-#define MSC_PRESENT\r
-#define MSC_COUNT 1\r
-#define EMU_PRESENT\r
-#define EMU_COUNT 1\r
-#define RMU_PRESENT\r
-#define RMU_COUNT 1\r
-#define CMU_PRESENT\r
-#define CMU_COUNT 1\r
-#define LESENSE_PRESENT\r
-#define LESENSE_COUNT 1\r
-#define RTC_PRESENT\r
-#define RTC_COUNT 1\r
-#define EBI_PRESENT\r
-#define EBI_COUNT 1\r
-#define GPIO_PRESENT\r
-#define GPIO_COUNT 1\r
-#define VCMP_PRESENT\r
-#define VCMP_COUNT 1\r
-#define PRS_PRESENT\r
-#define PRS_COUNT 1\r
-#define OPAMP_PRESENT\r
-#define OPAMP_COUNT 1\r
-#define BU_PRESENT\r
-#define BU_COUNT 1\r
-#define LCD_PRESENT\r
-#define LCD_COUNT 1\r
-#define BURTC_PRESENT\r
-#define BURTC_COUNT 1\r
-#define HFXTAL_PRESENT\r
-#define HFXTAL_COUNT 1\r
-#define LFXTAL_PRESENT\r
-#define LFXTAL_COUNT 1\r
-#define WDOG_PRESENT\r
-#define WDOG_COUNT 1\r
-#define DBG_PRESENT\r
-#define DBG_COUNT 1\r
-#define ETM_PRESENT\r
-#define ETM_COUNT 1\r
-#define BOOTLOADER_PRESENT\r
-#define BOOTLOADER_COUNT 1\r
-#define ANALOG_PRESENT\r
-#define ANALOG_COUNT 1\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_efm32gg.h" /* System Header */\r
-\r
-/** @} End of group EFM32GG995F512_Part */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_Peripheral_TypeDefs EFM32GG995F512 Peripheral TypeDefs\r
- * @{\r
- * @brief Device Specific Peripheral Register Structures\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_dma_ch.h"\r
-#include "efm32gg_dma.h"\r
-#include "efm32gg_aes.h"\r
-#include "efm32gg_usb_hc.h"\r
-#include "efm32gg_usb_diep.h"\r
-#include "efm32gg_usb_doep.h"\r
-#include "efm32gg_usb.h"\r
-#include "efm32gg_msc.h"\r
-#include "efm32gg_emu.h"\r
-#include "efm32gg_rmu.h"\r
-#include "efm32gg_cmu.h"\r
-#include "efm32gg_lesense_st.h"\r
-#include "efm32gg_lesense_buf.h"\r
-#include "efm32gg_lesense_ch.h"\r
-#include "efm32gg_lesense.h"\r
-#include "efm32gg_rtc.h"\r
-#include "efm32gg_letimer.h"\r
-#include "efm32gg_ebi.h"\r
-#include "efm32gg_usart.h"\r
-#include "efm32gg_timer_cc.h"\r
-#include "efm32gg_timer.h"\r
-#include "efm32gg_acmp.h"\r
-#include "efm32gg_i2c.h"\r
-#include "efm32gg_gpio_p.h"\r
-#include "efm32gg_gpio.h"\r
-#include "efm32gg_vcmp.h"\r
-#include "efm32gg_prs_ch.h"\r
-#include "efm32gg_prs.h"\r
-#include "efm32gg_leuart.h"\r
-#include "efm32gg_pcnt.h"\r
-#include "efm32gg_adc.h"\r
-#include "efm32gg_dac.h"\r
-#include "efm32gg_lcd.h"\r
-#include "efm32gg_burtc_ret.h"\r
-#include "efm32gg_burtc.h"\r
-#include "efm32gg_wdog.h"\r
-#include "efm32gg_etm.h"\r
-#include "efm32gg_dma_descriptor.h"\r
-#include "efm32gg_devinfo.h"\r
-#include "efm32gg_romtable.h"\r
-#include "efm32gg_calibrate.h"\r
-\r
-/** @} End of group EFM32GG995F512_Peripheral_TypeDefs */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_Peripheral_Base EFM32GG995F512 Peripheral Memory Map\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA_BASE (0x400C2000UL) /**< DMA base address */\r
-#define AES_BASE (0x400E0000UL) /**< AES base address */\r
-#define USB_BASE (0x400C4000UL) /**< USB base address */\r
-#define MSC_BASE (0x400C0000UL) /**< MSC base address */\r
-#define EMU_BASE (0x400C6000UL) /**< EMU base address */\r
-#define RMU_BASE (0x400CA000UL) /**< RMU base address */\r
-#define CMU_BASE (0x400C8000UL) /**< CMU base address */\r
-#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */\r
-#define RTC_BASE (0x40080000UL) /**< RTC base address */\r
-#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */\r
-#define EBI_BASE (0x40008000UL) /**< EBI base address */\r
-#define USART0_BASE (0x4000C000UL) /**< USART0 base address */\r
-#define USART1_BASE (0x4000C400UL) /**< USART1 base address */\r
-#define USART2_BASE (0x4000C800UL) /**< USART2 base address */\r
-#define UART0_BASE (0x4000E000UL) /**< UART0 base address */\r
-#define UART1_BASE (0x4000E400UL) /**< UART1 base address */\r
-#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */\r
-#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */\r
-#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */\r
-#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */\r
-#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */\r
-#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */\r
-#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */\r
-#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */\r
-#define GPIO_BASE (0x40006000UL) /**< GPIO base address */\r
-#define VCMP_BASE (0x40000000UL) /**< VCMP base address */\r
-#define PRS_BASE (0x400CC000UL) /**< PRS base address */\r
-#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */\r
-#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */\r
-#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */\r
-#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */\r
-#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */\r
-#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */\r
-#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */\r
-#define LCD_BASE (0x4008A000UL) /**< LCD base address */\r
-#define BURTC_BASE (0x40081000UL) /**< BURTC base address */\r
-#define WDOG_BASE (0x40088000UL) /**< WDOG base address */\r
-#define ETM_BASE (0xE0041000UL) /**< ETM base address */\r
-#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */\r
-#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */\r
-#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */\r
-#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */\r
-#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */\r
-\r
-/** @} End of group EFM32GG995F512_Peripheral_Base */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_Peripheral_Declaration EFM32GG995F512 Peripheral Declarations\r
- * @{\r
- *****************************************************************************/\r
-\r
-#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */\r
-#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */\r
-#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */\r
-#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */\r
-#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */\r
-#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */\r
-#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */\r
-#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */\r
-#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */\r
-#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */\r
-#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */\r
-#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */\r
-#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */\r
-#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */\r
-#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */\r
-#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */\r
-#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */\r
-#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */\r
-#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */\r
-#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */\r
-#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */\r
-#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */\r
-#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */\r
-#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */\r
-#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */\r
-#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */\r
-#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */\r
-#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */\r
-#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */\r
-#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */\r
-#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */\r
-#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */\r
-#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */\r
-#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */\r
-#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */\r
-#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */\r
-#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */\r
-#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */\r
-#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */\r
-#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */\r
-\r
-/** @} End of group EFM32GG995F512_Peripheral_Declaration */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_BitFields EFM32GG995F512 Bit Fields\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_prs_signals.h"\r
-#include "efm32gg_dmareq.h"\r
-#include "efm32gg_dmactrl.h"\r
-#include "efm32gg_uart.h"\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_UNLOCK EFM32GG995F512 Unlock Codes\r
- * @{\r
- *****************************************************************************/\r
-#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */\r
-#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */\r
-#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */\r
-#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */\r
-#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */\r
-#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */\r
-\r
-/** @} End of group EFM32GG995F512_UNLOCK */\r
-\r
-/** @} End of group EFM32GG995F512_BitFields */\r
-\r
-/**************************************************************************//**\r
- * @defgroup EFM32GG995F512_Alternate_Function EFM32GG995F512 Alternate Function\r
- * @{\r
- *****************************************************************************/\r
-\r
-#include "efm32gg_af_ports.h"\r
-#include "efm32gg_af_pins.h"\r
-\r
-/** @} End of group EFM32GG995F512_Alternate_Function */\r
-\r
-/**************************************************************************//**\r
- * @brief Set the value of a bit field within a register.\r
- *\r
- * @param REG\r
- * The register to update\r
- * @param MASK\r
- * The mask for the bit field to update\r
- * @param VALUE\r
- * The value to write to the bit field\r
- * @param OFFSET\r
- * The number of bits that the field is offset within the register.\r
- * 0 (zero) means LSB.\r
- *****************************************************************************/\r
-#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \\r
- REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));\r
-\r
-/** @} End of group EFM32GG995F512 */\r
-\r
-/** @} End of group Parts */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-#endif /* __SILICON_LABS_EFM32GG995F512_H__ */\r
/* SiLabs includes. */\r
#include "em_chip.h"\r
#include "bsp.h"\r
-#include "segmentlcd.h"\r
+#include "bsp_trace.h"\r
#include "sleep.h"\r
\r
/* Set mainCREATE_LOW_POWER_DEMO to one to run the simple blinky demo, or 0 to\r
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );\r
void vApplicationTickHook( void );\r
\r
-\r
-// SegmentLCD_Write(text);\r
-\r
/*-----------------------------------------------------------*/\r
\r
int main( void )\r
{\r
/* Library initialisation routines. */\r
CHIP_Init();\r
-//_RB_ BSP_TraceProfilerSetup();\r
+ BSP_TraceProfilerSetup();\r
SLEEP_Init( NULL, NULL );\r
- SegmentLCD_Init( false );\r
BSP_LedsInit();\r
\r
#if (configSLEEP_MODE < 3)\r
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