+;*****************************************************************************/\r
+; * @file startup_XMC1300.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC1300 Device Series\r
+; * @version V1.00\r
+; * @date 21. Jan. 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+; <h> Clock system handling by SSW\r
+; <h> CLK_VAL1 Configuration\r
+; <o0.0..7> FDIV Fractional Divider Selection\r
+; <o0.8..15> IDIV Divider Selection\r
+; <0=> Divider is bypassed\r
+; <1=> MCLK = 32 MHz\r
+; <2=> MCLK = 16 MHz\r
+; <3=> MCLK = 10.67 MHz\r
+; <4=> MCLK = 8 MHz\r
+; <254=> MCLK = 126 kHz\r
+; <255=> MCLK = 125.5 kHz\r
+; <o0.16> PCLKSEL PCLK Clock Select\r
+; <0=> PCLK = MCLK\r
+; <1=> PCLK = 2 x MCLK\r
+; <o0.17..19> RTCCLKSEL RTC Clock Select\r
+; <0=> 32.768kHz standby clock\r
+; <1=> 32.768kHz external clock from ERU0.IOUT0\r
+; <2=> 32.768kHz external clock from ACMP0.OUT\r
+; <3=> 32.768kHz external clock from ACMP1.OUT\r
+; <4=> 32.768kHz external clock from ACMP2.OUT\r
+; <5=> Reserved\r
+; <6=> Reserved\r
+; <7=> Reserved\r
+; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
+; </h>\r
+CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000\r
+\r
+; <h> CLK_VAL2 Configuration\r
+; <o0.0> disable VADC and SHS Gating\r
+; <o0.1> disable CCU80 Gating\r
+; <o0.2> disable CCU40 Gating\r
+; <o0.3> disable USIC0 Gating\r
+; <o0.4> disable BCCU0 Gating\r
+; <o0.5> disable LEDTS0 Gating\r
+; <o0.6> disable LEDTS1 Gating\r
+; <o0.7> disable POSIF0 Gating\r
+; <o0.8> disable MATH Gating\r
+; <o0.9> disable WDT Gating\r
+; <o0.10> disable RTC Gating\r
+; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
+; </h>\r
+CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000\r
+; </h>\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ;* Top of Stack\r
+ DCD Reset_Handler ;* Reset Handler\r
+ DCD 0 ;* Not used\r
+ DCD 0 ;* Not Used\r
+ DCD CLK_VAL1_Val ;* CLK_VAL1\r
+ DCD CLK_VAL2_Val ;* CLK_VAL2\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
+\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================== */\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR R0, =__initial_sp\r
+ MOV SP, R0\r
+\r
+ ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
+ ; The real veneers will be copied later from the scatter loader before reaching main.\r
+ ; This init code should handle an exception before the real veneers are copied.\r
+SRAM_BASE EQU 0x20000000\r
+VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
+\r
+ LDR R1, =SRAM_BASE\r
+ LDR R2, =VENEER_INIT_CODE \r
+ MOVS R0, #48 ; Veneer 0..47\r
+Init_Veneers\r
+ STR R2, [R1]\r
+ ADDS R1, #4\r
+ SUBS R0, R0, #1\r
+ BNE Init_Veneers\r
+\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+\r
+\r
+ ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ; weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+;* ========================================================================== */\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
+;* Default exception Handlers - Users may override this default functionality\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler\\r
+ PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler\\r
+ PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler\\r
+ PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+;* IRQ Handlers\r
+\r
+Default_Handler PROC\r
+ EXPORT SCU_0_IRQHandler [WEAK]\r
+ EXPORT SCU_1_IRQHandler [WEAK]\r
+ EXPORT SCU_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_0_IRQHandler [WEAK]\r
+ EXPORT ERU0_1_IRQHandler [WEAK]\r
+ EXPORT ERU0_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_3_IRQHandler [WEAK]\r
+ EXPORT MATH0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_1_IRQHandler [WEAK]\r
+ EXPORT USIC0_2_IRQHandler [WEAK]\r
+ EXPORT USIC0_3_IRQHandler [WEAK]\r
+ EXPORT USIC0_4_IRQHandler [WEAK]\r
+ EXPORT USIC0_5_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_0_IRQHandler [WEAK]\r
+ EXPORT CCU40_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_2_IRQHandler [WEAK]\r
+ EXPORT CCU40_3_IRQHandler [WEAK]\r
+ EXPORT CCU80_0_IRQHandler [WEAK]\r
+ EXPORT CCU80_1_IRQHandler [WEAK]\r
+ EXPORT POSIF0_0_IRQHandler [WEAK]\r
+ EXPORT POSIF0_1_IRQHandler [WEAK]\r
+ EXPORT LEDTS0_0_IRQHandler [WEAK]\r
+ EXPORT LEDTS1_0_IRQHandler [WEAK]\r
+ EXPORT BCCU0_0_IRQHandler [WEAK]\r
+\r
+SCU_0_IRQHandler\r
+SCU_1_IRQHandler\r
+SCU_2_IRQHandler\r
+ERU0_0_IRQHandler\r
+ERU0_1_IRQHandler\r
+ERU0_2_IRQHandler\r
+ERU0_3_IRQHandler\r
+MATH0_0_IRQHandler\r
+USIC0_0_IRQHandler\r
+USIC0_1_IRQHandler\r
+USIC0_2_IRQHandler\r
+USIC0_3_IRQHandler\r
+USIC0_4_IRQHandler\r
+USIC0_5_IRQHandler\r
+VADC0_C0_0_IRQHandler\r
+VADC0_C0_1_IRQHandler\r
+VADC0_G0_0_IRQHandler\r
+VADC0_G0_1_IRQHandler\r
+VADC0_G1_0_IRQHandler\r
+VADC0_G1_1_IRQHandler\r
+CCU40_0_IRQHandler\r
+CCU40_1_IRQHandler\r
+CCU40_2_IRQHandler\r
+CCU40_3_IRQHandler\r
+CCU80_0_IRQHandler\r
+CCU80_1_IRQHandler\r
+POSIF0_0_IRQHandler\r
+POSIF0_1_IRQHandler\r
+LEDTS0_0_IRQHandler\r
+LEDTS1_0_IRQHandler\r
+BCCU0_0_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowClkInitByStartup Handler */\r
+AllowClkInitByStartup PROC\r
+ EXPORT AllowClkInitByStartup [WEAK]\r
+ MOVS R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
+; Veneers are located to fix SRAM Address 0x2000'0000\r
+ AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
+\r
+; Each Veneer has exactly a lengs of 4 Byte\r
+\r
+ MACRO\r
+ STAYHERE $IrqNumber\r
+ LDR R0, =$IrqNumber\r
+ B .\r
+ MEND\r
+\r
+ MACRO\r
+ JUMPTO $Handler\r
+ LDR R0, =$Handler\r
+ BX R0\r
+ MEND\r
+\r
+ STAYHERE 0x0 ;* Reserved\r
+ STAYHERE 0x1 ;* Reserved \r
+ STAYHERE 0x2 ;* Reserved \r
+ JUMPTO HardFault_Handler ;* HardFault Veneer \r
+ STAYHERE 0x4 ;* Reserved \r
+ STAYHERE 0x5 ;* Reserved \r
+ STAYHERE 0x6 ;* Reserved \r
+ STAYHERE 0x7 ;* Reserved \r
+ STAYHERE 0x8 ;* Reserved \r
+ STAYHERE 0x9 ;* Reserved \r
+ STAYHERE 0xA ;* Reserved\r
+ JUMPTO SVC_Handler ;* SVC Veneer \r
+ STAYHERE 0xC ;* Reserved\r
+ STAYHERE 0xD ;* Reserved\r
+ JUMPTO PendSV_Handler ;* PendSV Veneer \r
+ JUMPTO SysTick_Handler ;* SysTick Veneer \r
+ JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
+ JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
+ JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
+ JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
+ JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
+ JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
+ JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
+ JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
+ STAYHERE 0x18 ;* Reserved\r
+ JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
+ JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
+ JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
+ JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
+ JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
+ JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
+ JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
+ JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
+ JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
+ JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
+ JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
+ JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
+ JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
+ JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
+ JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
+ JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
+ JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
+ JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
+ JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
+ JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
+ JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
+\r
+ ALIGN\r
+\r
+;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
+\r
+ END\r