Update RISK-V GCC port to ensure the first task starts with interrupts enabled -...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2745 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
index 436895158faef67124e929e33546850966fd4307..d6157c4d74965c14031951a90d570ea07e88b0d6 100644 (file)
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
@@ -172,7 +172,7 @@ handle_asynchronous:
                        li t4, -1\r
                        lw t2, 0(t1)                            /* Load the low word of ullNextTime into t2. */\r
                        lw t3, 4(t1)                            /* Load the high word of ullNextTime into t3. */\r
-                       sw t4, 0(t0)                            /* Low word no smaller than old value. */\r
+                       sw t4, 0(t0)                            /* Low word no smaller than old value to start with - will be overwritten below. */\r
                        sw t3, 4(t0)                            /* Store high word of ullNextTime into compare register.  No smaller than new value. */\r
                        sw t2, 0(t0)                            /* Store low word of ullNextTime into compare register. */\r
                        lw t0, uxTimerIncrementsForOneTick      /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */\r
@@ -223,11 +223,13 @@ test_if_environment_call:
        j processed_source\r
 \r
 is_exception:\r
-       ebreak\r
+       csrr t0, mcause                                         /* For viewing in the debugger only. */\r
+       csrr t1, mepc                                           /* For viewing in the debugger only */\r
+       csrr t2, mstatus\r
        j is_exception\r
 \r
 as_yet_unhandled:\r
-       ebreak\r
+       csrr t0, mcause                                         /* For viewing in the debugger only. */\r
        j as_yet_unhandled\r
 \r
 processed_source:\r
@@ -298,6 +300,7 @@ xPortStartFirstTask:
        portasmRESTORE_ADDITIONAL_REGISTERS     /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */\r
 \r
        load_x  t0, 29 * portWORD_SIZE( sp )    /* mstatus */\r
+       addi t0, t0, 0x08                                               /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */\r
        csrrw  x0, mstatus, t0                                  /* Interrupts enabled from here! */\r
 \r
        load_x  x5, 2 * portWORD_SIZE( sp )             /* t0 */\r
@@ -399,7 +402,7 @@ xPortStartFirstTask:
 pxPortInitialiseStack:\r
 \r
        csrr t0, mstatus                                        /* Obtain current mstatus value. */\r
-       addi t1, x0, 0x188                                      /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */\r
+       addi t1, x0, 0x188                                      /* Generate the value 0x1888, which are the MIE, MPIE and privilege bits to set in mstatus. */\r
        slli t1, t1, 4\r
        or t0, t0, t1                                           /* Set MPIE and MPP bits in mstatus value. */\r
 \r