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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2010 Spencer Oliver                                     *
   5  *   spen@spen-soft.co.uk                                                  *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  21  ***************************************************************************/
  22
  23         .text
  24         .arm
  25         .arch armv4
  26
  27         .section .init
  28
  29 /* algorithm register usage:
  30  * r0: source address (in RAM)
  31  * r1: target address (in Flash)
  32  * r2: count
  33  * r3: flash write command
  34  * r4: status byte (returned to host)
  35  * r5: busy test pattern
  36  * r6: error test pattern
  37  */
  38
  39 loop:
  40         ldrb    r4, [r0], #1
  41         strb    r3, [r1]
  42         strb    r4, [r1]
  43 busy:
  44         ldrb    r4, [r1]
  45         and             r7, r4, r5
  46         cmp             r7, r5
  47         bne             busy
  48         tst             r4, r6
  49         bne             done
  50         subs    r2, r2, #1
  51         beq             done
  52         add             r1, r1, #1
  53         b               loop
  54 done:
  55         b               done
  56
  57         .end