git.sur5r.net Git - openocd/blob - src/flash/nand/lpc3180.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *
   5  *   Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com>                *
   6  *   Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com>            *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include "lpc3180.h"
  29 #include <target/target.h>
  30
  31
  32 static int lpc3180_reset(struct nand_device *nand);
  33 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
  34 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
  35
  36
  37 #define ECC_OFFS   0x120
  38 #define SPARE_OFFS 0x140
  39 #define DATA_OFFS   0x200
  40
  41
  42 /* nand device lpc3180 <target#> <oscillator_frequency>
  43  */
  44 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
  45 {
  46         if (CMD_ARGC < 3)
  47         {
  48                 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
  49                 return ERROR_FLASH_BANK_INVALID;
  50         }
  51
  52         uint32_t osc_freq;
  53         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
  54
  55         struct lpc3180_nand_controller *lpc3180_info;
  56         lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
  57         nand->controller_priv = lpc3180_info;
  58
  59         lpc3180_info->osc_freq = osc_freq;
  60
  61         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  62         {
  63                 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
  64         }
  65         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  66         lpc3180_info->sw_write_protection = 0;
  67         lpc3180_info->sw_wp_lower_bound = 0x0;
  68         lpc3180_info->sw_wp_upper_bound = 0x0;
  69
  70         return ERROR_OK;
  71 }
  72
  73 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
  74 {
  75         int bypass = (pll_ctrl & 0x8000) >> 15;
  76         int direct = (pll_ctrl & 0x4000) >> 14;
  77         int feedback = (pll_ctrl & 0x2000) >> 13;
  78         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  79         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  80         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  81         int lock = (pll_ctrl & 0x1);
  82
  83         if (!lock)
  84                 LOG_WARNING("PLL is not locked");
  85
  86         if (!bypass && direct)  /* direct mode */
  87                 return (m * fclkin) / n;
  88
  89         if (bypass && !direct)  /* bypass mode */
  90                 return fclkin / (2 * p);
  91
  92         if (bypass & direct)    /* direct bypass mode */
  93                 return fclkin;
  94
  95         if (feedback)                   /* integer mode */
  96                 return m * (fclkin / n);
  97         else                                    /* non-integer mode */
  98                 return (m / (2 * p)) * (fclkin / n);
  99 }
 100
 101 static float lpc3180_cycle_time(struct nand_device *nand)
 102 {
 103         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 104         struct target *target = nand->target;
 105         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 106         int sysclk;
 107         int hclk;
 108         int hclk_pll;
 109         float cycle;
 110
 111         /* calculate timings */
 112
 113         /* determine current SYSCLK (13'MHz or main oscillator) */
 114         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 115
 116         if ((sysclk_ctrl & 1) == 0)
 117                 sysclk = lpc3180_info->osc_freq;
 118         else
 119                 sysclk = 13000;
 120
 121         /* determine selected HCLK source */
 122         target_read_u32(target, 0x40004044, &pwr_ctrl);
 123
 124         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 125         {
 126                 hclk = sysclk;
 127         }
 128         else
 129         {
 130                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 131                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 132
 133                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 134
 135                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 136                 {
 137                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 138                 }
 139                 else /* HCLK uses HCLK_PLL */
 140                 {
 141                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 142                 }
 143         }
 144
 145         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 146
 147         cycle = (1.0 / hclk) * 1000000.0;
 148
 149         return cycle;
 150 }
 151
 152 static int lpc3180_init(struct nand_device *nand)
 153 {
 154         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 155         struct target *target = nand->target;
 156         int bus_width = nand->bus_width ? : 8;
 157         int address_cycles = nand->address_cycles ? : 3;
 158         int page_size = nand->page_size ? : 512;
 159
 160         if (target->state != TARGET_HALTED)
 161         {
 162                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 163                 return ERROR_NAND_OPERATION_FAILED;
 164         }
 165
 166         /* sanitize arguments */
 167         if ((bus_width != 8) && (bus_width != 16))
 168         {
 169                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 170                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 171         }
 172
 173         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 174          * would support 16 bit, too, so we just warn about this for now
 175          */
 176         if (bus_width == 16)
 177         {
 178                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 179         }
 180
 181         /* inform calling code about selected bus width */
 182         nand->bus_width = bus_width;
 183
 184         if ((address_cycles != 3) && (address_cycles != 4))
 185         {
 186                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 187                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 188         }
 189
 190         if ((page_size != 512) && (page_size != 2048))
 191         {
 192                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 193                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 194         }
 195
 196         /* select MLC controller if none is currently selected */
 197         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 198         {
 199                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 200                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 201         }
 202
 203         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 204         {
 205                 uint32_t mlc_icr_value = 0x0;
 206                 float cycle;
 207                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 208
 209                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 210                 target_write_u32(target, 0x400040c8, 0x22);
 211
 212                 /* MLC_CEH = 0x0 (Force nCE assert) */
 213                 target_write_u32(target, 0x200b804c, 0x0);
 214
 215                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 216                 target_write_u32(target, 0x200b8044, 0xa25e);
 217
 218                 /* MLC_ICR = configuration */
 219                 if (lpc3180_info->sw_write_protection)
 220                         mlc_icr_value |= 0x8;
 221                 if (page_size == 2048)
 222                         mlc_icr_value |= 0x4;
 223                 if (address_cycles == 4)
 224                         mlc_icr_value |= 0x2;
 225                 if (bus_width == 16)
 226                         mlc_icr_value |= 0x1;
 227                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 228
 229                 /* calculate NAND controller timings */
 230                 cycle = lpc3180_cycle_time(nand);
 231
 232                 twp = ((40 / cycle) + 1);
 233                 twh = ((20 / cycle) + 1);
 234                 trp = ((30 / cycle) + 1);
 235                 treh = ((15 / cycle) + 1);
 236                 trhz = ((30 / cycle) + 1);
 237                 trbwb = ((100 / cycle) + 1);
 238                 tcea = ((45 / cycle) + 1);
 239
 240                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 241                 target_write_u32(target, 0x200b8044, 0xa25e);
 242
 243                 /* MLC_TIME_REG */
 244                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 245                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 246                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 247
 248                 lpc3180_reset(nand);
 249         }
 250         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 251         {
 252                 float cycle;
 253                 int r_setup, r_hold, r_width, r_rdy;
 254                 int w_setup, w_hold, w_width, w_rdy;
 255
 256                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 257                 target_write_u32(target, 0x400040c8, 0x05);
 258
 259                 /* after reset set other registers of SLC so reset calling is here at the begining*/
 260                 lpc3180_reset(nand);
 261
 262                 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
 263                 target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
 264
 265                 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
 266                 target_write_u32(target, 0x20020020, 0x03);
 267
 268                 /* DMA configuration */
 269                 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
 270                 target_write_u32(target, 0x400040e8, 0x01);
 271                 /* DMACConfig = DMA enabled*/
 272                 target_write_u32(target, 0x31000030, 0x01);
 273
 274
 275                 /* calculate NAND controller timings */
 276                 cycle = lpc3180_cycle_time(nand);
 277
 278                 r_setup = w_setup = 0;
 279                 r_hold = w_hold = 10 / cycle;
 280                 r_width = 30 / cycle;
 281                 w_width = 40 / cycle;
 282                 r_rdy = w_rdy = 100 / cycle;
 283
 284                 /* SLC_TAC: SLC timing arcs register */
 285                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 286                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 287                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 288
 289         }
 290
 291         return ERROR_OK;
 292 }
 293
 294 static int lpc3180_reset(struct nand_device *nand)
 295 {
 296         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 297         struct target *target = nand->target;
 298
 299         if (target->state != TARGET_HALTED)
 300         {
 301                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 302                 return ERROR_NAND_OPERATION_FAILED;
 303         }
 304
 305         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 306         {
 307                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 308                 return ERROR_NAND_OPERATION_FAILED;
 309         }
 310         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 311         {
 312                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 313                 target_write_u32(target, 0x200b8000, 0xff);
 314
 315                 if (!lpc3180_controller_ready(nand, 100))
 316                 {
 317                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 318                         return ERROR_NAND_OPERATION_TIMEOUT;
 319                 }
 320         }
 321         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 322         {
 323                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 324                 target_write_u32(target, 0x20020010, 0x6);
 325
 326                 if (!lpc3180_controller_ready(nand, 100))
 327                 {
 328                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 329                         return ERROR_NAND_OPERATION_TIMEOUT;
 330                 }
 331         }
 332
 333         return ERROR_OK;
 334 }
 335
 336 static int lpc3180_command(struct nand_device *nand, uint8_t command)
 337 {
 338         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 339         struct target *target = nand->target;
 340
 341         if (target->state != TARGET_HALTED)
 342         {
 343                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 344                 return ERROR_NAND_OPERATION_FAILED;
 345         }
 346
 347         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 348         {
 349                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 350                 return ERROR_NAND_OPERATION_FAILED;
 351         }
 352         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 353         {
 354                 /* MLC_CMD = command */
 355                 target_write_u32(target, 0x200b8000, command);
 356         }
 357         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 358         {
 359                 /* SLC_CMD = command */
 360                 target_write_u32(target, 0x20020008, command);
 361         }
 362
 363         return ERROR_OK;
 364 }
 365
 366 static int lpc3180_address(struct nand_device *nand, uint8_t address)
 367 {
 368         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 369         struct target *target = nand->target;
 370
 371         if (target->state != TARGET_HALTED)
 372         {
 373                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 374                 return ERROR_NAND_OPERATION_FAILED;
 375         }
 376
 377         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 378         {
 379                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 380                 return ERROR_NAND_OPERATION_FAILED;
 381         }
 382         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 383         {
 384                 /* MLC_ADDR = address */
 385                 target_write_u32(target, 0x200b8004, address);
 386         }
 387         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 388         {
 389                 /* SLC_ADDR = address */
 390                 target_write_u32(target, 0x20020004, address);
 391         }
 392
 393         return ERROR_OK;
 394 }
 395
 396 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
 397 {
 398         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 399         struct target *target = nand->target;
 400
 401         if (target->state != TARGET_HALTED)
 402         {
 403                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 404                 return ERROR_NAND_OPERATION_FAILED;
 405         }
 406
 407         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 408         {
 409                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 410                 return ERROR_NAND_OPERATION_FAILED;
 411         }
 412         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 413         {
 414                 /* MLC_DATA = data */
 415                 target_write_u32(target, 0x200b0000, data);
 416         }
 417         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 418         {
 419                 /* SLC_DATA = data */
 420                 target_write_u32(target, 0x20020000, data);
 421         }
 422
 423         return ERROR_OK;
 424 }
 425
 426 static int lpc3180_read_data(struct nand_device *nand, void *data)
 427 {
 428         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 429         struct target *target = nand->target;
 430
 431         if (target->state != TARGET_HALTED)
 432         {
 433                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 434                 return ERROR_NAND_OPERATION_FAILED;
 435         }
 436
 437         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 438         {
 439                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 440                 return ERROR_NAND_OPERATION_FAILED;
 441         }
 442         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 443         {
 444                 /* data = MLC_DATA, use sized access */
 445                 if (nand->bus_width == 8)
 446                 {
 447                         uint8_t *data8 = data;
 448                         target_read_u8(target, 0x200b0000, data8);
 449                 }
 450                 else if (nand->bus_width == 16)
 451                 {
 452                         uint16_t *data16 = data;
 453                         target_read_u16(target, 0x200b0000, data16);
 454                 }
 455                 else
 456                 {
 457                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 458                         return ERROR_NAND_OPERATION_FAILED;
 459                 }
 460         }
 461         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 462         {
 463                 uint32_t data32;
 464
 465                 /* data = SLC_DATA, must use 32-bit access */
 466                 target_read_u32(target, 0x20020000, &data32);
 467
 468                 if (nand->bus_width == 8)
 469                 {
 470                         uint8_t *data8 = data;
 471                         *data8 = data32 & 0xff;
 472                 }
 473                 else if (nand->bus_width == 16)
 474                 {
 475                         uint16_t *data16 = data;
 476                         *data16 = data32 & 0xffff;
 477                 }
 478                 else
 479                 {
 480                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 481                         return ERROR_NAND_OPERATION_FAILED;
 482                 }
 483         }
 484
 485         return ERROR_OK;
 486 }
 487
 488 static int lpc3180_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 489 {
 490         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 491         struct target *target = nand->target;
 492         int retval;
 493         uint8_t status;
 494         uint8_t *page_buffer;
 495
 496         if (target->state != TARGET_HALTED)
 497         {
 498                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 499                 return ERROR_NAND_OPERATION_FAILED;
 500         }
 501
 502         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 503         {
 504                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 505                 return ERROR_NAND_OPERATION_FAILED;
 506         }
 507         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 508         {
 509                 uint8_t *oob_buffer;
 510                 int quarter, num_quarters;
 511
 512                 if (!data && oob)
 513                 {
 514                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 515                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 516                 }
 517
 518                 if (oob && (oob_size > 24))
 519                 {
 520                         LOG_ERROR("LPC3180 MLC controller can't write more "
 521                                 "than 6 bytes for each quarter's OOB data");
 522                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 523                 }
 524
 525                 if (data_size > (uint32_t)nand->page_size)
 526                 {
 527                         LOG_ERROR("data size exceeds page size");
 528                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 529                 }
 530
 531                 /* MLC_CMD = sequential input */
 532                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 533
 534                 page_buffer = malloc(512);
 535                 oob_buffer = malloc(6);
 536
 537                 if (nand->page_size == 512)
 538                 {
 539                         /* MLC_ADDR = 0x0 (one column cycle) */
 540                         target_write_u32(target, 0x200b8004, 0x0);
 541
 542                         /* MLC_ADDR = row */
 543                         target_write_u32(target, 0x200b8004, page & 0xff);
 544                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 545
 546                         if (nand->address_cycles == 4)
 547                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 548                 }
 549                 else
 550                 {
 551                         /* MLC_ADDR = 0x0 (two column cycles) */
 552                         target_write_u32(target, 0x200b8004, 0x0);
 553                         target_write_u32(target, 0x200b8004, 0x0);
 554
 555                         /* MLC_ADDR = row */
 556                         target_write_u32(target, 0x200b8004, page & 0xff);
 557                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 558                 }
 559
 560                 /* when using the MLC controller, we have to treat a large page device
 561                  * as being made out of four quarters, each the size of a small page device
 562                  */
 563                 num_quarters = (nand->page_size == 2048) ? 4 : 1;
 564
 565                 for (quarter = 0; quarter < num_quarters; quarter++)
 566                 {
 567                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 568                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 569
 570                         memset(page_buffer, 0xff, 512);
 571                         if (data)
 572                         {
 573                                 memcpy(page_buffer, data, thisrun_data_size);
 574                                 data_size -= thisrun_data_size;
 575                                 data += thisrun_data_size;
 576                         }
 577
 578                         memset(oob_buffer, 0xff, 6);
 579                         if (oob)
 580                         {
 581                                 memcpy(oob_buffer, oob, thisrun_oob_size);
 582                                 oob_size -= thisrun_oob_size;
 583                                 oob += thisrun_oob_size;
 584                         }
 585
 586                         /* write MLC_ECC_ENC_REG to start encode cycle */
 587                         target_write_u32(target, 0x200b8008, 0x0);
 588
 589                         target_write_memory(target, 0x200a8000,
 590                                         4, 128, page_buffer);
 591                         target_write_memory(target, 0x200a8000,
 592                                         1, 6, oob_buffer);
 593
 594                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 595                         target_write_u32(target, 0x200b8010, 0x0);
 596
 597                         if (!lpc3180_controller_ready(nand, 1000))
 598                         {
 599                                 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
 600                                 return ERROR_NAND_OPERATION_FAILED;
 601                         }
 602                 }
 603
 604                 /* MLC_CMD = auto program command */
 605                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 606
 607                 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
 608                 {
 609                         LOG_ERROR("couldn't read status");
 610                         return ERROR_NAND_OPERATION_FAILED;
 611                 }
 612
 613                 if (status & NAND_STATUS_FAIL)
 614                 {
 615                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 616                         return ERROR_NAND_OPERATION_FAILED;
 617                 }
 618
 619                 free(page_buffer);
 620                 free(oob_buffer);
 621         }
 622         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 623         {
 624
 625                /**********************************************************************
 626                *     Write both SLC NAND flash page main area and spare area.
 627                *     Small page -
 628                *      ------------------------------------------
 629                *     |    512 bytes main   |   16 bytes spare   |
 630                *      ------------------------------------------
 631                *     Large page -
 632                *      ------------------------------------------
 633                *     |   2048 bytes main   |   64 bytes spare   |
 634                *      ------------------------------------------
 635                *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 636                *     data is written to the 3rd word of the spare area. The ECC
 637                *     generated for the 2nd 256-byte data is written to the 4th word
 638                *     of the spare area. The ECC generated for the 3rd 256-byte data is
 639                *     written to the 7th word of the spare area. The ECC generated
 640                *     for the 4th 256-byte data is written to the 8th word of the
 641                *     spare area and so on.
 642                *
 643                **********************************************************************/
 644
 645                int i=0,target_mem_base;
 646                uint8_t *ecc_flash_buffer;
 647                struct working_area *pworking_area;
 648
 649
 650                 if(lpc3180_info->is_bulk){
 651
 652                     if (!data && oob){
 653                         /*if oob only mode is active original method is used as SLC controller hangs during DMA interworking. Anyway the code supports the oob only mode below. */
 654                 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 655         }
 656                     retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
 657                     if (ERROR_OK != retval)
 658                         return retval;
 659
 660                     /* allocate a working area */
 661                     if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
 662                         LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
 663                         return ERROR_FLASH_OPERATION_FAILED;
 664                     }
 665                     if (target->working_area_phys%4){
 666                         LOG_ERROR("Reserve the physical target working area at word boundary");
 667                         return ERROR_FLASH_OPERATION_FAILED;
 668                     }
 669                     if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
 670                     {
 671                         LOG_ERROR("no working area specified, can't read LPC internal flash");
 672                         return ERROR_FLASH_OPERATION_FAILED;
 673                     }
 674                     target_mem_base = target->working_area_phys;
 675
 676
 677                     if (nand->page_size == 2048)
 678                     {
 679                         page_buffer = malloc(2048);
 680                     }
 681                     else
 682                     {
 683                         page_buffer = malloc(512);
 684                     }
 685
 686                     ecc_flash_buffer = malloc(64);
 687
 688                     /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA write to SLC, WIDTH = bus_width) */
 689                     target_write_u32(target, 0x20020014, 0x3c);
 690
 691                     if( data && !oob){
 692                         /* set DMA LLI-s in target memory and in DMA*/
 693                         for(i=0;i<nand->page_size/0x100;i++){
 694
 695                             int tmp;
 696                             /* -------LLI for 256 byte block---------*/
 697                             /* DMACC0SrcAddr = SRAM */
 698                             target_write_u32(target,target_mem_base+0+i*32,target_mem_base+DATA_OFFS+i*256 );
 699                             if(i==0) target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
 700                             /* DMACCxDestAddr = SLC_DMA_DATA */
 701                             target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
 702                             if(i==0)  target_write_u32(target,0x31000104,0x20020038 );
 703                             /* DMACCxLLI = next element */
 704                             tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
 705                             target_write_u32(target,target_mem_base+8+i*32, tmp );
 706                             if(i==0) target_write_u32(target,0x31000108, tmp );
 707                             /* DMACCxControl =  TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 708                             Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 709                             Destination increment = 0, Terminal count interrupt enable bit = 0*/
 710                             target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 711                             if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 712
 713                             /* -------LLI for 3 byte ECC---------*/
 714                             /* DMACC0SrcAddr = SLC_ECC*/
 715                             target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
 716                             /* DMACCxDestAddr = SRAM */
 717                             target_write_u32(target,target_mem_base+20+i*32,target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4 );
 718                             /* DMACCxLLI = next element */
 719                                 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
 720                             target_write_u32(target,target_mem_base+24+i*32, tmp );
 721                             /* DMACCxControl =  TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
 722                             Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
 723                             Destination increment = 1, Terminal count interrupt enable bit = 0*/
 724                             target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
 725                         }
 726                     }
 727                     else if (data && oob){
 728                         /* -------LLI for 512 or 2048 bytes page---------*/
 729                         /* DMACC0SrcAddr = SRAM */
 730                         target_write_u32(target,target_mem_base,target_mem_base+DATA_OFFS );
 731                         target_write_u32(target,0x31000100,target_mem_base+DATA_OFFS );
 732                         /* DMACCxDestAddr = SLC_DMA_DATA */
 733                         target_write_u32(target,target_mem_base+4,0x20020038 );
 734                         target_write_u32(target,0x31000104,0x20020038 );
 735                         /* DMACCxLLI = next element */
 736                         target_write_u32(target,target_mem_base+8, (target_mem_base+32)&0xfffffffc );
 737                         target_write_u32(target,0x31000108, (target_mem_base+32)&0xfffffffc );
 738                         /* DMACCxControl =  TransferSize =512 or 128, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 739                         Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 740                         Destination increment = 0, Terminal count interrupt enable bit = 0*/
 741                         target_write_u32(target,target_mem_base+12,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 742                         target_write_u32(target,0x3100010c,(nand->page_size==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 743                         i = 1;
 744                     }
 745                     else if (!data && oob){
 746                         i = 0;
 747                     }
 748
 749                     /* -------LLI for spare area---------*/
 750                     /* DMACC0SrcAddr = SRAM*/
 751                     target_write_u32(target,target_mem_base+0+i*32,target_mem_base+SPARE_OFFS );
 752                     if(i==0) target_write_u32(target,0x31000100,target_mem_base+SPARE_OFFS );
 753                     /* DMACCxDestAddr = SLC_DMA_DATA */
 754                     target_write_u32(target,target_mem_base+4+i*32,0x20020038 );
 755                     if(i==0) target_write_u32(target,0x31000104,0x20020038 );
 756                     /* DMACCxLLI = next element = NULL */
 757                     target_write_u32(target,target_mem_base+8+i*32, 0 );
 758                     if(i==0) target_write_u32(target,0x31000108,0 );
 759                     /* DMACCxControl =  TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
 760                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
 761                     Destination increment = 0, Terminal count interrupt enable bit = 0*/
 762                     target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
 763                     if(i==0) target_write_u32(target,0x3100010c,(nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31 );
 764
 765
 766
 767                     memset(ecc_flash_buffer, 0xff, 64);
 768                     if( oob ){
 769                         memcpy(ecc_flash_buffer,oob, oob_size);
 770                     }
 771                     target_write_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
 772
 773                     if (data){
 774                         memset(page_buffer, 0xff, nand->page_size == 2048?2048:512);
 775                         memcpy(page_buffer,data, data_size);
 776                         target_write_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
 777                     }
 778
 779                     free(page_buffer);
 780                     free(ecc_flash_buffer);
 781
 782                     /* Enable DMA after channel set up !
 783                         LLI only works when DMA is the flow controller!
 784                     */
 785                     /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
 786                     target_write_u32(target,0x31000110,   1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
 787
 788
 789
 790                      /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
 791                      target_write_u32(target, 0x20020010, 0x3);
 792
 793                     /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
 794                      target_write_u32(target, 0x20020028, 2);
 795
 796                     /* SLC_TC */
 797                     if (!data && oob)
 798                        target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x10:0x04));
 799                     else
 800                        target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x840:0x210));
 801
 802                     nand_write_finish(nand);
 803
 804
 805                     if (!lpc3180_tc_ready(nand, 1000))
 806                     {
 807                         LOG_ERROR("timeout while waiting for completion of DMA");
 808                         return ERROR_NAND_OPERATION_FAILED;
 809                     }
 810
 811                 target_free_working_area(target,pworking_area);
 812
 813                 LOG_INFO("Page =  0x%" PRIx32 " was written.",page);
 814
 815                 }
 816                 else
 817                     return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 818         }
 819
 820
 821         return ERROR_OK;
 822 }
 823
 824 static int lpc3180_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 825 {
 826         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
 827         struct target *target = nand->target;
 828         uint8_t *page_buffer;
 829
 830         if (target->state != TARGET_HALTED)
 831         {
 832                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 833                 return ERROR_NAND_OPERATION_FAILED;
 834         }
 835
 836         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 837         {
 838                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 839                 return ERROR_NAND_OPERATION_FAILED;
 840         }
 841         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 842         {
 843                 uint8_t *oob_buffer;
 844                 uint32_t page_bytes_done = 0;
 845                 uint32_t oob_bytes_done = 0;
 846                 uint32_t mlc_isr;
 847
 848 #if 0
 849                 if (oob && (oob_size > 6))
 850                 {
 851                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 852                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 853                 }
 854 #endif
 855
 856                 if (data_size > (uint32_t)nand->page_size)
 857                 {
 858                         LOG_ERROR("data size exceeds page size");
 859                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 860                 }
 861
 862                 if (nand->page_size == 2048)
 863                 {
 864                         page_buffer = malloc(2048);
 865                         oob_buffer = malloc(64);
 866                 }
 867                 else
 868                 {
 869                         page_buffer = malloc(512);
 870                         oob_buffer = malloc(16);
 871                 }
 872
 873                 if (!data && oob)
 874                 {
 875                         /* MLC_CMD = Read OOB
 876                          * we can use the READOOB command on both small and large page devices,
 877                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 878                          * positioning of the serial buffer read pointer
 879                          */
 880                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 881                 }
 882                 else
 883                 {
 884                         /* MLC_CMD = Read0 */
 885                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 886                 }
 887
 888                 if (nand->page_size == 512)
 889                 {
 890                         /* small page device */
 891                         /* MLC_ADDR = 0x0 (one column cycle) */
 892                         target_write_u32(target, 0x200b8004, 0x0);
 893
 894                         /* MLC_ADDR = row */
 895                         target_write_u32(target, 0x200b8004, page & 0xff);
 896                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 897
 898                         if (nand->address_cycles == 4)
 899                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 900                 }
 901                 else
 902                 {
 903                         /* large page device */
 904                         /* MLC_ADDR = 0x0 (two column cycles) */
 905                         target_write_u32(target, 0x200b8004, 0x0);
 906                         target_write_u32(target, 0x200b8004, 0x0);
 907
 908                         /* MLC_ADDR = row */
 909                         target_write_u32(target, 0x200b8004, page & 0xff);
 910                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 911
 912                         /* MLC_CMD = Read Start */
 913                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 914                 }
 915
 916                 while (page_bytes_done < (uint32_t)nand->page_size)
 917                 {
 918                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 919                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 920
 921                         if (!lpc3180_controller_ready(nand, 1000))
 922                         {
 923                                 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
 924                                 return ERROR_NAND_OPERATION_FAILED;
 925                         }
 926
 927                         target_read_u32(target, 0x200b8048, &mlc_isr);
 928
 929                         if (mlc_isr & 0x8)
 930                         {
 931                                 if (mlc_isr & 0x40)
 932                                 {
 933                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
 934                                         return ERROR_NAND_OPERATION_FAILED;
 935                                 }
 936
 937                                 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
 938                         }
 939
 940                         if (data)
 941                         {
 942                                 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
 943                         }
 944
 945                         if (oob)
 946                         {
 947                                 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
 948                         }
 949
 950                         page_bytes_done += 512;
 951                         oob_bytes_done += 16;
 952                 }
 953
 954                 if (data)
 955                         memcpy(data, page_buffer, data_size);
 956
 957                 if (oob)
 958                         memcpy(oob, oob_buffer, oob_size);
 959
 960                 free(page_buffer);
 961                 free(oob_buffer);
 962         }
 963         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 964         {
 965
 966            /**********************************************************************
 967            *     Read both SLC NAND flash page main area and spare area.
 968            *     Small page -
 969            *      ------------------------------------------
 970            *     |    512 bytes main   |   16 bytes spare   |
 971            *      ------------------------------------------
 972            *     Large page -
 973            *      ------------------------------------------
 974            *     |   2048 bytes main   |   64 bytes spare   |
 975            *      ------------------------------------------
 976            *     If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
 977            *     data is compared with the 3rd word of the spare area. The ECC
 978            *     generated for the 2nd 256-byte data is compared with the 4th word
 979            *     of the spare area. The ECC generated for the 3rd 256-byte data is
 980            *     compared with the 7th word of the spare area. The ECC generated
 981            *     for the 4th 256-byte data is compared with the 8th word of the
 982            *     spare area and so on.
 983            *
 984            **********************************************************************/
 985
 986            int retval,i,target_mem_base;
 987            uint8_t *ecc_hw_buffer;
 988            uint8_t *ecc_flash_buffer;
 989            struct working_area *pworking_area;
 990
 991            if(lpc3180_info->is_bulk){
 992
 993                 /* read always the data and also oob areas*/
 994
 995                 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
 996                 if (ERROR_OK != retval)
 997                         return retval;
 998
 999                 /* allocate a working area */
1000                 if (target->working_area_size < (uint32_t) nand->page_size + 0x200){
1001                     LOG_ERROR("Reserve at least 0x%x physical target working area",nand->page_size + 0x200);
1002                     return ERROR_FLASH_OPERATION_FAILED;
1003                 }
1004                 if (target->working_area_phys%4){
1005                     LOG_ERROR("Reserve the physical target working area at word boundary");
1006                     return ERROR_FLASH_OPERATION_FAILED;
1007                 }
1008                 if (target_alloc_working_area(target, target->working_area_size, &pworking_area) != ERROR_OK)
1009                 {
1010                     LOG_ERROR("no working area specified, can't read LPC internal flash");
1011                     return ERROR_FLASH_OPERATION_FAILED;
1012                 }
1013                 target_mem_base = target->working_area_phys;
1014
1015                 if (nand->page_size == 2048)
1016                 {
1017                     page_buffer = malloc(2048);
1018                 }
1019                 else
1020                 {
1021                     page_buffer = malloc(512);
1022                 }
1023
1024                 ecc_hw_buffer = malloc(32);
1025                 ecc_flash_buffer = malloc(64);
1026
1027                 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
1028                 target_write_u32(target, 0x20020014, 0x3e);
1029
1030                 /* set DMA LLI-s in target memory and in DMA*/
1031                 for(i=0;i<nand->page_size/0x100;i++){
1032                     int tmp;
1033                     /* -------LLI for 256 byte block---------*/
1034                     /* DMACC0SrcAddr = SLC_DMA_DATA*/
1035                     target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1036                     if(i==0) target_write_u32(target,0x31000100,0x20020038 );
1037                     /* DMACCxDestAddr = SRAM */
1038                     target_write_u32(target,target_mem_base+4+i*32,target_mem_base+DATA_OFFS+i*256 );
1039                     if(i==0)  target_write_u32(target,0x31000104,target_mem_base+DATA_OFFS );
1040                     /* DMACCxLLI = next element */
1041                     tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1042                     target_write_u32(target,target_mem_base+8+i*32, tmp );
1043                     if(i==0) target_write_u32(target,0x31000108, tmp );
1044                     /* DMACCxControl =  TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1045                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1046                     Destination increment = 1, Terminal count interrupt enable bit = 0*/
1047                     target_write_u32(target,target_mem_base+12+i*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1048                     if(i==0) target_write_u32(target,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1049
1050                     /* -------LLI for 3 byte ECC---------*/
1051                     /* DMACC0SrcAddr = SLC_ECC*/
1052                     target_write_u32(target,target_mem_base+16+i*32,0x20020034 );
1053                     /* DMACCxDestAddr = SRAM */
1054                     target_write_u32(target,target_mem_base+20+i*32,target_mem_base+ECC_OFFS+i*4 );
1055                     /* DMACCxLLI = next element */
1056                     tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1057                     target_write_u32(target,target_mem_base+24+i*32, tmp );
1058                     /* DMACCxControl =  TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
1059                     Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1060                     Destination increment = 1, Terminal count interrupt enable bit = 0*/
1061                     target_write_u32(target,target_mem_base+28+i*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1062
1063
1064                 }
1065
1066                 /* -------LLI for spare area---------*/
1067                 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1068                 target_write_u32(target,target_mem_base+0+i*32,0x20020038 );
1069                 /* DMACCxDestAddr = SRAM */
1070                 target_write_u32(target,target_mem_base+4+i*32,target_mem_base+SPARE_OFFS );
1071                 /* DMACCxLLI = next element = NULL */
1072                 target_write_u32(target,target_mem_base+8+i*32, 0 );
1073                 /* DMACCxControl =  TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1074                 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1075                 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1076                 target_write_u32(target,target_mem_base+12+i*32, (nand->page_size==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1077
1078                 /* Enable DMA after channel set up !
1079                     LLI only works when DMA is the flow controller!
1080                 */
1081                 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1082                 target_write_u32(target,0x31000110,   1 | 1<<1 | 1<<6 |  2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1083
1084
1085                  /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1086                 target_write_u32(target, 0x20020010, 0x3);
1087
1088                 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1089                 target_write_u32(target, 0x20020028, 2);
1090
1091                 /* SLC_TC */
1092                 target_write_u32(target, 0x20020030,  (nand->page_size==2048?0x840:0x210));
1093
1094                 if (!lpc3180_tc_ready(nand, 1000))
1095                 {
1096                     LOG_ERROR("timeout while waiting for completion of DMA");
1097                     free(page_buffer);
1098                     free(ecc_hw_buffer);
1099                     free(ecc_flash_buffer);
1100                     target_free_working_area(target,pworking_area);
1101                     return ERROR_NAND_OPERATION_FAILED;
1102                 }
1103
1104                 if (data){
1105                     target_read_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
1106                     memcpy(data, page_buffer, data_size);
1107
1108                     LOG_INFO("Page =  0x%" PRIx32 " was read.",page);
1109
1110                     /* check hw generated ECC for each 256 bytes block with the saved ECC in flash spare area*/
1111                     int idx = nand->page_size/0x200 ;
1112                     target_read_memory(target, target_mem_base+SPARE_OFFS, 4, 16, ecc_flash_buffer);
1113                     target_read_memory(target, target_mem_base+ECC_OFFS, 4, 8, ecc_hw_buffer);
1114                     for(i=0;i<idx;i++){
1115                         if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)) )
1116                             LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+1,page);
1117                         if( (0x00ffffff&*(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) != (0x00ffffff&*(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)) )
1118                             LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+2,page);
1119                     }
1120                 }
1121
1122                 if (oob)
1123                     memcpy(oob, ecc_flash_buffer, oob_size);
1124
1125                 free(page_buffer);
1126                 free(ecc_hw_buffer);
1127                 free(ecc_flash_buffer);
1128
1129                 target_free_working_area(target,pworking_area);
1130
1131             }
1132             else
1133                 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1134         }
1135
1136         return ERROR_OK;
1137 }
1138
1139 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1140 {
1141         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1142         struct target *target = nand->target;
1143
1144         if (target->state != TARGET_HALTED)
1145         {
1146                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1147                 return ERROR_NAND_OPERATION_FAILED;
1148         }
1149
1150         LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1151
1152         do
1153         {
1154                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1155                 {
1156                         uint8_t status;
1157
1158                         /* Read MLC_ISR, wait for controller to become ready */
1159                         target_read_u8(target, 0x200b8048, &status);
1160
1161                         if (status & 2) {
1162                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1163                                                 timeout);
1164                                 return 1;
1165                         }
1166                 }
1167                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1168                 {
1169                         uint32_t status;
1170
1171                         /* Read SLC_STAT and check READY bit */
1172                         target_read_u32(target, 0x20020018, &status);
1173
1174                         if (status & 1) {
1175                                 LOG_DEBUG("lpc3180_controller_ready count=%d",
1176                                                 timeout);
1177                                 return 1;
1178                         }
1179                 }
1180
1181                 alive_sleep(1);
1182         } while (timeout-- > 0);
1183
1184         return 0;
1185 }
1186
1187 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1188 {
1189         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1190         struct target *target = nand->target;
1191
1192         if (target->state != TARGET_HALTED)
1193         {
1194                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1195                 return ERROR_NAND_OPERATION_FAILED;
1196         }
1197
1198         LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1199
1200         do
1201         {
1202                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1203                 {
1204                         uint8_t status = 0x0;
1205
1206                         /* Read MLC_ISR, wait for NAND flash device to become ready */
1207                         target_read_u8(target, 0x200b8048, &status);
1208
1209                         if (status & 1) {
1210                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1211                                                 timeout);
1212                                 return 1;
1213                         }
1214                 }
1215                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1216                 {
1217                         uint32_t status = 0x0;
1218
1219                         /* Read SLC_STAT and check READY bit */
1220                         target_read_u32(target, 0x20020018, &status);
1221
1222                         if (status & 1) {
1223                                 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1224                                                 timeout);
1225                                 return 1;
1226                         }
1227                 }
1228
1229                 alive_sleep(1);
1230         } while (timeout-- > 0);
1231
1232         return 0;
1233 }
1234
1235 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1236 {
1237         struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1238         struct target *target = nand->target;
1239
1240         if (target->state != TARGET_HALTED)
1241         {
1242                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1243                 return ERROR_NAND_OPERATION_FAILED;
1244         }
1245
1246       LOG_DEBUG("lpc3180_tc_ready count start=%d",
1247                           timeout);
1248
1249         do
1250         {
1251                 if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
1252                 {
1253                    uint32_t status = 0x0;
1254                         /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1255                         target_read_u32(target, 0x2002001c, &status);
1256
1257                         if (status & 2){
1258                         LOG_DEBUG("lpc3180_tc_ready count=%d",
1259                                             timeout);
1260                         return 1;
1261                     }
1262                 }
1263
1264                 alive_sleep(1);
1265         } while (timeout-- > 0);
1266
1267         return 0;
1268 }
1269
1270
1271 COMMAND_HANDLER(handle_lpc3180_select_command)
1272 {
1273         struct lpc3180_nand_controller *lpc3180_info = NULL;
1274         char *selected[] =
1275         {
1276                 "no", "mlc", "slc"
1277         };
1278
1279         if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1280         {
1281                 return ERROR_COMMAND_SYNTAX_ERROR;
1282         }
1283
1284         unsigned num;
1285         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1286         struct nand_device *nand = get_nand_device_by_num(num);
1287         if (!nand)
1288         {
1289                 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1290                 return ERROR_OK;
1291         }
1292
1293         lpc3180_info = nand->controller_priv;
1294
1295         if (CMD_ARGC >= 2)
1296         {
1297                 if (strcmp(CMD_ARGV[1], "mlc") == 0)
1298                 {
1299                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
1300                 }
1301                 else if (strcmp(CMD_ARGV[1], "slc") == 0)
1302                 {
1303                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
1304                    if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0){
1305                         lpc3180_info->is_bulk = 1;
1306                    }
1307                    else{
1308                         lpc3180_info->is_bulk = 0;
1309                    }
1310                 }
1311                 else
1312                 {
1313                         return ERROR_COMMAND_SYNTAX_ERROR;
1314                 }
1315         }
1316
1317       if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1318         command_print(CMD_CTX, "%s controller selected", selected[lpc3180_info->selected_controller]);
1319       else{
1320             command_print(CMD_CTX, lpc3180_info->is_bulk?"%s controller selected bulk mode is available":"%s controller selected bulk mode is not available", selected[lpc3180_info->selected_controller]);
1321       }
1322
1323
1324         return ERROR_OK;
1325 }
1326
1327 static const struct command_registration lpc3180_exec_command_handlers[] = {
1328         {
1329                 .name = "select",
1330                 .handler = handle_lpc3180_select_command,
1331                 .mode = COMMAND_EXEC,
1332                 .help = "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1333                 .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1334         },
1335         COMMAND_REGISTRATION_DONE
1336 };
1337 static const struct command_registration lpc3180_command_handler[] = {
1338         {
1339                 .name = "lpc3180",
1340                 .mode = COMMAND_ANY,
1341                 .help = "LPC3180 NAND flash controller commands",
1342                 .chain = lpc3180_exec_command_handlers,
1343         },
1344         COMMAND_REGISTRATION_DONE
1345 };
1346
1347 struct nand_flash_controller lpc3180_nand_controller = {
1348         .name = "lpc3180",
1349         .commands = lpc3180_command_handler,
1350         .nand_device_command = lpc3180_nand_device_command,
1351         .init = lpc3180_init,
1352         .reset = lpc3180_reset,
1353         .command = lpc3180_command,
1354         .address = lpc3180_address,
1355         .write_data = lpc3180_write_data,
1356         .read_data = lpc3180_read_data,
1357         .write_page = lpc3180_write_page,
1358         .read_page = lpc3180_read_page,
1359         .nand_ready = lpc3180_nand_ready,
1360 };