git.sur5r.net Git - openocd/blob - src/flash/nor/kinetis.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Mathias Kuester                                 *
   3  *   kesmtp@freenet.de                                                     *
   4  *                                                                         *
   5  *   Copyright (C) 2011 sleep(5) ltd                                       *
   6  *   tomas@sleepfive.com                                                   *
   7  *                                                                         *
   8  *   Copyright (C) 2012 by Christopher D. Kilgour                          *
   9  *   techie at whiterocker.com                                             *
  10  *                                                                         *
  11  *   Copyright (C) 2013 Nemui Trinomius                                    *
  12  *   nemuisan_kawausogasuki@live.jp                                        *
  13  *                                                                         *
  14  *   Copyright (C) 2015 Tomas Vanek                                        *
  15  *   vanekt@fbl.cz                                                         *
  16  *                                                                         *
  17  *   This program is free software; you can redistribute it and/or modify  *
  18  *   it under the terms of the GNU General Public License as published by  *
  19  *   the Free Software Foundation; either version 2 of the License, or     *
  20  *   (at your option) any later version.                                   *
  21  *                                                                         *
  22  *   This program is distributed in the hope that it will be useful,       *
  23  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  24  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  25  *   GNU General Public License for more details.                          *
  26  *                                                                         *
  27  *   You should have received a copy of the GNU General Public License     *
  28  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  29  ***************************************************************************/
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include "jtag/interface.h"
  36 #include "imp.h"
  37 #include <helper/binarybuffer.h>
  38 #include <helper/time_support.h>
  39 #include <target/target_type.h>
  40 #include <target/algorithm.h>
  41 #include <target/armv7m.h>
  42 #include <target/cortex_m.h>
  43
  44 /*
  45  * Implementation Notes
  46  *
  47  * The persistent memories in the Kinetis chip families K10 through
  48  * K70 are all manipulated with the Flash Memory Module.  Some
  49  * variants call this module the FTFE, others call it the FTFL.  To
  50  * indicate that both are considered here, we use FTFX.
  51  *
  52  * Within the module, according to the chip variant, the persistent
  53  * memory is divided into what Freescale terms Program Flash, FlexNVM,
  54  * and FlexRAM.  All chip variants have Program Flash.  Some chip
  55  * variants also have FlexNVM and FlexRAM, which always appear
  56  * together.
  57  *
  58  * A given Kinetis chip may have 1, 2 or 4 blocks of flash.  Here we map
  59  * each block to a separate bank.  Each block size varies by chip and
  60  * may be determined by the read-only SIM_FCFG1 register.  The sector
  61  * size within each bank/block varies by chip, and may be 1, 2 or 4k.
  62  * The sector size may be different for flash and FlexNVM.
  63  *
  64  * The first half of the flash (1 or 2 blocks) is always Program Flash
  65  * and always starts at address 0x00000000.  The "PFLSH" flag, bit 23
  66  * of the read-only SIM_FCFG2 register, determines whether the second
  67  * half of the flash is also Program Flash or FlexNVM+FlexRAM.  When
  68  * PFLSH is set, the second from the first half.  When PFLSH is clear,
  69  * the second half of flash is FlexNVM and always starts at address
  70  * 0x10000000.  FlexRAM, which is also present when PFLSH is clear,
  71  * always starts at address 0x14000000.
  72  *
  73  * The Flash Memory Module provides a register set where flash
  74  * commands are loaded to perform flash operations like erase and
  75  * program.  Different commands are available depending on whether
  76  * Program Flash or FlexNVM/FlexRAM is being manipulated.  Although
  77  * the commands used are quite consistent between flash blocks, the
  78  * parameters they accept differ according to the flash sector size.
  79  *
  80  */
  81
  82 /* Addressess */
  83 #define FCF_ADDRESS     0x00000400
  84 #define FCF_FPROT       0x8
  85 #define FCF_FSEC        0xc
  86 #define FCF_FOPT        0xd
  87 #define FCF_FDPROT      0xf
  88 #define FCF_SIZE        0x10
  89
  90 #define FLEXRAM         0x14000000
  91
  92 #define MSCM_OCMDR0     0x40001400
  93 #define FMC_PFB01CR     0x4001f004
  94 #define FTFx_FSTAT      0x40020000
  95 #define FTFx_FCNFG      0x40020001
  96 #define FTFx_FCCOB3     0x40020004
  97 #define FTFx_FPROT3     0x40020010
  98 #define FTFx_FDPROT     0x40020017
  99 #define SIM_BASE        0x40047000
 100 #define SIM_BASE_KL28   0x40074000
 101 #define SIM_COPC        0x40048100
 102         /* SIM_COPC does not exist on devices with changed SIM_BASE */
 103 #define WDOG_BASE       0x40052000
 104 #define WDOG32_KE1X     0x40052000
 105 #define WDOG32_KL28     0x40076000
 106 #define SMC_PMCTRL      0x4007E001
 107 #define SMC_PMSTAT      0x4007E003
 108 #define SMC32_PMCTRL    0x4007E00C
 109 #define SMC32_PMSTAT    0x4007E014
 110 #define MCM_PLACR       0xF000300C
 111
 112 /* Offsets */
 113 #define SIM_SOPT1_OFFSET    0x0000
 114 #define SIM_SDID_OFFSET     0x1024
 115 #define SIM_FCFG1_OFFSET    0x104c
 116 #define SIM_FCFG2_OFFSET    0x1050
 117
 118 #define WDOG_STCTRLH_OFFSET      0
 119 #define WDOG32_CS_OFFSET         0
 120
 121 /* Values */
 122 #define PM_STAT_RUN             0x01
 123 #define PM_STAT_VLPR            0x04
 124 #define PM_CTRL_RUNM_RUN        0x00
 125
 126 /* Commands */
 127 #define FTFx_CMD_BLOCKSTAT  0x00
 128 #define FTFx_CMD_SECTSTAT   0x01
 129 #define FTFx_CMD_LWORDPROG  0x06
 130 #define FTFx_CMD_SECTERASE  0x09
 131 #define FTFx_CMD_SECTWRITE  0x0b
 132 #define FTFx_CMD_MASSERASE  0x44
 133 #define FTFx_CMD_PGMPART    0x80
 134 #define FTFx_CMD_SETFLEXRAM 0x81
 135
 136 /* The older Kinetis K series uses the following SDID layout :
 137  * Bit 31-16 : 0
 138  * Bit 15-12 : REVID
 139  * Bit 11-7  : DIEID
 140  * Bit 6-4   : FAMID
 141  * Bit 3-0   : PINID
 142  *
 143  * The newer Kinetis series uses the following SDID layout :
 144  * Bit 31-28 : FAMID
 145  * Bit 27-24 : SUBFAMID
 146  * Bit 23-20 : SERIESID
 147  * Bit 19-16 : SRAMSIZE
 148  * Bit 15-12 : REVID
 149  * Bit 6-4   : Reserved (0)
 150  * Bit 3-0   : PINID
 151  *
 152  * We assume that if bits 31-16 are 0 then it's an older
 153  * K-series MCU.
 154  */
 155
 156 #define KINETIS_SOPT1_RAMSIZE_MASK  0x0000F000
 157 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
 158
 159 #define KINETIS_SDID_K_SERIES_MASK  0x0000FFFF
 160
 161 #define KINETIS_SDID_DIEID_MASK 0x00000F80
 162
 163 #define KINETIS_SDID_DIEID_K22FN128     0x00000680 /* smaller pflash with FTFA */
 164 #define KINETIS_SDID_DIEID_K22FN256     0x00000A80
 165 #define KINETIS_SDID_DIEID_K22FN512     0x00000E80
 166 #define KINETIS_SDID_DIEID_K24FN256     0x00000700
 167
 168 #define KINETIS_SDID_DIEID_K24FN1M      0x00000300 /* Detect Errata 7534 */
 169
 170 /* We can't rely solely on the FAMID field to determine the MCU
 171  * type since some FAMID values identify multiple MCUs with
 172  * different flash sector sizes (K20 and K22 for instance).
 173  * Therefore we combine it with the DIEID bits which may possibly
 174  * break if Freescale bumps the DIEID for a particular MCU. */
 175 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
 176 #define KINETIS_K_SDID_K10_M50   0x00000000
 177 #define KINETIS_K_SDID_K10_M72   0x00000080
 178 #define KINETIS_K_SDID_K10_M100  0x00000100
 179 #define KINETIS_K_SDID_K10_M120  0x00000180
 180 #define KINETIS_K_SDID_K11               0x00000220
 181 #define KINETIS_K_SDID_K12               0x00000200
 182 #define KINETIS_K_SDID_K20_M50   0x00000010
 183 #define KINETIS_K_SDID_K20_M72   0x00000090
 184 #define KINETIS_K_SDID_K20_M100  0x00000110
 185 #define KINETIS_K_SDID_K20_M120  0x00000190
 186 #define KINETIS_K_SDID_K21_M50   0x00000230
 187 #define KINETIS_K_SDID_K21_M120  0x00000330
 188 #define KINETIS_K_SDID_K22_M50   0x00000210
 189 #define KINETIS_K_SDID_K22_M120  0x00000310
 190 #define KINETIS_K_SDID_K30_M72   0x000000A0
 191 #define KINETIS_K_SDID_K30_M100  0x00000120
 192 #define KINETIS_K_SDID_K40_M72   0x000000B0
 193 #define KINETIS_K_SDID_K40_M100  0x00000130
 194 #define KINETIS_K_SDID_K50_M72   0x000000E0
 195 #define KINETIS_K_SDID_K51_M72   0x000000F0
 196 #define KINETIS_K_SDID_K53               0x00000170
 197 #define KINETIS_K_SDID_K60_M100  0x00000140
 198 #define KINETIS_K_SDID_K60_M150  0x000001C0
 199 #define KINETIS_K_SDID_K70_M150  0x000001D0
 200
 201 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
 202 #define KINETIS_SDID_SERIESID_K   0x00000000
 203 #define KINETIS_SDID_SERIESID_KL   0x00100000
 204 #define KINETIS_SDID_SERIESID_KE   0x00200000
 205 #define KINETIS_SDID_SERIESID_KW   0x00500000
 206 #define KINETIS_SDID_SERIESID_KV   0x00600000
 207
 208 #define KINETIS_SDID_SUBFAMID_SHIFT 24
 209 #define KINETIS_SDID_SUBFAMID_MASK  0x0F000000
 210 #define KINETIS_SDID_SUBFAMID_KX0   0x00000000
 211 #define KINETIS_SDID_SUBFAMID_KX1   0x01000000
 212 #define KINETIS_SDID_SUBFAMID_KX2   0x02000000
 213 #define KINETIS_SDID_SUBFAMID_KX3   0x03000000
 214 #define KINETIS_SDID_SUBFAMID_KX4   0x04000000
 215 #define KINETIS_SDID_SUBFAMID_KX5   0x05000000
 216 #define KINETIS_SDID_SUBFAMID_KX6   0x06000000
 217 #define KINETIS_SDID_SUBFAMID_KX7   0x07000000
 218 #define KINETIS_SDID_SUBFAMID_KX8   0x08000000
 219
 220 #define KINETIS_SDID_FAMILYID_SHIFT 28
 221 #define KINETIS_SDID_FAMILYID_MASK  0xF0000000
 222 #define KINETIS_SDID_FAMILYID_K0X   0x00000000
 223 #define KINETIS_SDID_FAMILYID_K1X   0x10000000
 224 #define KINETIS_SDID_FAMILYID_K2X   0x20000000
 225 #define KINETIS_SDID_FAMILYID_K3X   0x30000000
 226 #define KINETIS_SDID_FAMILYID_K4X   0x40000000
 227 #define KINETIS_SDID_FAMILYID_K5X   0x50000000
 228 #define KINETIS_SDID_FAMILYID_K6X   0x60000000
 229 #define KINETIS_SDID_FAMILYID_K7X   0x70000000
 230 #define KINETIS_SDID_FAMILYID_K8X   0x80000000
 231 #define KINETIS_SDID_FAMILYID_KL8X  0x90000000
 232
 233 /* The field originally named DIEID has new name/meaning on KE1x */
 234 #define KINETIS_SDID_PROJECTID_MASK  KINETIS_SDID_DIEID_MASK
 235 #define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
 236 #define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
 237
 238 struct kinetis_flash_bank {
 239         struct kinetis_chip *k_chip;
 240         bool probed;
 241         unsigned bank_number;           /* bank number in particular chip */
 242         struct flash_bank *bank;
 243
 244         uint32_t sector_size;
 245         uint32_t protection_size;
 246         uint32_t prog_base;             /* base address for FTFx operations */
 247                                         /* usually same as bank->base for pflash, differs for FlexNVM */
 248         uint32_t protection_block;      /* number of first protection block in this bank */
 249
 250         enum {
 251                 FC_AUTO = 0,
 252                 FC_PFLASH,
 253                 FC_FLEX_NVM,
 254                 FC_FLEX_RAM,
 255         } flash_class;
 256 };
 257
 258 #define KINETIS_MAX_BANKS 4u
 259
 260 struct kinetis_chip {
 261         struct target *target;
 262         bool probed;
 263
 264         uint32_t sim_sdid;
 265         uint32_t sim_fcfg1;
 266         uint32_t sim_fcfg2;
 267         uint32_t fcfg2_maxaddr0_shifted;
 268         uint32_t fcfg2_maxaddr1_shifted;
 269
 270         unsigned num_pflash_blocks, num_nvm_blocks;
 271         unsigned pflash_sector_size, nvm_sector_size;
 272         unsigned max_flash_prog_size;
 273
 274         uint32_t pflash_base;
 275         uint32_t pflash_size;
 276         uint32_t nvm_base;
 277         uint32_t nvm_size;              /* whole FlexNVM */
 278         uint32_t dflash_size;           /* accessible rest of FlexNVM if EEPROM backup uses part of FlexNVM */
 279
 280         uint32_t progr_accel_ram;
 281         uint32_t sim_base;
 282
 283         enum {
 284                 FS_PROGRAM_SECTOR = 1,
 285                 FS_PROGRAM_LONGWORD = 2,
 286                 FS_PROGRAM_PHRASE = 4,          /* Unsupported */
 287
 288                 FS_NO_CMD_BLOCKSTAT = 0x40,
 289                 FS_WIDTH_256BIT = 0x80,
 290                 FS_ECC = 0x100,
 291         } flash_support;
 292
 293         enum {
 294                 KINETIS_CACHE_NONE,
 295                 KINETIS_CACHE_K,        /* invalidate using FMC->PFB0CR/PFB01CR */
 296                 KINETIS_CACHE_L,        /* invalidate using MCM->PLACR */
 297                 KINETIS_CACHE_MSCM,     /* devices like KE1xF, invalidate MSCM->OCMDR0 */
 298         } cache_type;
 299
 300         enum {
 301                 KINETIS_WDOG_NONE,
 302                 KINETIS_WDOG_K,
 303                 KINETIS_WDOG_COP,
 304                 KINETIS_WDOG32_KE1X,
 305                 KINETIS_WDOG32_KL28,
 306         } watchdog_type;
 307
 308         enum {
 309                 KINETIS_SMC,
 310                 KINETIS_SMC32,
 311         } sysmodectrlr_type;
 312
 313         char name[40];
 314
 315         unsigned num_banks;
 316         struct kinetis_flash_bank banks[KINETIS_MAX_BANKS];
 317 };
 318
 319 struct kinetis_type {
 320         uint32_t sdid;
 321         char *name;
 322 };
 323
 324 static const struct kinetis_type kinetis_types_old[] = {
 325         { KINETIS_K_SDID_K10_M50,  "MK10D%s5" },
 326         { KINETIS_K_SDID_K10_M72,  "MK10D%s7" },
 327         { KINETIS_K_SDID_K10_M100, "MK10D%s10" },
 328         { KINETIS_K_SDID_K10_M120, "MK10F%s12" },
 329         { KINETIS_K_SDID_K11,      "MK11D%s5" },
 330         { KINETIS_K_SDID_K12,      "MK12D%s5" },
 331
 332         { KINETIS_K_SDID_K20_M50,  "MK20D%s5" },
 333         { KINETIS_K_SDID_K20_M72,  "MK20D%s7" },
 334         { KINETIS_K_SDID_K20_M100, "MK20D%s10" },
 335         { KINETIS_K_SDID_K20_M120, "MK20F%s12" },
 336         { KINETIS_K_SDID_K21_M50,  "MK21D%s5" },
 337         { KINETIS_K_SDID_K21_M120, "MK21F%s12" },
 338         { KINETIS_K_SDID_K22_M50,  "MK22D%s5" },
 339         { KINETIS_K_SDID_K22_M120, "MK22F%s12" },
 340
 341         { KINETIS_K_SDID_K30_M72,  "MK30D%s7" },
 342         { KINETIS_K_SDID_K30_M100, "MK30D%s10" },
 343
 344         { KINETIS_K_SDID_K40_M72,  "MK40D%s7" },
 345         { KINETIS_K_SDID_K40_M100, "MK40D%s10" },
 346
 347         { KINETIS_K_SDID_K50_M72,  "MK50D%s7" },
 348         { KINETIS_K_SDID_K51_M72,  "MK51D%s7" },
 349         { KINETIS_K_SDID_K53,      "MK53D%s10" },
 350
 351         { KINETIS_K_SDID_K60_M100, "MK60D%s10" },
 352         { KINETIS_K_SDID_K60_M150, "MK60F%s15" },
 353
 354         { KINETIS_K_SDID_K70_M150, "MK70F%s15" },
 355 };
 356
 357
 358 #define MDM_AP                  1
 359
 360 #define MDM_REG_STAT            0x00
 361 #define MDM_REG_CTRL            0x04
 362 #define MDM_REG_ID              0xfc
 363
 364 #define MDM_STAT_FMEACK         (1<<0)
 365 #define MDM_STAT_FREADY         (1<<1)
 366 #define MDM_STAT_SYSSEC         (1<<2)
 367 #define MDM_STAT_SYSRES         (1<<3)
 368 #define MDM_STAT_FMEEN          (1<<5)
 369 #define MDM_STAT_BACKDOOREN     (1<<6)
 370 #define MDM_STAT_LPEN           (1<<7)
 371 #define MDM_STAT_VLPEN          (1<<8)
 372 #define MDM_STAT_LLSMODEXIT     (1<<9)
 373 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 374 #define MDM_STAT_CORE_HALTED    (1<<16)
 375 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 376 #define MDM_STAT_CORESLEEPING   (1<<18)
 377
 378 #define MDM_CTRL_FMEIP          (1<<0)
 379 #define MDM_CTRL_DBG_DIS        (1<<1)
 380 #define MDM_CTRL_DBG_REQ        (1<<2)
 381 #define MDM_CTRL_SYS_RES_REQ    (1<<3)
 382 #define MDM_CTRL_CORE_HOLD_RES  (1<<4)
 383 #define MDM_CTRL_VLLSX_DBG_REQ  (1<<5)
 384 #define MDM_CTRL_VLLSX_DBG_ACK  (1<<6)
 385 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
 386
 387 #define MDM_ACCESS_TIMEOUT      500 /* msec */
 388
 389
 390 static bool allow_fcf_writes;
 391 static uint8_t fcf_fopt = 0xff;
 392 static bool fcf_fopt_configured;
 393 static bool create_banks;
 394
 395
 396 struct flash_driver kinetis_flash;
 397 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
 398                         uint32_t offset, uint32_t count);
 399 static int kinetis_probe_chip(struct kinetis_chip *k_chip);
 400 static int kinetis_auto_probe(struct flash_bank *bank);
 401
 402
 403 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
 404 {
 405         int retval;
 406         LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
 407
 408         retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
 409         if (retval != ERROR_OK) {
 410                 LOG_DEBUG("MDM: failed to queue a write request");
 411                 return retval;
 412         }
 413
 414         retval = dap_run(dap);
 415         if (retval != ERROR_OK) {
 416                 LOG_DEBUG("MDM: dap_run failed");
 417                 return retval;
 418         }
 419
 420
 421         return ERROR_OK;
 422 }
 423
 424 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
 425 {
 426         int retval;
 427
 428         retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
 429         if (retval != ERROR_OK) {
 430                 LOG_DEBUG("MDM: failed to queue a read request");
 431                 return retval;
 432         }
 433
 434         retval = dap_run(dap);
 435         if (retval != ERROR_OK) {
 436                 LOG_DEBUG("MDM: dap_run failed");
 437                 return retval;
 438         }
 439
 440         LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
 441         return ERROR_OK;
 442 }
 443
 444 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
 445                         uint32_t mask, uint32_t value, uint32_t timeout_ms)
 446 {
 447         uint32_t val;
 448         int retval;
 449         int64_t ms_timeout = timeval_ms() + timeout_ms;
 450
 451         do {
 452                 retval = kinetis_mdm_read_register(dap, reg, &val);
 453                 if (retval != ERROR_OK || (val & mask) == value)
 454                         return retval;
 455
 456                 alive_sleep(1);
 457         } while (timeval_ms() < ms_timeout);
 458
 459         LOG_DEBUG("MDM: polling timed out");
 460         return ERROR_FAIL;
 461 }
 462
 463 /*
 464  * This command can be used to break a watchdog reset loop when
 465  * connecting to an unsecured target. Unlike other commands, halt will
 466  * automatically retry as it does not know how far into the boot process
 467  * it is when the command is called.
 468  */
 469 COMMAND_HANDLER(kinetis_mdm_halt)
 470 {
 471         struct target *target = get_current_target(CMD_CTX);
 472         struct cortex_m_common *cortex_m = target_to_cm(target);
 473         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 474         int retval;
 475         int tries = 0;
 476         uint32_t stat;
 477         int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
 478
 479         if (!dap) {
 480                 LOG_ERROR("Cannot perform halt with a high-level adapter");
 481                 return ERROR_FAIL;
 482         }
 483
 484         while (true) {
 485                 tries++;
 486
 487                 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
 488
 489                 alive_sleep(1);
 490
 491                 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
 492                 if (retval != ERROR_OK) {
 493                         LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
 494                         continue;
 495                 }
 496
 497                 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
 498                  * reset with flash ready and without security
 499                  */
 500                 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
 501                                 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
 502                         break;
 503
 504                 if (timeval_ms() >= ms_timeout) {
 505                         LOG_ERROR("MDM: halt timed out");
 506                         return ERROR_FAIL;
 507                 }
 508         }
 509
 510         LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
 511
 512         target_poll(target);
 513         /* enable polling in case kinetis_check_flash_security_status disabled it */
 514         jtag_poll_set_enabled(true);
 515
 516         alive_sleep(100);
 517
 518         target->reset_halt = true;
 519         target->type->assert_reset(target);
 520
 521         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 522         if (retval != ERROR_OK) {
 523                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 524                 return retval;
 525         }
 526
 527         target->type->deassert_reset(target);
 528
 529         return ERROR_OK;
 530 }
 531
 532 COMMAND_HANDLER(kinetis_mdm_reset)
 533 {
 534         struct target *target = get_current_target(CMD_CTX);
 535         struct cortex_m_common *cortex_m = target_to_cm(target);
 536         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 537         int retval;
 538
 539         if (!dap) {
 540                 LOG_ERROR("Cannot perform reset with a high-level adapter");
 541                 return ERROR_FAIL;
 542         }
 543
 544         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
 545         if (retval != ERROR_OK) {
 546                 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
 547                 return retval;
 548         }
 549
 550         retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
 551         if (retval != ERROR_OK) {
 552                 LOG_ERROR("MDM: failed to assert reset");
 553                 return retval;
 554         }
 555
 556         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 557         if (retval != ERROR_OK) {
 558                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 559                 return retval;
 560         }
 561
 562         return ERROR_OK;
 563 }
 564
 565 /*
 566  * This function implements the procedure to mass erase the flash via
 567  * SWD/JTAG on Kinetis K and L series of devices as it is described in
 568  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
 569  * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
 570  * the core remains halted after this function completes as suggested
 571  * by the application note.
 572  */
 573 COMMAND_HANDLER(kinetis_mdm_mass_erase)
 574 {
 575         struct target *target = get_current_target(CMD_CTX);
 576         struct cortex_m_common *cortex_m = target_to_cm(target);
 577         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 578
 579         if (!dap) {
 580                 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
 581                 return ERROR_FAIL;
 582         }
 583
 584         int retval;
 585
 586         /*
 587          * ... Power on the processor, or if power has already been
 588          * applied, assert the RESET pin to reset the processor. For
 589          * devices that do not have a RESET pin, write the System
 590          * Reset Request bit in the MDM-AP control register after
 591          * establishing communication...
 592          */
 593
 594         /* assert SRST if configured */
 595         bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
 596         if (has_srst)
 597                 adapter_assert_reset();
 598
 599         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
 600         if (retval != ERROR_OK && !has_srst) {
 601                 LOG_ERROR("MDM: failed to assert reset");
 602                 goto deassert_reset_and_exit;
 603         }
 604
 605         /*
 606          * ... Read the MDM-AP status register repeatedly and wait for
 607          * stable conditions suitable for mass erase:
 608          * - mass erase is enabled
 609          * - flash is ready
 610          * - reset is finished
 611          *
 612          * Mass erase is started as soon as all conditions are met in 32
 613          * subsequent status reads.
 614          *
 615          * In case of not stable conditions (RESET/WDOG loop in secured device)
 616          * the user is asked for manual pressing of RESET button
 617          * as a last resort.
 618          */
 619         int cnt_mass_erase_disabled = 0;
 620         int cnt_ready = 0;
 621         int64_t ms_start = timeval_ms();
 622         bool man_reset_requested = false;
 623
 624         do {
 625                 uint32_t stat = 0;
 626                 int64_t ms_elapsed = timeval_ms() - ms_start;
 627
 628                 if (!man_reset_requested && ms_elapsed > 100) {
 629                         LOG_INFO("MDM: Press RESET button now if possible.");
 630                         man_reset_requested = true;
 631                 }
 632
 633                 if (ms_elapsed > 3000) {
 634                         LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
 635                         LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
 636                         LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
 637                         goto deassert_reset_and_exit;
 638                 }
 639                 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
 640                 if (retval != ERROR_OK) {
 641                         cnt_ready = 0;
 642                         continue;
 643                 }
 644
 645                 if (!(stat & MDM_STAT_FMEEN)) {
 646                         cnt_ready = 0;
 647                         cnt_mass_erase_disabled++;
 648                         if (cnt_mass_erase_disabled > 10) {
 649                                 LOG_ERROR("MDM: mass erase is disabled");
 650                                 goto deassert_reset_and_exit;
 651                         }
 652                         continue;
 653                 }
 654
 655                 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
 656                         cnt_ready++;
 657                 else
 658                         cnt_ready = 0;
 659
 660         } while (cnt_ready < 32);
 661
 662         /*
 663          * ... Write the MDM-AP control register to set the Flash Mass
 664          * Erase in Progress bit. This will start the mass erase
 665          * process...
 666          */
 667         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
 668         if (retval != ERROR_OK) {
 669                 LOG_ERROR("MDM: failed to start mass erase");
 670                 goto deassert_reset_and_exit;
 671         }
 672
 673         /*
 674          * ... Read the MDM-AP control register until the Flash Mass
 675          * Erase in Progress bit clears...
 676          * Data sheed defines erase time <3.6 sec/512kB flash block.
 677          * The biggest device has 4 pflash blocks => timeout 16 sec.
 678          */
 679         retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
 680         if (retval != ERROR_OK) {
 681                 LOG_ERROR("MDM: mass erase timeout");
 682                 goto deassert_reset_and_exit;
 683         }
 684
 685         target_poll(target);
 686         /* enable polling in case kinetis_check_flash_security_status disabled it */
 687         jtag_poll_set_enabled(true);
 688
 689         alive_sleep(100);
 690
 691         target->reset_halt = true;
 692         target->type->assert_reset(target);
 693
 694         /*
 695          * ... Negate the RESET signal or clear the System Reset Request
 696          * bit in the MDM-AP control register.
 697          */
 698         retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 699         if (retval != ERROR_OK)
 700                 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
 701
 702         target->type->deassert_reset(target);
 703
 704         return retval;
 705
 706 deassert_reset_and_exit:
 707         kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
 708         if (has_srst)
 709                 adapter_deassert_reset();
 710         return retval;
 711 }
 712
 713 static const uint32_t kinetis_known_mdm_ids[] = {
 714         0x001C0000,     /* Kinetis-K Series */
 715         0x001C0020,     /* Kinetis-L/M/V/E Series */
 716         0x001C0030,     /* Kinetis with a Cortex-M7, in time of writing KV58 */
 717 };
 718
 719 /*
 720  * This function implements the procedure to connect to
 721  * SWD/JTAG on Kinetis K and L series of devices as it is described in
 722  * AN4835 "Production Flash Programming Best Practices for Kinetis K-
 723  * and L-series MCUs" Section 4.1.1
 724  */
 725 COMMAND_HANDLER(kinetis_check_flash_security_status)
 726 {
 727         struct target *target = get_current_target(CMD_CTX);
 728         struct cortex_m_common *cortex_m = target_to_cm(target);
 729         struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
 730
 731         if (!dap) {
 732                 LOG_WARNING("Cannot check flash security status with a high-level adapter");
 733                 return ERROR_OK;
 734         }
 735
 736         if (!dap->ops)
 737                 return ERROR_OK;        /* too early to check, in JTAG mode ops may not be initialised */
 738
 739         uint32_t val;
 740         int retval;
 741
 742         /*
 743          * ... The MDM-AP ID register can be read to verify that the
 744          * connection is working correctly...
 745          */
 746         retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
 747         if (retval != ERROR_OK) {
 748                 LOG_ERROR("MDM: failed to read ID register");
 749                 return ERROR_OK;
 750         }
 751
 752         if (val == 0)
 753                 return ERROR_OK;        /* dap not yet initialised */
 754
 755         bool found = false;
 756         for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
 757                 if (val == kinetis_known_mdm_ids[i]) {
 758                         found = true;
 759                         break;
 760                 }
 761         }
 762
 763         if (!found)
 764                 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
 765
 766         /*
 767          * ... Read the System Security bit to determine if security is enabled.
 768          * If System Security = 0, then proceed. If System Security = 1, then
 769          * communication with the internals of the processor, including the
 770          * flash, will not be possible without issuing a mass erase command or
 771          * unsecuring the part through other means (backdoor key unlock)...
 772          */
 773         retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
 774         if (retval != ERROR_OK) {
 775                 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
 776                 return ERROR_OK;
 777         }
 778
 779         /*
 780          * System Security bit is also active for short time during reset.
 781          * If a MCU has blank flash and runs in RESET/WDOG loop,
 782          * System Security bit is active most of time!
 783          * We should observe Flash Ready bit and read status several times
 784          * to avoid false detection of secured MCU
 785          */
 786         int secured_score = 0, flash_not_ready_score = 0;
 787
 788         if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
 789                 uint32_t stats[32];
 790                 int i;
 791
 792                 for (i = 0; i < 32; i++) {
 793                         stats[i] = MDM_STAT_FREADY;
 794                         dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
 795                 }
 796                 retval = dap_run(dap);
 797                 if (retval != ERROR_OK) {
 798                         LOG_DEBUG("MDM: dap_run failed when validating secured state");
 799                         return ERROR_OK;
 800                 }
 801                 for (i = 0; i < 32; i++) {
 802                         if (stats[i] & MDM_STAT_SYSSEC)
 803                                 secured_score++;
 804                         if (!(stats[i] & MDM_STAT_FREADY))
 805                                 flash_not_ready_score++;
 806                 }
 807         }
 808
 809         if (flash_not_ready_score <= 8 && secured_score > 24) {
 810                 jtag_poll_set_enabled(false);
 811
 812                 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
 813                 LOG_WARNING("****                                                          ****");
 814                 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that,  ****");
 815                 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD    ****");
 816                 LOG_WARNING("**** interface will NOT work. In order to restore its         ****");
 817                 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase'      ****");
 818                 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD.        ****");
 819                 LOG_WARNING("****                                                          ****");
 820                 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
 821
 822         } else if (flash_not_ready_score > 24) {
 823                 jtag_poll_set_enabled(false);
 824                 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
 825                 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector).  ****");
 826                 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected   ****");
 827                 LOG_WARNING("**** and configured, use 'reset halt'                           ****");
 828                 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running  ****");
 829                 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase'         ****");
 830
 831         } else {
 832                 LOG_INFO("MDM: Chip is unsecured. Continuing.");
 833                 jtag_poll_set_enabled(true);
 834         }
 835
 836         return ERROR_OK;
 837 }
 838
 839
 840 static struct kinetis_chip *kinetis_get_chip(struct target *target)
 841 {
 842         struct flash_bank *bank_iter;
 843         struct kinetis_flash_bank *k_bank;
 844
 845         /* iterate over all kinetis banks */
 846         for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
 847                 if (bank_iter->driver != &kinetis_flash
 848                     || bank_iter->target != target)
 849                         continue;
 850
 851                 k_bank = bank_iter->driver_priv;
 852                 if (!k_bank)
 853                         continue;
 854
 855                 if (k_bank->k_chip)
 856                         return k_bank->k_chip;
 857         }
 858         return NULL;
 859 }
 860
 861 static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const char *argv[])
 862 {
 863         int i;
 864         for (i = 0; i < argc; i++) {
 865                 if (strcmp(argv[i], "-sim-base") == 0) {
 866                         if (i + 1 < argc)
 867                                 k_chip->sim_base = strtoul(argv[++i], NULL, 0);
 868                 } else
 869                         LOG_ERROR("Unsupported flash bank option %s", argv[i]);
 870         }
 871         return ERROR_OK;
 872 }
 873
 874 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
 875 {
 876         struct target *target = bank->target;
 877         struct kinetis_chip *k_chip;
 878         struct kinetis_flash_bank *k_bank;
 879         int retval;
 880
 881         if (CMD_ARGC < 6)
 882                 return ERROR_COMMAND_SYNTAX_ERROR;
 883
 884         LOG_INFO("add flash_bank kinetis %s", bank->name);
 885
 886         k_chip = kinetis_get_chip(target);
 887
 888         if (k_chip == NULL) {
 889                 k_chip = calloc(sizeof(struct kinetis_chip), 1);
 890                 if (k_chip == NULL) {
 891                         LOG_ERROR("No memory");
 892                         return ERROR_FAIL;
 893                 }
 894
 895                 k_chip->target = target;
 896
 897                 /* only the first defined bank can define chip options */
 898                 retval = kinetis_chip_options(k_chip, CMD_ARGC - 6, CMD_ARGV + 6);
 899                 if (retval != ERROR_OK)
 900                         return retval;
 901         }
 902
 903         if (k_chip->num_banks >= KINETIS_MAX_BANKS) {
 904                 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
 905                 return ERROR_FAIL;
 906         }
 907
 908         bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
 909         k_bank->k_chip = k_chip;
 910         k_bank->bank_number = k_chip->num_banks;
 911         k_bank->bank = bank;
 912         k_chip->num_banks++;
 913
 914         return ERROR_OK;
 915 }
 916
 917
 918 static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
 919 {
 920         unsigned bank_idx;
 921         unsigned num_blocks;
 922         struct kinetis_flash_bank *k_bank;
 923         struct flash_bank *bank;
 924         char base_name[80], name[80], num[4];
 925         char *class, *p;
 926
 927         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
 928         if (num_blocks > KINETIS_MAX_BANKS) {
 929                 LOG_ERROR("Only %u Kinetis flash banks are supported", KINETIS_MAX_BANKS);
 930                 return ERROR_FAIL;
 931         }
 932
 933         bank = k_chip->banks[0].bank;
 934         if (bank && bank->name) {
 935                 strncpy(base_name, bank->name, sizeof(base_name));
 936                 p = strstr(base_name, ".pflash");
 937                 if (p) {
 938                         *p = '\0';
 939                         if (k_chip->num_pflash_blocks > 1) {
 940                                 /* rename first bank if numbering is needed */
 941                                 snprintf(name, sizeof(name), "%s.pflash0", base_name);
 942                                 free((void *)bank->name);
 943                                 bank->name = strdup(name);
 944                         }
 945                 }
 946         } else {
 947                 strncpy(base_name, target_name(k_chip->target), sizeof(base_name));
 948                 p = strstr(base_name, ".cpu");
 949                 if (p)
 950                         *p = '\0';
 951         }
 952
 953         for (bank_idx = 1; bank_idx < num_blocks; bank_idx++) {
 954                 k_bank = &(k_chip->banks[bank_idx]);
 955                 bank = k_bank->bank;
 956
 957                 if (bank)
 958                         continue;
 959
 960                 num[0] = '\0';
 961
 962                 if (bank_idx < k_chip->num_pflash_blocks) {
 963                         class = "pflash";
 964                         if (k_chip->num_pflash_blocks > 1)
 965                                 snprintf(num, sizeof(num), "%u", bank_idx);
 966                 } else {
 967                         class = "flexnvm";
 968                         if (k_chip->num_nvm_blocks > 1)
 969                                 snprintf(num, sizeof(num), "%u",
 970                                          bank_idx - k_chip->num_pflash_blocks);
 971                 }
 972
 973                 bank = calloc(sizeof(struct flash_bank), 1);
 974                 if (bank == NULL)
 975                         return ERROR_FAIL;
 976
 977                 bank->target = k_chip->target;
 978                 bank->driver = &kinetis_flash;
 979                 bank->default_padded_value = bank->erased_value = 0xff;
 980
 981                 snprintf(name, sizeof(name), "%s.%s%s",
 982                          base_name, class, num);
 983                 bank->name = strdup(name);
 984
 985                 bank->driver_priv = k_bank = &(k_chip->banks[k_chip->num_banks]);
 986                 k_bank->k_chip = k_chip;
 987                 k_bank->bank_number = bank_idx;
 988                 k_bank->bank = bank;
 989                 if (k_chip->num_banks <= bank_idx)
 990                         k_chip->num_banks = bank_idx + 1;
 991
 992                 flash_bank_add(bank);
 993         }
 994         return ERROR_OK;
 995 }
 996
 997
 998 static int kinetis_disable_wdog_algo(struct target *target, size_t code_size, const uint8_t *code, uint32_t wdog_base)
 999 {
1000         struct working_area *wdog_algorithm;
1001         struct armv7m_algorithm armv7m_info;
1002         struct reg_param reg_params[1];
1003         int retval;
1004
1005         if (target->state != TARGET_HALTED) {
1006                 LOG_ERROR("Target not halted");
1007                 return ERROR_TARGET_NOT_HALTED;
1008         }
1009
1010         retval = target_alloc_working_area(target, code_size, &wdog_algorithm);
1011         if (retval != ERROR_OK)
1012                 return retval;
1013
1014         retval = target_write_buffer(target, wdog_algorithm->address,
1015                         code_size, code);
1016         if (retval == ERROR_OK) {
1017                 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1018                 armv7m_info.core_mode = ARM_MODE_THREAD;
1019
1020                 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
1021                 buf_set_u32(reg_params[0].value, 0, 32, wdog_base);
1022
1023                 retval = target_run_algorithm(target, 0, NULL, 1, reg_params,
1024                         wdog_algorithm->address,
1025                         wdog_algorithm->address + code_size - 2,
1026                         500, &armv7m_info);
1027
1028                 destroy_reg_param(&reg_params[0]);
1029
1030                 if (retval != ERROR_OK)
1031                         LOG_ERROR("Error executing Kinetis WDOG unlock algorithm");
1032         }
1033
1034         target_free_working_area(target, wdog_algorithm);
1035
1036         return retval;
1037 }
1038
1039 /* Disable the watchdog on Kinetis devices
1040  * Standard Kx WDOG peripheral checks timing and therefore requires to run algo.
1041  */
1042 static int kinetis_disable_wdog_kx(struct target *target)
1043 {
1044         const uint32_t wdog_base = WDOG_BASE;
1045         uint16_t wdog;
1046         int retval;
1047
1048         static const uint8_t kinetis_unlock_wdog_code[] = {
1049 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
1050         };
1051
1052         retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1053         if (retval != ERROR_OK)
1054                 return retval;
1055
1056         if ((wdog & 0x1) == 0) {
1057                 /* watchdog already disabled */
1058                 return ERROR_OK;
1059         }
1060         LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%04" PRIx16 ")", wdog);
1061
1062         retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1063         if (retval != ERROR_OK)
1064                 return retval;
1065
1066         retval = target_read_u16(target, wdog_base + WDOG_STCTRLH_OFFSET, &wdog);
1067         if (retval != ERROR_OK)
1068                 return retval;
1069
1070         LOG_INFO("WDOG_STCTRLH = 0x%04" PRIx16, wdog);
1071         return (wdog & 0x1) ? ERROR_FAIL : ERROR_OK;
1072 }
1073
1074 static int kinetis_disable_wdog32(struct target *target, uint32_t wdog_base)
1075 {
1076         uint32_t wdog_cs;
1077         int retval;
1078
1079         static const uint8_t kinetis_unlock_wdog_code[] = {
1080 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog32.inc"
1081         };
1082
1083         retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1084         if (retval != ERROR_OK)
1085                 return retval;
1086
1087         if ((wdog_cs & 0x80) == 0)
1088                 return ERROR_OK; /* watchdog already disabled */
1089
1090         LOG_INFO("Disabling Kinetis watchdog (initial WDOG_CS 0x%08" PRIx32 ")", wdog_cs);
1091
1092         retval = kinetis_disable_wdog_algo(target, sizeof(kinetis_unlock_wdog_code), kinetis_unlock_wdog_code, wdog_base);
1093         if (retval != ERROR_OK)
1094                 return retval;
1095
1096         retval = target_read_u32(target, wdog_base + WDOG32_CS_OFFSET, &wdog_cs);
1097         if (retval != ERROR_OK)
1098                 return retval;
1099
1100         if ((wdog_cs & 0x80) == 0)
1101                 return ERROR_OK; /* watchdog disabled successfully */
1102
1103         LOG_ERROR("Cannot disable Kinetis watchdog (WDOG_CS 0x%08" PRIx32 "), issue 'reset init'", wdog_cs);
1104         return ERROR_FAIL;
1105 }
1106
1107 static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
1108 {
1109         struct target *target = k_chip->target;
1110         uint8_t sim_copc;
1111         int retval;
1112
1113         if (!k_chip->probed) {
1114                 retval = kinetis_probe_chip(k_chip);
1115                 if (retval != ERROR_OK)
1116                         return retval;
1117         }
1118
1119         switch (k_chip->watchdog_type) {
1120         case KINETIS_WDOG_K:
1121                 return kinetis_disable_wdog_kx(target);
1122
1123         case KINETIS_WDOG_COP:
1124                 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1125                 if (retval != ERROR_OK)
1126                         return retval;
1127
1128                 if ((sim_copc & 0xc) == 0)
1129                         return ERROR_OK; /* watchdog already disabled */
1130
1131                 LOG_INFO("Disabling Kinetis watchdog (initial SIM_COPC 0x%02" PRIx8 ")", sim_copc);
1132                 retval = target_write_u8(target, SIM_COPC, sim_copc & ~0xc);
1133                 if (retval != ERROR_OK)
1134                         return retval;
1135
1136                 retval = target_read_u8(target, SIM_COPC, &sim_copc);
1137                 if (retval != ERROR_OK)
1138                         return retval;
1139
1140                 if ((sim_copc & 0xc) == 0)
1141                         return ERROR_OK; /* watchdog disabled successfully */
1142
1143                 LOG_ERROR("Cannot disable Kinetis watchdog (SIM_COPC 0x%02" PRIx8 "), issue 'reset init'", sim_copc);
1144                 return ERROR_FAIL;
1145
1146         case KINETIS_WDOG32_KE1X:
1147                 return kinetis_disable_wdog32(target, WDOG32_KE1X);
1148
1149         case KINETIS_WDOG32_KL28:
1150                 return kinetis_disable_wdog32(target, WDOG32_KL28);
1151
1152         default:
1153                 return ERROR_OK;
1154         }
1155 }
1156
1157 COMMAND_HANDLER(kinetis_disable_wdog_handler)
1158 {
1159         int result;
1160         struct target *target = get_current_target(CMD_CTX);
1161         struct kinetis_chip *k_chip = kinetis_get_chip(target);
1162
1163         if (k_chip == NULL)
1164                 return ERROR_FAIL;
1165
1166         if (CMD_ARGC > 0)
1167                 return ERROR_COMMAND_SYNTAX_ERROR;
1168
1169         result = kinetis_disable_wdog(k_chip);
1170         return result;
1171 }
1172
1173
1174 static int kinetis_ftfx_decode_error(uint8_t fstat)
1175 {
1176         if (fstat & 0x20) {
1177                 LOG_ERROR("Flash operation failed, illegal command");
1178                 return ERROR_FLASH_OPER_UNSUPPORTED;
1179
1180         } else if (fstat & 0x10)
1181                 LOG_ERROR("Flash operation failed, protection violated");
1182
1183         else if (fstat & 0x40)
1184                 LOG_ERROR("Flash operation failed, read collision");
1185
1186         else if (fstat & 0x80)
1187                 return ERROR_OK;
1188
1189         else
1190                 LOG_ERROR("Flash operation timed out");
1191
1192         return ERROR_FLASH_OPERATION_FAILED;
1193 }
1194
1195 static int kinetis_ftfx_clear_error(struct target *target)
1196 {
1197         /* reset error flags */
1198         return target_write_u8(target, FTFx_FSTAT, 0x70);
1199 }
1200
1201
1202 static int kinetis_ftfx_prepare(struct target *target)
1203 {
1204         int result, i;
1205         uint8_t fstat;
1206
1207         /* wait until busy */
1208         for (i = 0; i < 50; i++) {
1209                 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1210                 if (result != ERROR_OK)
1211                         return result;
1212
1213                 if (fstat & 0x80)
1214                         break;
1215         }
1216
1217         if ((fstat & 0x80) == 0) {
1218                 LOG_ERROR("Flash controller is busy");
1219                 return ERROR_FLASH_OPERATION_FAILED;
1220         }
1221         if (fstat != 0x80) {
1222                 /* reset error flags */
1223                 result = kinetis_ftfx_clear_error(target);
1224         }
1225         return result;
1226 }
1227
1228 /* Kinetis Program-LongWord Microcodes */
1229 static const uint8_t kinetis_flash_write_code[] = {
1230 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
1231 };
1232
1233 /* Program LongWord Block Write */
1234 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
1235                 uint32_t offset, uint32_t wcount)
1236 {
1237         struct target *target = bank->target;
1238         uint32_t buffer_size = 2048;            /* Default minimum value */
1239         struct working_area *write_algorithm;
1240         struct working_area *source;
1241         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1242         uint32_t address = k_bank->prog_base + offset;
1243         uint32_t end_address;
1244         struct reg_param reg_params[5];
1245         struct armv7m_algorithm armv7m_info;
1246         int retval;
1247         uint8_t fstat;
1248
1249         /* Increase buffer_size if needed */
1250         if (buffer_size < (target->working_area_size/2))
1251                 buffer_size = (target->working_area_size/2);
1252
1253         /* allocate working area with flash programming code */
1254         if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
1255                         &write_algorithm) != ERROR_OK) {
1256                 LOG_WARNING("no working area available, can't do block memory writes");
1257                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1258         }
1259
1260         retval = target_write_buffer(target, write_algorithm->address,
1261                 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
1262         if (retval != ERROR_OK)
1263                 return retval;
1264
1265         /* memory buffer */
1266         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
1267                 buffer_size /= 4;
1268                 if (buffer_size <= 256) {
1269                         /* free working area, write algorithm already allocated */
1270                         target_free_working_area(target, write_algorithm);
1271
1272                         LOG_WARNING("No large enough working area available, can't do block memory writes");
1273                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1274                 }
1275         }
1276
1277         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1278         armv7m_info.core_mode = ARM_MODE_THREAD;
1279
1280         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* address */
1281         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* word count */
1282         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1283         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1284         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1285
1286         buf_set_u32(reg_params[0].value, 0, 32, address);
1287         buf_set_u32(reg_params[1].value, 0, 32, wcount);
1288         buf_set_u32(reg_params[2].value, 0, 32, source->address);
1289         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
1290         buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
1291
1292         retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
1293                                                 0, NULL,
1294                                                 5, reg_params,
1295                                                 source->address, source->size,
1296                                                 write_algorithm->address, 0,
1297                                                 &armv7m_info);
1298
1299         if (retval == ERROR_FLASH_OPERATION_FAILED) {
1300                 end_address = buf_get_u32(reg_params[0].value, 0, 32);
1301
1302                 LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
1303
1304                 retval = target_read_u8(target, FTFx_FSTAT, &fstat);
1305                 if (retval == ERROR_OK) {
1306                         retval = kinetis_ftfx_decode_error(fstat);
1307
1308                         /* reset error flags */
1309                         target_write_u8(target, FTFx_FSTAT, 0x70);
1310                 }
1311         } else if (retval != ERROR_OK)
1312                 LOG_ERROR("Error executing kinetis Flash programming algorithm");
1313
1314         target_free_working_area(target, source);
1315         target_free_working_area(target, write_algorithm);
1316
1317         destroy_reg_param(&reg_params[0]);
1318         destroy_reg_param(&reg_params[1]);
1319         destroy_reg_param(&reg_params[2]);
1320         destroy_reg_param(&reg_params[3]);
1321         destroy_reg_param(&reg_params[4]);
1322
1323         return retval;
1324 }
1325
1326 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
1327 {
1328         int i;
1329
1330         if (allow_fcf_writes) {
1331                 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
1332                 return ERROR_FAIL;
1333         }
1334
1335         if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
1336                 LOG_ERROR("No protection possible for current bank!");
1337                 return ERROR_FLASH_BANK_INVALID;
1338         }
1339
1340         for (i = first; i < bank->num_prot_blocks && i <= last; i++)
1341                 bank->prot_blocks[i].is_protected = set;
1342
1343         LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
1344         LOG_INFO("Do not issue 'flash info' command until protection is written,");
1345         LOG_INFO("doing so would re-read protection status from MCU.");
1346
1347         return ERROR_OK;
1348 }
1349
1350 static int kinetis_protect_check(struct flash_bank *bank)
1351 {
1352         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1353         int result;
1354         int i, b;
1355         uint32_t fprot;
1356
1357         if (k_bank->flash_class == FC_PFLASH) {
1358
1359                 /* read protection register */
1360                 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
1361                 if (result != ERROR_OK)
1362                         return result;
1363
1364                 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1365
1366         } else if (k_bank->flash_class == FC_FLEX_NVM) {
1367                 uint8_t fdprot;
1368
1369                 /* read protection register */
1370                 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1371                 if (result != ERROR_OK)
1372                         return result;
1373
1374                 fprot = fdprot;
1375
1376         } else {
1377                 LOG_ERROR("Protection checks for FlexRAM not supported");
1378                 return ERROR_FLASH_BANK_INVALID;
1379         }
1380
1381         b = k_bank->protection_block;
1382         for (i = 0; i < bank->num_prot_blocks; i++) {
1383                 if ((fprot >> b) & 1)
1384                         bank->prot_blocks[i].is_protected = 0;
1385                 else
1386                         bank->prot_blocks[i].is_protected = 1;
1387
1388                 b++;
1389         }
1390
1391         return ERROR_OK;
1392 }
1393
1394
1395 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1396 {
1397         uint32_t fprot = 0xffffffff;
1398         uint8_t fsec = 0xfe;             /* set MCU unsecure */
1399         uint8_t fdprot = 0xff;
1400         int i;
1401         unsigned bank_idx;
1402         unsigned num_blocks;
1403         uint32_t pflash_bit;
1404         uint8_t dflash_bit;
1405         struct flash_bank *bank_iter;
1406         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1407         struct kinetis_chip *k_chip = k_bank->k_chip;
1408
1409         memset(fcf, 0xff, FCF_SIZE);
1410
1411         pflash_bit = 1;
1412         dflash_bit = 1;
1413
1414         /* iterate over all kinetis banks */
1415         /* current bank is bank 0, it contains FCF */
1416         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
1417         for (bank_idx = 0; bank_idx < num_blocks; bank_idx++) {
1418                 k_bank = &(k_chip->banks[bank_idx]);
1419                 bank_iter = k_bank->bank;
1420
1421                 if (bank_iter == NULL) {
1422                         LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
1423                         continue;
1424                 }
1425
1426                 kinetis_auto_probe(bank_iter);
1427
1428                 if (k_bank->flash_class == FC_PFLASH) {
1429                         for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1430                                 if (bank_iter->prot_blocks[i].is_protected == 1)
1431                                         fprot &= ~pflash_bit;
1432
1433                                 pflash_bit <<= 1;
1434                         }
1435
1436                 } else if (k_bank->flash_class == FC_FLEX_NVM) {
1437                         for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1438                                 if (bank_iter->prot_blocks[i].is_protected == 1)
1439                                         fdprot &= ~dflash_bit;
1440
1441                                 dflash_bit <<= 1;
1442                         }
1443
1444                 }
1445         }
1446
1447         target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1448         fcf[FCF_FSEC] = fsec;
1449         fcf[FCF_FOPT] = fcf_fopt;
1450         fcf[FCF_FDPROT] = fdprot;
1451         return ERROR_OK;
1452 }
1453
1454 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1455                                 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1456                                 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1457                                 uint8_t *ftfx_fstat)
1458 {
1459         uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1460                         fccob7, fccob6, fccob5, fccob4,
1461                         fccobb, fccoba, fccob9, fccob8};
1462         int result;
1463         uint8_t fstat;
1464         int64_t ms_timeout = timeval_ms() + 250;
1465
1466         result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1467         if (result != ERROR_OK)
1468                 return result;
1469
1470         /* start command */
1471         result = target_write_u8(target, FTFx_FSTAT, 0x80);
1472         if (result != ERROR_OK)
1473                 return result;
1474
1475         /* wait for done */
1476         do {
1477                 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1478
1479                 if (result != ERROR_OK)
1480                         return result;
1481
1482                 if (fstat & 0x80)
1483                         break;
1484
1485         } while (timeval_ms() < ms_timeout);
1486
1487         if (ftfx_fstat)
1488                 *ftfx_fstat = fstat;
1489
1490         if ((fstat & 0xf0) != 0x80) {
1491                 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1492                          fstat, command[3], command[2], command[1], command[0],
1493                          command[7], command[6], command[5], command[4],
1494                          command[11], command[10], command[9], command[8]);
1495
1496                 return kinetis_ftfx_decode_error(fstat);
1497         }
1498
1499         return ERROR_OK;
1500 }
1501
1502
1503 static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
1504 {
1505         int result;
1506         uint32_t stat32;
1507         struct target *target = k_chip->target;
1508
1509         switch (k_chip->sysmodectrlr_type) {
1510         case KINETIS_SMC:
1511                 result = target_read_u8(target, SMC_PMSTAT, pmstat);
1512                 return result;
1513
1514         case KINETIS_SMC32:
1515                 result = target_read_u32(target, SMC32_PMSTAT, &stat32);
1516                 if (result == ERROR_OK)
1517                         *pmstat = stat32 & 0xff;
1518                 return result;
1519         }
1520         return ERROR_FAIL;
1521 }
1522
1523 static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
1524 {
1525         int result, i;
1526         uint8_t pmstat;
1527         struct target *target;
1528
1529         if (k_chip == NULL) {
1530                 LOG_ERROR("Chip not probed.");
1531                 return ERROR_FAIL;
1532         }
1533         target = k_chip->target;
1534
1535         if (target->state != TARGET_HALTED) {
1536                 LOG_ERROR("Target not halted");
1537                 return ERROR_TARGET_NOT_HALTED;
1538         }
1539
1540         result = kinetis_read_pmstat(k_chip, &pmstat);
1541         if (result != ERROR_OK)
1542                 return result;
1543
1544         if (pmstat == PM_STAT_RUN)
1545                 return ERROR_OK;
1546
1547         if (pmstat == PM_STAT_VLPR) {
1548                 /* It is safe to switch from VLPR to RUN mode without changing clock */
1549                 LOG_INFO("Switching from VLPR to RUN mode.");
1550
1551                 switch (k_chip->sysmodectrlr_type) {
1552                 case KINETIS_SMC:
1553                         result = target_write_u8(target, SMC_PMCTRL, PM_CTRL_RUNM_RUN);
1554                         break;
1555
1556                 case KINETIS_SMC32:
1557                         result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
1558                         break;
1559                 }
1560                 if (result != ERROR_OK)
1561                         return result;
1562
1563                 for (i = 100; i; i--) {
1564                         result = kinetis_read_pmstat(k_chip, &pmstat);
1565                         if (result != ERROR_OK)
1566                                 return result;
1567
1568                         if (pmstat == PM_STAT_RUN)
1569                                 return ERROR_OK;
1570                 }
1571         }
1572
1573         LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1574         LOG_ERROR("Issue a 'reset init' command.");
1575         return ERROR_TARGET_NOT_HALTED;
1576 }
1577
1578
1579 static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
1580 {
1581         struct target *target = k_chip->target;
1582
1583         switch (k_chip->cache_type) {
1584         case KINETIS_CACHE_K:
1585                 target_write_u8(target, FMC_PFB01CR + 2, 0xf0);
1586                 /* Set CINV_WAY bits - request invalidate of all cache ways */
1587                 /* FMC_PFB0CR has same address and CINV_WAY bits as FMC_PFB01CR */
1588                 break;
1589
1590         case KINETIS_CACHE_L:
1591                 target_write_u8(target, MCM_PLACR + 1, 0x04);
1592                 /* set bit CFCC - Clear Flash Controller Cache */
1593                 break;
1594
1595         case KINETIS_CACHE_MSCM:
1596                 target_write_u32(target, MSCM_OCMDR0, 0x30);
1597                 /* disable data prefetch and flash speculate */
1598                 break;
1599
1600         default:
1601                 break;
1602         }
1603 }
1604
1605
1606 static int kinetis_erase(struct flash_bank *bank, int first, int last)
1607 {
1608         int result, i;
1609         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1610         struct kinetis_chip *k_chip = k_bank->k_chip;
1611
1612         result = kinetis_check_run_mode(k_chip);
1613         if (result != ERROR_OK)
1614                 return result;
1615
1616         /* reset error flags */
1617         result = kinetis_ftfx_prepare(bank->target);
1618         if (result != ERROR_OK)
1619                 return result;
1620
1621         if ((first > bank->num_sectors) || (last > bank->num_sectors))
1622                 return ERROR_FLASH_OPERATION_FAILED;
1623
1624         /*
1625          * FIXME: TODO: use the 'Erase Flash Block' command if the
1626          * requested erase is PFlash or NVM and encompasses the entire
1627          * block.  Should be quicker.
1628          */
1629         for (i = first; i <= last; i++) {
1630                 /* set command and sector address */
1631                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
1632                                 0, 0, 0, 0,  0, 0, 0, 0,  NULL);
1633
1634                 if (result != ERROR_OK) {
1635                         LOG_WARNING("erase sector %d failed", i);
1636                         return ERROR_FLASH_OPERATION_FAILED;
1637                 }
1638
1639                 bank->sectors[i].is_erased = 1;
1640
1641                 if (k_bank->prog_base == 0
1642                         && bank->sectors[i].offset <= FCF_ADDRESS
1643                         && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1644                         if (allow_fcf_writes) {
1645                                 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1646                                 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1647                         } else {
1648                                 uint8_t fcf_buffer[FCF_SIZE];
1649
1650                                 kinetis_fill_fcf(bank, fcf_buffer);
1651                                 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1652                                 if (result != ERROR_OK)
1653                                         LOG_WARNING("Flash Configuration Field write failed");
1654                                 bank->sectors[i].is_erased = 0;
1655                         }
1656                 }
1657         }
1658
1659         kinetis_invalidate_flash_cache(k_bank->k_chip);
1660
1661         return ERROR_OK;
1662 }
1663
1664 static int kinetis_make_ram_ready(struct target *target)
1665 {
1666         int result;
1667         uint8_t ftfx_fcnfg;
1668
1669         /* check if ram ready */
1670         result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1671         if (result != ERROR_OK)
1672                 return result;
1673
1674         if (ftfx_fcnfg & (1 << 1))
1675                 return ERROR_OK;        /* ram ready */
1676
1677         /* make flex ram available */
1678         result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1679                                  0, 0, 0, 0,  0, 0, 0, 0,  NULL);
1680         if (result != ERROR_OK)
1681                 return ERROR_FLASH_OPERATION_FAILED;
1682
1683         /* check again */
1684         result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1685         if (result != ERROR_OK)
1686                 return result;
1687
1688         if (ftfx_fcnfg & (1 << 1))
1689                 return ERROR_OK;        /* ram ready */
1690
1691         return ERROR_FLASH_OPERATION_FAILED;
1692 }
1693
1694
1695 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1696                          uint32_t offset, uint32_t count)
1697 {
1698         int result = ERROR_OK;
1699         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1700         struct kinetis_chip *k_chip = k_bank->k_chip;
1701         uint8_t *buffer_aligned = NULL;
1702         /*
1703          * Kinetis uses different terms for the granularity of
1704          * sector writes, e.g. "phrase" or "128 bits".  We use
1705          * the generic term "chunk". The largest possible
1706          * Kinetis "chunk" is 16 bytes (128 bits).
1707          */
1708         uint32_t prog_section_chunk_bytes = k_bank->sector_size >> 8;
1709         uint32_t prog_size_bytes = k_chip->max_flash_prog_size;
1710
1711         while (count > 0) {
1712                 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1713                 uint32_t align_begin = offset % prog_section_chunk_bytes;
1714                 uint32_t align_end;
1715                 uint32_t size_aligned;
1716                 uint16_t chunk_count;
1717                 uint8_t ftfx_fstat;
1718
1719                 if (size > count)
1720                         size = count;
1721
1722                 align_end = (align_begin + size) % prog_section_chunk_bytes;
1723                 if (align_end)
1724                         align_end = prog_section_chunk_bytes - align_end;
1725
1726                 size_aligned = align_begin + size + align_end;
1727                 chunk_count = size_aligned / prog_section_chunk_bytes;
1728
1729                 if (size != size_aligned) {
1730                         /* aligned section: the first, the last or the only */
1731                         if (!buffer_aligned)
1732                                 buffer_aligned = malloc(prog_size_bytes);
1733
1734                         memset(buffer_aligned, 0xff, size_aligned);
1735                         memcpy(buffer_aligned + align_begin, buffer, size);
1736
1737                         result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1738                                                 4, size_aligned / 4, buffer_aligned);
1739
1740                         LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
1741                                         bank->base + offset, align_begin, align_end);
1742                 } else
1743                         result = target_write_memory(bank->target, k_chip->progr_accel_ram,
1744                                                 4, size_aligned / 4, buffer);
1745
1746                 LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
1747                           bank->base + offset, size);
1748
1749                 if (result != ERROR_OK) {
1750                         LOG_ERROR("target_write_memory failed");
1751                         break;
1752                 }
1753
1754                 /* execute section-write command */
1755                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1756                                 k_bank->prog_base + offset - align_begin,
1757                                 chunk_count>>8, chunk_count, 0, 0,
1758                                 0, 0, 0, 0,  &ftfx_fstat);
1759
1760                 if (result != ERROR_OK) {
1761                         LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
1762                         break;
1763                 }
1764
1765                 if (ftfx_fstat & 0x01) {
1766                         LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1767                         if (k_bank->prog_base == 0 && offset == FCF_ADDRESS + FCF_SIZE
1768                                         && (k_chip->flash_support & FS_WIDTH_256BIT)) {
1769                                 LOG_ERROR("Flash write immediately after the end of Flash Config Field shows error");
1770                                 LOG_ERROR("because the flash memory is 256 bits wide (data were written correctly).");
1771                                 LOG_ERROR("Either change the linker script to add a gap of 16 bytes after FCF");
1772                                 LOG_ERROR("or set 'kinetis fcf_source write'");
1773                         }
1774                 }
1775
1776                 buffer += size;
1777                 offset += size;
1778                 count -= size;
1779         }
1780
1781         free(buffer_aligned);
1782         return result;
1783 }
1784
1785
1786 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1787                          uint32_t offset, uint32_t count)
1788 {
1789         int result, fallback = 0;
1790         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1791         struct kinetis_chip *k_chip = k_bank->k_chip;
1792
1793         if (!(k_chip->flash_support & FS_PROGRAM_SECTOR)) {
1794                 /* fallback to longword write */
1795                 fallback = 1;
1796                 LOG_INFO("This device supports Program Longword execution only.");
1797         } else {
1798                 result = kinetis_make_ram_ready(bank->target);
1799                 if (result != ERROR_OK) {
1800                         fallback = 1;
1801                         LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1802                 }
1803         }
1804
1805         LOG_DEBUG("flash write @ %08" PRIx32, bank->base + offset);
1806
1807         if (fallback == 0) {
1808                 /* program section command */
1809                 kinetis_write_sections(bank, buffer, offset, count);
1810         } else if (k_chip->flash_support & FS_PROGRAM_LONGWORD) {
1811                 /* program longword command, not supported in FTFE */
1812                 uint8_t *new_buffer = NULL;
1813
1814                 /* check word alignment */
1815                 if (offset & 0x3) {
1816                         LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1817                         return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1818                 }
1819
1820                 if (count & 0x3) {
1821                         uint32_t old_count = count;
1822                         count = (old_count | 3) + 1;
1823                         new_buffer = malloc(count);
1824                         if (new_buffer == NULL) {
1825                                 LOG_ERROR("odd number of bytes to write and no memory "
1826                                         "for padding buffer");
1827                                 return ERROR_FAIL;
1828                         }
1829                         LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1830                                 "and padding with 0xff", old_count, count);
1831                         memset(new_buffer + old_count, 0xff, count - old_count);
1832                         buffer = memcpy(new_buffer, buffer, old_count);
1833                 }
1834
1835                 uint32_t words_remaining = count / 4;
1836
1837                 kinetis_disable_wdog(k_chip);
1838
1839                 /* try using a block write */
1840                 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1841
1842                 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1843                         /* if block write failed (no sufficient working area),
1844                          * we use normal (slow) single word accesses */
1845                         LOG_WARNING("couldn't use block writes, falling back to single "
1846                                 "memory accesses");
1847
1848                         while (words_remaining) {
1849                                 uint8_t ftfx_fstat;
1850
1851                                 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1852
1853                                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
1854                                                 buffer[3], buffer[2], buffer[1], buffer[0],
1855                                                 0, 0, 0, 0,  &ftfx_fstat);
1856
1857                                 if (result != ERROR_OK) {
1858                                         LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
1859                                         break;
1860                                 }
1861
1862                                 if (ftfx_fstat & 0x01)
1863                                         LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1864
1865                                 buffer += 4;
1866                                 offset += 4;
1867                                 words_remaining--;
1868                         }
1869                 }
1870                 free(new_buffer);
1871         } else {
1872                 LOG_ERROR("Flash write strategy not implemented");
1873                 return ERROR_FLASH_OPERATION_FAILED;
1874         }
1875
1876         kinetis_invalidate_flash_cache(k_chip);
1877         return result;
1878 }
1879
1880
1881 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1882                          uint32_t offset, uint32_t count)
1883 {
1884         int result;
1885         bool set_fcf = false;
1886         bool fcf_in_data_valid = false;
1887         int sect = 0;
1888         struct kinetis_flash_bank *k_bank = bank->driver_priv;
1889         struct kinetis_chip *k_chip = k_bank->k_chip;
1890         uint8_t fcf_buffer[FCF_SIZE];
1891         uint8_t fcf_current[FCF_SIZE];
1892         uint8_t fcf_in_data[FCF_SIZE];
1893
1894         result = kinetis_check_run_mode(k_chip);
1895         if (result != ERROR_OK)
1896                 return result;
1897
1898         /* reset error flags */
1899         result = kinetis_ftfx_prepare(bank->target);
1900         if (result != ERROR_OK)
1901                 return result;
1902
1903         if (k_bank->prog_base == 0 && !allow_fcf_writes) {
1904                 if (bank->sectors[1].offset <= FCF_ADDRESS)
1905                         sect = 1;       /* 1kb sector, FCF in 2nd sector */
1906
1907                 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1908                         && offset + count > bank->sectors[sect].offset)
1909                         set_fcf = true; /* write to any part of sector with FCF */
1910         }
1911
1912         if (set_fcf) {
1913                 kinetis_fill_fcf(bank, fcf_buffer);
1914
1915                 fcf_in_data_valid = offset <= FCF_ADDRESS
1916                                          && offset + count >= FCF_ADDRESS + FCF_SIZE;
1917                 if (fcf_in_data_valid) {
1918                         memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
1919                         if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
1920                                 fcf_in_data_valid = false;
1921                                 LOG_INFO("Flash protection requested in programmed file differs from current setting.");
1922                         }
1923                         if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
1924                                 fcf_in_data_valid = false;
1925                                 LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
1926                         }
1927                         if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
1928                                 fcf_in_data_valid = false;
1929                                 LOG_INFO("Device security requested in programmed file!");
1930                         } else if (k_chip->flash_support & FS_ECC
1931                             && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
1932                                 fcf_in_data_valid = false;
1933                                 LOG_INFO("Strange unsecure mode 0x%02" PRIx8
1934                                          "requested in programmed file!",
1935                                          fcf_in_data[FCF_FSEC]);
1936                         }
1937                         if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
1938                             && fcf_in_data[FCF_FOPT] != fcf_fopt) {
1939                                 fcf_in_data_valid = false;
1940                                 LOG_INFO("FOPT requested in programmed file differs from current setting.");
1941                         }
1942                         if (!fcf_in_data_valid)
1943                                 LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
1944                 }
1945         }
1946
1947         if (set_fcf && !fcf_in_data_valid) {
1948                 if (offset < FCF_ADDRESS) {
1949                         /* write part preceding FCF */
1950                         result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1951                         if (result != ERROR_OK)
1952                                 return result;
1953                 }
1954
1955                 result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1956                 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1957                         set_fcf = false;
1958
1959                 if (set_fcf) {
1960                         /* write FCF if differs from flash - eliminate multiple writes */
1961                         result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1962                         if (result != ERROR_OK)
1963                                 return result;
1964                 }
1965
1966                 LOG_WARNING("Flash Configuration Field written.");
1967                 LOG_WARNING("Reset or power off the device to make settings effective.");
1968
1969                 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1970                         uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1971                         /* write part after FCF */
1972                         result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
1973                 }
1974                 return result;
1975
1976         } else {
1977                 /* no FCF fiddling, normal write */
1978                 return kinetis_write_inner(bank, buffer, offset, count);
1979         }
1980 }
1981
1982
1983 static int kinetis_probe_chip(struct kinetis_chip *k_chip)
1984 {
1985         int result;
1986         uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
1987         uint8_t fcfg2_pflsh;
1988         uint32_t ee_size = 0;
1989         uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
1990         uint32_t pflash_size_m;
1991         unsigned num_blocks = 0;
1992         unsigned maxaddr_shift = 13;
1993         struct target *target = k_chip->target;
1994
1995         unsigned familyid = 0, subfamid = 0;
1996         unsigned cpu_mhz = 120;
1997         unsigned idx;
1998         bool use_nvm_marking = false;
1999         char flash_marking[11], nvm_marking[2];
2000         char name[40];
2001
2002         k_chip->probed = false;
2003         k_chip->pflash_sector_size = 0;
2004         k_chip->pflash_base = 0;
2005         k_chip->nvm_base = 0x10000000;
2006         k_chip->progr_accel_ram = FLEXRAM;
2007
2008         name[0] = '\0';
2009
2010         if (k_chip->sim_base)
2011                 result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2012         else {
2013                 result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2014                 if (result == ERROR_OK)
2015                         k_chip->sim_base = SIM_BASE;
2016                 else {
2017                         result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
2018                         if (result == ERROR_OK)
2019                                 k_chip->sim_base = SIM_BASE_KL28;
2020                 }
2021         }
2022         if (result != ERROR_OK)
2023                 return result;
2024
2025         if ((k_chip->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
2026                 /* older K-series MCU */
2027                 uint32_t mcu_type = k_chip->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
2028                 k_chip->cache_type = KINETIS_CACHE_K;
2029                 k_chip->watchdog_type = KINETIS_WDOG_K;
2030
2031                 switch (mcu_type) {
2032                 case KINETIS_K_SDID_K10_M50:
2033                 case KINETIS_K_SDID_K20_M50:
2034                         /* 1kB sectors */
2035                         k_chip->pflash_sector_size = 1<<10;
2036                         k_chip->nvm_sector_size = 1<<10;
2037                         num_blocks = 2;
2038                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2039                         break;
2040                 case KINETIS_K_SDID_K10_M72:
2041                 case KINETIS_K_SDID_K20_M72:
2042                 case KINETIS_K_SDID_K30_M72:
2043                 case KINETIS_K_SDID_K30_M100:
2044                 case KINETIS_K_SDID_K40_M72:
2045                 case KINETIS_K_SDID_K40_M100:
2046                 case KINETIS_K_SDID_K50_M72:
2047                         /* 2kB sectors, 1kB FlexNVM sectors */
2048                         k_chip->pflash_sector_size = 2<<10;
2049                         k_chip->nvm_sector_size = 1<<10;
2050                         num_blocks = 2;
2051                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2052                         k_chip->max_flash_prog_size = 1<<10;
2053                         break;
2054                 case KINETIS_K_SDID_K10_M100:
2055                 case KINETIS_K_SDID_K20_M100:
2056                 case KINETIS_K_SDID_K11:
2057                 case KINETIS_K_SDID_K12:
2058                 case KINETIS_K_SDID_K21_M50:
2059                 case KINETIS_K_SDID_K22_M50:
2060                 case KINETIS_K_SDID_K51_M72:
2061                 case KINETIS_K_SDID_K53:
2062                 case KINETIS_K_SDID_K60_M100:
2063                         /* 2kB sectors */
2064                         k_chip->pflash_sector_size = 2<<10;
2065                         k_chip->nvm_sector_size = 2<<10;
2066                         num_blocks = 2;
2067                         k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR;
2068                         break;
2069                 case KINETIS_K_SDID_K21_M120:
2070                 case KINETIS_K_SDID_K22_M120:
2071                         /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
2072                         k_chip->pflash_sector_size = 4<<10;
2073                         k_chip->max_flash_prog_size = 1<<10;
2074                         k_chip->nvm_sector_size = 4<<10;
2075                         num_blocks = 2;
2076                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2077                         break;
2078                 case KINETIS_K_SDID_K10_M120:
2079                 case KINETIS_K_SDID_K20_M120:
2080                 case KINETIS_K_SDID_K60_M150:
2081                 case KINETIS_K_SDID_K70_M150:
2082                         /* 4kB sectors */
2083                         k_chip->pflash_sector_size = 4<<10;
2084                         k_chip->nvm_sector_size = 4<<10;
2085                         num_blocks = 4;
2086                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2087                         break;
2088                 default:
2089                         LOG_ERROR("Unsupported K-family FAMID");
2090                 }
2091
2092                 for (idx = 0; idx < ARRAY_SIZE(kinetis_types_old); idx++) {
2093                         if (kinetis_types_old[idx].sdid == mcu_type) {
2094                                 strcpy(name, kinetis_types_old[idx].name);
2095                                 use_nvm_marking = true;
2096                                 break;
2097                         }
2098                 }
2099
2100         } else {
2101                 /* Newer K-series or KL series MCU */
2102                 familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
2103                 subfamid = (k_chip->sim_sdid & KINETIS_SDID_SUBFAMID_MASK) >> KINETIS_SDID_SUBFAMID_SHIFT;
2104
2105                 switch (k_chip->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
2106                 case KINETIS_SDID_SERIESID_K:
2107                         use_nvm_marking = true;
2108                         k_chip->cache_type = KINETIS_CACHE_K;
2109                         k_chip->watchdog_type = KINETIS_WDOG_K;
2110
2111                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2112                         case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
2113                                 /* K02FN64, K02FN128: FTFA, 2kB sectors */
2114                                 k_chip->pflash_sector_size = 2<<10;
2115                                 num_blocks = 1;
2116                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2117                                 cpu_mhz = 100;
2118                                 break;
2119
2120                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
2121                                 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
2122                                 uint32_t sopt1;
2123                                 result = target_read_u32(target, k_chip->sim_base + SIM_SOPT1_OFFSET, &sopt1);
2124                                 if (result != ERROR_OK)
2125                                         return result;
2126
2127                                 if (((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
2128                                                 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
2129                                         /* MK24FN1M */
2130                                         k_chip->pflash_sector_size = 4<<10;
2131                                         num_blocks = 2;
2132                                         k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2133                                         k_chip->max_flash_prog_size = 1<<10;
2134                                         subfamid = 4; /* errata 1N83J fix */
2135                                         break;
2136                                 }
2137                                 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
2138                                         || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
2139                                         || (k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
2140                                         /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
2141                                         k_chip->pflash_sector_size = 2<<10;
2142                                         /* autodetect 1 or 2 blocks */
2143                                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2144                                         break;
2145                                 }
2146                                 LOG_ERROR("Unsupported Kinetis K22 DIEID");
2147                                 break;
2148                         }
2149                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
2150                                 k_chip->pflash_sector_size = 4<<10;
2151                                 if ((k_chip->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
2152                                         /* K24FN256 - smaller pflash with FTFA */
2153                                         num_blocks = 1;
2154                                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2155                                         break;
2156                                 }
2157                                 /* K24FN1M without errata 7534 */
2158                                 num_blocks = 2;
2159                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2160                                 k_chip->max_flash_prog_size = 1<<10;
2161                                 break;
2162
2163                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1:     /* errata 7534 - should be K63 */
2164                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2:     /* errata 7534 - should be K64 */
2165                                 subfamid += 2; /* errata 7534 fix */
2166                                 /* fallthrough */
2167                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
2168                                 /* K63FN1M0 */
2169                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
2170                                 /* K64FN1M0, K64FX512 */
2171                                 k_chip->pflash_sector_size = 4<<10;
2172                                 k_chip->nvm_sector_size = 4<<10;
2173                                 k_chip->max_flash_prog_size = 1<<10;
2174                                 num_blocks = 2;
2175                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2176                                 break;
2177
2178                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
2179                                 /* K26FN2M0 */
2180                         case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
2181                                 /* K66FN2M0, K66FX1M0 */
2182                                 k_chip->pflash_sector_size = 4<<10;
2183                                 k_chip->nvm_sector_size = 4<<10;
2184                                 k_chip->max_flash_prog_size = 1<<10;
2185                                 num_blocks = 4;
2186                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_ECC;
2187                                 cpu_mhz = 180;
2188                                 break;
2189
2190                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX0:
2191                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX1:
2192                         case KINETIS_SDID_FAMILYID_K8X | KINETIS_SDID_SUBFAMID_KX2:
2193                                 /* K80FN256, K81FN256, K82FN256 */
2194                                 k_chip->pflash_sector_size = 4<<10;
2195                                 num_blocks = 1;
2196                                 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2197                                 cpu_mhz = 150;
2198                                 break;
2199
2200                         case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX1:
2201                         case KINETIS_SDID_FAMILYID_KL8X | KINETIS_SDID_SUBFAMID_KX2:
2202                                 /* KL81Z128, KL82Z128 */
2203                                 k_chip->pflash_sector_size = 2<<10;
2204                                 num_blocks = 1;
2205                                 k_chip->flash_support = FS_PROGRAM_LONGWORD | FS_NO_CMD_BLOCKSTAT;
2206                                 k_chip->cache_type = KINETIS_CACHE_L;
2207
2208                                 use_nvm_marking = false;
2209                                 snprintf(name, sizeof(name), "MKL8%uZ%%s7",
2210                                          subfamid);
2211                                 break;
2212
2213                         default:
2214                                 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
2215                         }
2216
2217                         if (name[0] == '\0')
2218                                 snprintf(name, sizeof(name), "MK%u%uF%%s%u",
2219                                          familyid, subfamid, cpu_mhz / 10);
2220                         break;
2221
2222                 case KINETIS_SDID_SERIESID_KL:
2223                         /* KL-series */
2224                         k_chip->pflash_sector_size = 1<<10;
2225                         k_chip->nvm_sector_size = 1<<10;
2226                         /* autodetect 1 or 2 blocks */
2227                         k_chip->flash_support = FS_PROGRAM_LONGWORD;
2228                         k_chip->cache_type = KINETIS_CACHE_L;
2229                         k_chip->watchdog_type = KINETIS_WDOG_COP;
2230
2231                         cpu_mhz = 48;
2232                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2233                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX3:
2234                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX3:
2235                                 subfamid = 7;
2236                                 break;
2237
2238                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX8:
2239                                 cpu_mhz = 72;
2240                                 k_chip->pflash_sector_size = 2<<10;
2241                                 num_blocks = 2;
2242                                 k_chip->watchdog_type = KINETIS_WDOG32_KL28;
2243                                 k_chip->sysmodectrlr_type = KINETIS_SMC32;
2244                                 break;
2245                         }
2246
2247                         snprintf(name, sizeof(name), "MKL%u%uZ%%s%u",
2248                                  familyid, subfamid, cpu_mhz / 10);
2249                         break;
2250
2251                 case KINETIS_SDID_SERIESID_KW:
2252                         /* Newer KW-series (all KW series except KW2xD, KW01Z) */
2253                         cpu_mhz = 48;
2254                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2255                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX0:
2256                                 /* KW40Z */
2257                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2258                                 /* KW30Z */
2259                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX0:
2260                                 /* KW20Z */
2261                                 /* FTFA, 1kB sectors */
2262                                 k_chip->pflash_sector_size = 1<<10;
2263                                 k_chip->nvm_sector_size = 1<<10;
2264                                 /* autodetect 1 or 2 blocks */
2265                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2266                                 k_chip->cache_type = KINETIS_CACHE_L;
2267                                 k_chip->watchdog_type = KINETIS_WDOG_COP;
2268                                 break;
2269                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX1:
2270                                 /* KW41Z */
2271                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2272                                 /* KW31Z */
2273                         case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX1:
2274                                 /* KW21Z */
2275                                 /* FTFA, 2kB sectors */
2276                                 k_chip->pflash_sector_size = 2<<10;
2277                                 k_chip->nvm_sector_size = 2<<10;
2278                                 /* autodetect 1 or 2 blocks */
2279                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2280                                 k_chip->cache_type = KINETIS_CACHE_L;
2281                                 k_chip->watchdog_type = KINETIS_WDOG_COP;
2282                                 break;
2283                         default:
2284                                 LOG_ERROR("Unsupported KW FAMILYID SUBFAMID");
2285                         }
2286                         snprintf(name, sizeof(name), "MKW%u%uZ%%s%u",
2287                                          familyid, subfamid, cpu_mhz / 10);
2288                         break;
2289
2290                 case KINETIS_SDID_SERIESID_KV:
2291                         /* KV-series */
2292                         k_chip->watchdog_type = KINETIS_WDOG_K;
2293                         switch (k_chip->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
2294                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
2295                                 /* KV10: FTFA, 1kB sectors */
2296                                 k_chip->pflash_sector_size = 1<<10;
2297                                 num_blocks = 1;
2298                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2299                                 k_chip->cache_type = KINETIS_CACHE_L;
2300                                 strcpy(name, "MKV10Z%s7");
2301                                 break;
2302
2303                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
2304                                 /* KV11: FTFA, 2kB sectors */
2305                                 k_chip->pflash_sector_size = 2<<10;
2306                                 num_blocks = 1;
2307                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2308                                 k_chip->cache_type = KINETIS_CACHE_L;
2309                                 strcpy(name, "MKV11Z%s7");
2310                                 break;
2311
2312                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
2313                                 /* KV30: FTFA, 2kB sectors, 1 block */
2314                         case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
2315                                 /* KV31: FTFA, 2kB sectors, 2 blocks */
2316                                 k_chip->pflash_sector_size = 2<<10;
2317                                 /* autodetect 1 or 2 blocks */
2318                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2319                                 k_chip->cache_type = KINETIS_CACHE_K;
2320                                 break;
2321
2322                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
2323                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
2324                         case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
2325                                 /* KV4x: FTFA, 4kB sectors */
2326                                 k_chip->pflash_sector_size = 4<<10;
2327                                 num_blocks = 1;
2328                                 k_chip->flash_support = FS_PROGRAM_LONGWORD;
2329                                 k_chip->cache_type = KINETIS_CACHE_K;
2330                                 cpu_mhz = 168;
2331                                 break;
2332
2333                         case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX6:
2334                         case KINETIS_SDID_FAMILYID_K5X | KINETIS_SDID_SUBFAMID_KX8:
2335                                 /* KV5x: FTFE, 8kB sectors */
2336                                 k_chip->pflash_sector_size = 8<<10;
2337                                 k_chip->max_flash_prog_size = 1<<10;
2338                                 num_blocks = 1;
2339                                 maxaddr_shift = 14;
2340                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_WIDTH_256BIT | FS_ECC;
2341                                 k_chip->pflash_base = 0x10000000;
2342                                 k_chip->progr_accel_ram = 0x18000000;
2343                                 cpu_mhz = 240;
2344                                 break;
2345
2346                         default:
2347                                 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
2348                         }
2349
2350                         if (name[0] == '\0')
2351                                 snprintf(name, sizeof(name), "MKV%u%uF%%s%u",
2352                                          familyid, subfamid, cpu_mhz / 10);
2353                         break;
2354
2355                 case KINETIS_SDID_SERIESID_KE:
2356                         /* KE1x-series */
2357                         k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
2358                         switch (k_chip->sim_sdid &
2359                                 (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
2360                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
2361                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
2362                                 /* KE1xZ: FTFE, 2kB sectors */
2363                                 k_chip->pflash_sector_size = 2<<10;
2364                                 k_chip->nvm_sector_size = 2<<10;
2365                                 k_chip->max_flash_prog_size = 1<<9;
2366                                 num_blocks = 2;
2367                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2368                                 k_chip->cache_type = KINETIS_CACHE_L;
2369
2370                                 cpu_mhz = 72;
2371                                 snprintf(name, sizeof(name), "MKE%u%uZ%%s%u",
2372                                          familyid, subfamid, cpu_mhz / 10);
2373                                 break;
2374
2375                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
2376                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
2377                         case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
2378                                 /* KE1xF: FTFE, 4kB sectors */
2379                                 k_chip->pflash_sector_size = 4<<10;
2380                                 k_chip->nvm_sector_size = 2<<10;
2381                                 k_chip->max_flash_prog_size = 1<<10;
2382                                 num_blocks = 2;
2383                                 k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
2384                                 k_chip->cache_type = KINETIS_CACHE_MSCM;
2385
2386                                 cpu_mhz = 168;
2387                                 snprintf(name, sizeof(name), "MKE%u%uF%%s%u",
2388                                          familyid, subfamid, cpu_mhz / 10);
2389                                 break;
2390
2391                         default:
2392                                 LOG_ERROR("Unsupported KE FAMILYID SUBFAMID");
2393                         }
2394                         break;
2395
2396                 default:
2397                         LOG_ERROR("Unsupported K-series");
2398                 }
2399         }
2400
2401         if (k_chip->pflash_sector_size == 0) {
2402                 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
2403                 return ERROR_FLASH_OPER_UNSUPPORTED;
2404         }
2405
2406         result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
2407         if (result != ERROR_OK)
2408                 return result;
2409
2410         result = target_read_u32(target, k_chip->sim_base + SIM_FCFG2_OFFSET, &k_chip->sim_fcfg2);
2411         if (result != ERROR_OK)
2412                 return result;
2413
2414         LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, k_chip->sim_sdid,
2415                         k_chip->sim_fcfg1, k_chip->sim_fcfg2);
2416
2417         fcfg1_nvmsize = (uint8_t)((k_chip->sim_fcfg1 >> 28) & 0x0f);
2418         fcfg1_pfsize = (uint8_t)((k_chip->sim_fcfg1 >> 24) & 0x0f);
2419         fcfg1_eesize = (uint8_t)((k_chip->sim_fcfg1 >> 16) & 0x0f);
2420         fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2421
2422         fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2423         k_chip->fcfg2_maxaddr0_shifted = ((k_chip->sim_fcfg2 >> 24) & 0x7f) << maxaddr_shift;
2424         k_chip->fcfg2_maxaddr1_shifted = ((k_chip->sim_fcfg2 >> 16) & 0x7f) << maxaddr_shift;
2425
2426         if (num_blocks == 0)
2427                 num_blocks = k_chip->fcfg2_maxaddr1_shifted ? 2 : 1;
2428         else if (k_chip->fcfg2_maxaddr1_shifted == 0 && num_blocks >= 2 && fcfg2_pflsh) {
2429                 /* fcfg2_maxaddr1 may be zero due to partitioning whole NVM as EEPROM backup
2430                  * Do not adjust block count in this case! */
2431                 num_blocks = 1;
2432                 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
2433         } else if (k_chip->fcfg2_maxaddr1_shifted != 0 && num_blocks == 1) {
2434                 num_blocks = 2;
2435                 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
2436         }
2437
2438         /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
2439         if (!fcfg2_pflsh) {
2440                 switch (fcfg1_nvmsize) {
2441                 case 0x03:
2442                 case 0x05:
2443                 case 0x07:
2444                 case 0x09:
2445                 case 0x0b:
2446                         k_chip->nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
2447                         break;
2448                 case 0x0f:
2449                         if (k_chip->pflash_sector_size >= 4<<10)
2450                                 k_chip->nvm_size = 512<<10;
2451                         else
2452                                 /* K20_100 */
2453                                 k_chip->nvm_size = 256<<10;
2454                         break;
2455                 default:
2456                         k_chip->nvm_size = 0;
2457                         break;
2458                 }
2459
2460                 switch (fcfg1_eesize) {
2461                 case 0x00:
2462                 case 0x01:
2463                 case 0x02:
2464                 case 0x03:
2465                 case 0x04:
2466                 case 0x05:
2467                 case 0x06:
2468                 case 0x07:
2469                 case 0x08:
2470                 case 0x09:
2471                         ee_size = (16 << (10 - fcfg1_eesize));
2472                         break;
2473                 default:
2474                         ee_size = 0;
2475                         break;
2476                 }
2477
2478                 switch (fcfg1_depart) {
2479                 case 0x01:
2480                 case 0x02:
2481                 case 0x03:
2482                 case 0x04:
2483                 case 0x05:
2484                 case 0x06:
2485                         k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
2486                         break;
2487                 case 0x07:
2488                 case 0x08:
2489                         k_chip->dflash_size = 0;
2490                         break;
2491                 case 0x09:
2492                 case 0x0a:
2493                 case 0x0b:
2494                 case 0x0c:
2495                 case 0x0d:
2496                         k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
2497                         break;
2498                 default:
2499                         k_chip->dflash_size = k_chip->nvm_size;
2500                         break;
2501                 }
2502         }
2503
2504         switch (fcfg1_pfsize) {
2505         case 0x00:
2506                 k_chip->pflash_size = 8192;
2507                 break;
2508         case 0x01:
2509         case 0x03:
2510         case 0x05:
2511         case 0x07:
2512         case 0x09:
2513         case 0x0b:
2514         case 0x0d:
2515                 k_chip->pflash_size = 1 << (14 + (fcfg1_pfsize >> 1));
2516                 break;
2517         case 0x0f:
2518                 /* a peculiar case: Freescale states different sizes for 0xf
2519                  * KL03P24M48SF0RM      32 KB .... duplicate of code 0x3
2520                  * K02P64M100SFARM      128 KB ... duplicate of code 0x7
2521                  * K22P121M120SF8RM     256 KB ... duplicate of code 0x9
2522                  * K22P121M120SF7RM     512 KB ... duplicate of code 0xb
2523                  * K22P100M120SF5RM     1024 KB ... duplicate of code 0xd
2524                  * K26P169M180SF5RM     2048 KB ... the only unique value
2525                  * fcfg2_maxaddr0 seems to be the only clue to pflash_size
2526                  * Checking fcfg2_maxaddr0 in bank probe is pointless then
2527                  */
2528                 if (fcfg2_pflsh)
2529                         k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks;
2530                 else
2531                         k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
2532                 if (k_chip->pflash_size != 2048<<10)
2533                         LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
2534
2535                 break;
2536         default:
2537                 k_chip->pflash_size = 0;
2538                 break;
2539         }
2540
2541         if (k_chip->flash_support & FS_PROGRAM_SECTOR && k_chip->max_flash_prog_size == 0) {
2542                 k_chip->max_flash_prog_size = k_chip->pflash_sector_size;
2543                 /* Program section size is equal to sector size by default */
2544         }
2545
2546         if (fcfg2_pflsh) {
2547                 k_chip->num_pflash_blocks = num_blocks;
2548                 k_chip->num_nvm_blocks = 0;
2549         } else {
2550                 k_chip->num_pflash_blocks = (num_blocks + 1) / 2;
2551                 k_chip->num_nvm_blocks = num_blocks - k_chip->num_pflash_blocks;
2552         }
2553
2554         if (use_nvm_marking) {
2555                 nvm_marking[0] = k_chip->num_nvm_blocks ? 'X' : 'N';
2556                 nvm_marking[1] = '\0';
2557         } else
2558                 nvm_marking[0] = '\0';
2559
2560         pflash_size_k = k_chip->pflash_size / 1024;
2561         pflash_size_m = pflash_size_k / 1024;
2562         if (pflash_size_m)
2563                 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "M0xxx", nvm_marking, pflash_size_m);
2564         else
2565                 snprintf(flash_marking, sizeof(flash_marking), "%s%" PRIu32 "xxx", nvm_marking, pflash_size_k);
2566
2567         snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
2568         LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
2569         LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
2570         if (k_chip->num_nvm_blocks) {
2571                 nvm_size_k = k_chip->nvm_size / 1024;
2572                 dflash_size_k = k_chip->dflash_size / 1024;
2573                 LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
2574                          k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
2575         }
2576
2577         k_chip->probed = true;
2578
2579         if (create_banks)
2580                 kinetis_create_missing_banks(k_chip);
2581
2582         return ERROR_OK;
2583 }
2584
2585 static int kinetis_probe(struct flash_bank *bank)
2586 {
2587         int result, i;
2588         uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
2589         unsigned num_blocks, first_nvm_bank;
2590         uint32_t size_k;
2591         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2592         struct kinetis_chip *k_chip = k_bank->k_chip;
2593
2594         k_bank->probed = false;
2595
2596         if (!k_chip->probed) {
2597                 result = kinetis_probe_chip(k_chip);
2598                 if (result != ERROR_OK)
2599                         return result;
2600         }
2601
2602         num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2603         first_nvm_bank = k_chip->num_pflash_blocks;
2604
2605         if (k_bank->bank_number < k_chip->num_pflash_blocks) {
2606                 /* pflash, banks start at address zero */
2607                 k_bank->flash_class = FC_PFLASH;
2608                 bank->size = (k_chip->pflash_size / k_chip->num_pflash_blocks);
2609                 bank->base = k_chip->pflash_base + bank->size * k_bank->bank_number;
2610                 k_bank->prog_base = 0x00000000 + bank->size * k_bank->bank_number;
2611                 k_bank->sector_size = k_chip->pflash_sector_size;
2612                 /* pflash is divided into 32 protection areas for
2613                  * parts with more than 32K of PFlash. For parts with
2614                  * less the protection unit is set to 1024 bytes */
2615                 k_bank->protection_size = MAX(k_chip->pflash_size / 32, 1024);
2616                 bank->num_prot_blocks = bank->size / k_bank->protection_size;
2617                 k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
2618
2619                 size_k = bank->size / 1024;
2620                 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
2621                          k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2622
2623         } else if (k_bank->bank_number < num_blocks) {
2624                 /* nvm, banks start at address 0x10000000 */
2625                 unsigned nvm_ord = k_bank->bank_number - first_nvm_bank;
2626                 uint32_t limit;
2627
2628                 k_bank->flash_class = FC_FLEX_NVM;
2629                 bank->size = k_chip->nvm_size / k_chip->num_nvm_blocks;
2630                 bank->base = k_chip->nvm_base + bank->size * nvm_ord;
2631                 k_bank->prog_base = 0x00800000 + bank->size * nvm_ord;
2632                 k_bank->sector_size = k_chip->nvm_sector_size;
2633                 if (k_chip->dflash_size == 0) {
2634                         k_bank->protection_size = 0;
2635                 } else {
2636                         for (i = k_chip->dflash_size; ~i & 1; i >>= 1)
2637                                 ;
2638                         if (i == 1)
2639                                 k_bank->protection_size = k_chip->dflash_size / 8;      /* data flash size = 2^^n */
2640                         else
2641                                 k_bank->protection_size = k_chip->nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
2642                 }
2643                 bank->num_prot_blocks = 8 / k_chip->num_nvm_blocks;
2644                 k_bank->protection_block = bank->num_prot_blocks * nvm_ord;
2645
2646                 /* EEPROM backup part of FlexNVM is not accessible, use dflash_size as a limit */
2647                 if (k_chip->dflash_size > bank->size * nvm_ord)
2648                         limit = k_chip->dflash_size - bank->size * nvm_ord;
2649                 else
2650                         limit = 0;
2651
2652                 if (bank->size > limit) {
2653                         bank->size = limit;
2654                         LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
2655                                 k_bank->bank_number, limit);
2656                 }
2657
2658                 size_k = bank->size / 1024;
2659                 LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
2660                          k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
2661
2662         } else {
2663                 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
2664                                 k_bank->bank_number, num_blocks);
2665                 return ERROR_FLASH_BANK_INVALID;
2666         }
2667
2668         fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
2669         fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
2670         fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
2671
2672         if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
2673                 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
2674                                 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
2675
2676         if (fcfg2_pflsh) {
2677                 if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
2678                         LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
2679                                 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2680         } else {
2681                 if (k_bank->bank_number == first_nvm_bank
2682                                 && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
2683                         LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
2684                                 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
2685         }
2686
2687         if (bank->sectors) {
2688                 free(bank->sectors);
2689                 bank->sectors = NULL;
2690         }
2691         if (bank->prot_blocks) {
2692                 free(bank->prot_blocks);
2693                 bank->prot_blocks = NULL;
2694         }
2695
2696         if (k_bank->sector_size == 0) {
2697                 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
2698                 return ERROR_FLASH_BANK_INVALID;
2699         }
2700
2701         bank->num_sectors = bank->size / k_bank->sector_size;
2702
2703         if (bank->num_sectors > 0) {
2704                 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
2705                 bank->sectors = alloc_block_array(0, k_bank->sector_size, bank->num_sectors);
2706                 if (!bank->sectors)
2707                         return ERROR_FAIL;
2708
2709                 bank->prot_blocks = alloc_block_array(0, k_bank->protection_size, bank->num_prot_blocks);
2710                 if (!bank->prot_blocks)
2711                         return ERROR_FAIL;
2712
2713         } else {
2714                 bank->num_prot_blocks = 0;
2715         }
2716
2717         k_bank->probed = true;
2718
2719         return ERROR_OK;
2720 }
2721
2722 static int kinetis_auto_probe(struct flash_bank *bank)
2723 {
2724         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2725
2726         if (k_bank && k_bank->probed)
2727                 return ERROR_OK;
2728
2729         return kinetis_probe(bank);
2730 }
2731
2732 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2733 {
2734         const char *bank_class_names[] = {
2735                 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2736         };
2737
2738         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2739         struct kinetis_chip *k_chip = k_bank->k_chip;
2740         uint32_t size_k = bank->size / 1024;
2741
2742         snprintf(buf, buf_size,
2743                 "%s %s: %" PRIu32 "k %s bank %s at 0x%08" PRIx32,
2744                 bank->driver->name, k_chip->name,
2745                 size_k, bank_class_names[k_bank->flash_class],
2746                 bank->name, bank->base);
2747
2748         return ERROR_OK;
2749 }
2750
2751 static int kinetis_blank_check(struct flash_bank *bank)
2752 {
2753         struct kinetis_flash_bank *k_bank = bank->driver_priv;
2754         struct kinetis_chip *k_chip = k_bank->k_chip;
2755         int result;
2756
2757         /* suprisingly blank check does not work in VLPR and HSRUN modes */
2758         result = kinetis_check_run_mode(k_chip);
2759         if (result != ERROR_OK)
2760                 return result;
2761
2762         /* reset error flags */
2763         result = kinetis_ftfx_prepare(bank->target);
2764         if (result != ERROR_OK)
2765                 return result;
2766
2767         if (k_bank->flash_class == FC_PFLASH || k_bank->flash_class == FC_FLEX_NVM) {
2768                 bool block_dirty = true;
2769                 bool use_block_cmd = !(k_chip->flash_support & FS_NO_CMD_BLOCKSTAT);
2770                 uint8_t ftfx_fstat;
2771
2772                 if (use_block_cmd && k_bank->flash_class == FC_FLEX_NVM) {
2773                         uint8_t fcfg1_depart = (uint8_t)((k_chip->sim_fcfg1 >> 8) & 0x0f);
2774                         /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2775                         if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2776                                 use_block_cmd = false;
2777                 }
2778
2779                 if (use_block_cmd) {
2780                         /* check if whole bank is blank */
2781                         result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
2782                                                          0, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
2783
2784                         if (result != ERROR_OK)
2785                                 kinetis_ftfx_clear_error(bank->target);
2786                         else if ((ftfx_fstat & 0x01) == 0)
2787                                 block_dirty = false;
2788                 }
2789
2790                 if (block_dirty) {
2791                         /* the whole bank is not erased, check sector-by-sector */
2792                         int i;
2793                         for (i = 0; i < bank->num_sectors; i++) {
2794                                 /* normal margin */
2795                                 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2796                                                 k_bank->prog_base + bank->sectors[i].offset,
2797                                                 1, 0, 0, 0,  0, 0, 0, 0, &ftfx_fstat);
2798
2799                                 if (result == ERROR_OK) {
2800                                         bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2801                                 } else {
2802                                         LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2803                                         kinetis_ftfx_clear_error(bank->target);
2804                                         bank->sectors[i].is_erased = -1;
2805                                 }
2806                         }
2807                 } else {
2808                         /* the whole bank is erased, update all sectors */
2809                         int i;
2810                         for (i = 0; i < bank->num_sectors; i++)
2811                                 bank->sectors[i].is_erased = 1;
2812                 }
2813         } else {
2814                 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2815                 return ERROR_FLASH_OPERATION_FAILED;
2816         }
2817
2818         return ERROR_OK;
2819 }
2820
2821
2822 COMMAND_HANDLER(kinetis_nvm_partition)
2823 {
2824         int result;
2825         unsigned bank_idx;
2826         unsigned num_blocks, first_nvm_bank;
2827         unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2828         enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2829         bool enable;
2830         uint8_t load_flex_ram = 1;
2831         uint8_t ee_size_code = 0x3f;
2832         uint8_t flex_nvm_partition_code = 0;
2833         uint8_t ee_split = 3;
2834         struct target *target = get_current_target(CMD_CTX);
2835         struct kinetis_chip *k_chip;
2836         uint32_t sim_fcfg1;
2837
2838         k_chip = kinetis_get_chip(target);
2839
2840         if (CMD_ARGC >= 2) {
2841                 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2842                         sz_type = DF_SIZE;
2843                 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2844                         sz_type = EEBKP_SIZE;
2845
2846                 par = strtoul(CMD_ARGV[1], NULL, 10);
2847                 while (par >> (log2 + 3))
2848                         log2++;
2849         }
2850         switch (sz_type) {
2851         case SHOW_INFO:
2852                 if (k_chip == NULL) {
2853                         LOG_ERROR("Chip not probed.");
2854                         return ERROR_FAIL;
2855                 }
2856                 result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &sim_fcfg1);
2857                 if (result != ERROR_OK)
2858                         return result;
2859
2860                 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2861                 switch (flex_nvm_partition_code) {
2862                 case 0:
2863                         command_print(CMD_CTX, "No EEPROM backup, data flash only");
2864                         break;
2865                 case 1:
2866                 case 2:
2867                 case 3:
2868                 case 4:
2869                 case 5:
2870                 case 6:
2871                         command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2872                         break;
2873                 case 8:
2874                         command_print(CMD_CTX, "No data flash, EEPROM backup only");
2875                         break;
2876                 case 0x9:
2877                 case 0xA:
2878                 case 0xB:
2879                 case 0xC:
2880                 case 0xD:
2881                 case 0xE:
2882                         command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2883                         break;
2884                 case 0xf:
2885                         command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
2886                         break;
2887                 default:
2888                         command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2889                 }
2890                 return ERROR_OK;
2891
2892         case DF_SIZE:
2893                 flex_nvm_partition_code = 0x8 | log2;
2894                 break;
2895
2896         case EEBKP_SIZE:
2897                 flex_nvm_partition_code = log2;
2898                 break;
2899         }
2900
2901         if (CMD_ARGC == 3)
2902                 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2903         else if (CMD_ARGC >= 4) {
2904                 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2905                 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2906         }
2907
2908         enable = ee1 + ee2 > 0;
2909         if (enable) {
2910                 for (log2 = 2; ; log2++) {
2911                         if (ee1 + ee2 == (16u << 10) >> log2)
2912                                 break;
2913                         if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2914                                 LOG_ERROR("Unsupported EEPROM size");
2915                                 return ERROR_FLASH_OPERATION_FAILED;
2916                         }
2917                 }
2918
2919                 if (ee1 * 3 == ee2)
2920                         ee_split = 1;
2921                 else if (ee1 * 7 == ee2)
2922                         ee_split = 0;
2923                 else if (ee1 != ee2) {
2924                         LOG_ERROR("Unsupported EEPROM sizes ratio");
2925                         return ERROR_FLASH_OPERATION_FAILED;
2926                 }
2927
2928                 ee_size_code = log2 | ee_split << 4;
2929         }
2930
2931         if (CMD_ARGC >= 5)
2932                 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2933         if (enable)
2934                 load_flex_ram = 0;
2935
2936         LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2937                  flex_nvm_partition_code, ee_size_code);
2938
2939         result = kinetis_check_run_mode(k_chip);
2940         if (result != ERROR_OK)
2941                 return result;
2942
2943         /* reset error flags */
2944         result = kinetis_ftfx_prepare(target);
2945         if (result != ERROR_OK)
2946                 return result;
2947
2948         result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2949                                       ee_size_code, flex_nvm_partition_code, 0, 0,
2950                                       0, 0, 0, 0,  NULL);
2951         if (result != ERROR_OK)
2952                 return result;
2953
2954         command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
2955
2956         if (k_chip) {
2957                 first_nvm_bank = k_chip->num_pflash_blocks;
2958                 num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
2959                 for (bank_idx = first_nvm_bank; bank_idx < num_blocks; bank_idx++)
2960                         k_chip->banks[bank_idx].probed = false; /* re-probe before next use */
2961                 k_chip->probed = false;
2962         }
2963
2964         command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
2965         return ERROR_OK;
2966 }
2967
2968 COMMAND_HANDLER(kinetis_fcf_source_handler)
2969 {
2970         if (CMD_ARGC > 1)
2971                 return ERROR_COMMAND_SYNTAX_ERROR;
2972
2973         if (CMD_ARGC == 1) {
2974                 if (strcmp(CMD_ARGV[0], "write") == 0)
2975                         allow_fcf_writes = true;
2976                 else if (strcmp(CMD_ARGV[0], "protection") == 0)
2977                         allow_fcf_writes = false;
2978                 else
2979                         return ERROR_COMMAND_SYNTAX_ERROR;
2980         }
2981
2982         if (allow_fcf_writes) {
2983                 command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
2984                 command_print(CMD_CTX, "Protection info writes to FCF disabled.");
2985                 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
2986         } else {
2987                 command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
2988                 command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
2989         }
2990
2991         return ERROR_OK;
2992 }
2993
2994 COMMAND_HANDLER(kinetis_fopt_handler)
2995 {
2996         if (CMD_ARGC > 1)
2997                 return ERROR_COMMAND_SYNTAX_ERROR;
2998
2999         if (CMD_ARGC == 1) {
3000                 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
3001                 fcf_fopt_configured = true;
3002         } else {
3003                 command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
3004         }
3005
3006         return ERROR_OK;
3007 }
3008
3009 COMMAND_HANDLER(kinetis_create_banks_handler)
3010 {
3011         if (CMD_ARGC > 0)
3012                 return ERROR_COMMAND_SYNTAX_ERROR;
3013
3014         create_banks = true;
3015
3016         return ERROR_OK;
3017 }
3018
3019
3020 static const struct command_registration kinetis_security_command_handlers[] = {
3021         {
3022                 .name = "check_security",
3023                 .mode = COMMAND_EXEC,
3024                 .help = "Check status of device security lock",
3025                 .usage = "",
3026                 .handler = kinetis_check_flash_security_status,
3027         },
3028         {
3029                 .name = "halt",
3030                 .mode = COMMAND_EXEC,
3031                 .help = "Issue a halt via the MDM-AP",
3032                 .usage = "",
3033                 .handler = kinetis_mdm_halt,
3034         },
3035         {
3036                 .name = "mass_erase",
3037                 .mode = COMMAND_EXEC,
3038                 .help = "Issue a complete flash erase via the MDM-AP",
3039                 .usage = "",
3040                 .handler = kinetis_mdm_mass_erase,
3041         },
3042         {       .name = "reset",
3043                 .mode = COMMAND_EXEC,
3044                 .help = "Issue a reset via the MDM-AP",
3045                 .usage = "",
3046                 .handler = kinetis_mdm_reset,
3047         },
3048         COMMAND_REGISTRATION_DONE
3049 };
3050
3051 static const struct command_registration kinetis_exec_command_handlers[] = {
3052         {
3053                 .name = "mdm",
3054                 .mode = COMMAND_ANY,
3055                 .help = "MDM-AP command group",
3056                 .usage = "",
3057                 .chain = kinetis_security_command_handlers,
3058         },
3059         {
3060                 .name = "disable_wdog",
3061                 .mode = COMMAND_EXEC,
3062                 .help = "Disable the watchdog timer",
3063                 .usage = "",
3064                 .handler = kinetis_disable_wdog_handler,
3065         },
3066         {
3067                 .name = "nvm_partition",
3068                 .mode = COMMAND_EXEC,
3069                 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
3070                         " set two EEPROM sizes in bytes and FlexRAM loading during reset",
3071                 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
3072                 .handler = kinetis_nvm_partition,
3073         },
3074         {
3075                 .name = "fcf_source",
3076                 .mode = COMMAND_EXEC,
3077                 .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
3078                         " Mode 'protection' is safe from unwanted locking of the device.",
3079                 .usage = "['protection'|'write']",
3080                 .handler = kinetis_fcf_source_handler,
3081         },
3082         {
3083                 .name = "fopt",
3084                 .mode = COMMAND_EXEC,
3085                 .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
3086                 .usage = "[num]",
3087                 .handler = kinetis_fopt_handler,
3088         },
3089         {
3090                 .name = "create_banks",
3091                 .mode = COMMAND_CONFIG,
3092                 .help = "Driver creates additional banks if device with two/four flash blocks is probed",
3093                 .handler = kinetis_create_banks_handler,
3094         },
3095         COMMAND_REGISTRATION_DONE
3096 };
3097
3098 static const struct command_registration kinetis_command_handler[] = {
3099         {
3100                 .name = "kinetis",
3101                 .mode = COMMAND_ANY,
3102                 .help = "Kinetis flash controller commands",
3103                 .usage = "",
3104                 .chain = kinetis_exec_command_handlers,
3105         },
3106         COMMAND_REGISTRATION_DONE
3107 };
3108
3109
3110
3111 struct flash_driver kinetis_flash = {
3112         .name = "kinetis",
3113         .commands = kinetis_command_handler,
3114         .flash_bank_command = kinetis_flash_bank_command,
3115         .erase = kinetis_erase,
3116         .protect = kinetis_protect,
3117         .write = kinetis_write,
3118         .read = default_flash_read,
3119         .probe = kinetis_probe,
3120         .auto_probe = kinetis_auto_probe,
3121         .erase_check = kinetis_blank_check,
3122         .protect_check = kinetis_protect_check,
3123         .info = kinetis_info,
3124 };