git.sur5r.net Git - openocd/blob - src/flash/nor/mrvlqspi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com>                *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17
  18  /*
  19   * This is QSPI flash controller driver for Marvell's Wireless
  20   * Microcontroller platform.
  21   *
  22   * For more information please refer,
  23   * https://origin-www.marvell.com/microcontrollers/wi-fi-microcontroller-platform/
  24   */
  25
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "imp.h"
  31 #include "spi.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 #define QSPI_R_EN (0x0)
  37 #define QSPI_W_EN (0x1)
  38 #define QSPI_SS_DISABLE (0x0)
  39 #define QSPI_SS_ENABLE (0x1)
  40 #define WRITE_DISBALE (0x0)
  41 #define WRITE_ENABLE (0x1)
  42
  43 #define QSPI_TIMEOUT (1000)
  44 #define FIFO_FLUSH_TIMEOUT (1000)
  45 #define BLOCK_ERASE_TIMEOUT (1000)
  46 #define CHIP_ERASE_TIMEOUT (10000)
  47
  48 #define SS_EN (1 << 0)
  49 #define XFER_RDY (1 << 1)
  50 #define RFIFO_EMPTY (1 << 4)
  51 #define WFIFO_EMPTY (1 << 6)
  52 #define WFIFO_FULL (1 << 7)
  53 #define FIFO_FLUSH (1 << 9)
  54 #define RW_EN (1 << 13)
  55 #define XFER_STOP (1 << 14)
  56 #define XFER_START (1 << 15)
  57 #define CONF_MASK (0x7)
  58 #define CONF_OFFSET (10)
  59
  60 #define INS_WRITE_ENABLE 0x06
  61 #define INS_WRITE_DISABLE 0x04
  62 #define INS_READ_STATUS 0x05
  63 #define INS_PAGE_PROGRAM 0x02
  64
  65 #define CNTL 0x0 /* QSPI_BASE + 0x0 */
  66 #define CONF 0x4
  67 #define DOUT 0x8
  68 #define DIN 0xc
  69 #define INSTR 0x10
  70 #define ADDR 0x14
  71 #define RDMODE 0x18
  72 #define HDRCNT 0x1c
  73 #define DINCNT 0x20
  74
  75 struct mrvlqspi_flash_bank {
  76         int probed;
  77         uint32_t reg_base;
  78         uint32_t bank_num;
  79         const struct flash_device *dev;
  80 };
  81
  82 static inline uint32_t mrvlqspi_get_reg(struct flash_bank *bank, uint32_t reg)
  83 {
  84         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
  85         return reg + mrvlqspi_info->reg_base;
  86 }
  87
  88 static inline int mrvlqspi_set_din_cnt(struct flash_bank *bank, uint32_t count)
  89 {
  90         struct target *target = bank->target;
  91
  92         return target_write_u32(target, mrvlqspi_get_reg(bank, DINCNT), count);
  93 }
  94
  95 static inline int mrvlqspi_set_addr(struct flash_bank *bank, uint32_t addr)
  96 {
  97         struct target *target = bank->target;
  98
  99         return target_write_u32(target, mrvlqspi_get_reg(bank, ADDR), addr);
 100 }
 101
 102 static inline int mrvlqspi_set_instr(struct flash_bank *bank, uint32_t instr)
 103 {
 104         struct target *target = bank->target;
 105
 106         return target_write_u32(target, mrvlqspi_get_reg(bank, INSTR), instr);
 107 }
 108
 109 static inline int mrvlqspi_set_hdr_cnt(struct flash_bank *bank, uint32_t hdr_cnt)
 110 {
 111         struct target *target = bank->target;
 112
 113         return target_write_u32(target, mrvlqspi_get_reg(bank, HDRCNT), hdr_cnt);
 114 }
 115
 116 static int mrvlqspi_set_conf(struct flash_bank *bank, uint32_t conf_val)
 117 {
 118         int retval;
 119         uint32_t regval;
 120         struct target *target = bank->target;
 121
 122         retval = target_read_u32(target,
 123                         mrvlqspi_get_reg(bank, CONF), &regval);
 124         if (retval != ERROR_OK)
 125                 return retval;
 126
 127         regval &= ~(CONF_MASK << CONF_OFFSET);
 128         regval |= (conf_val << CONF_OFFSET);
 129
 130         return target_write_u32(target,
 131                         mrvlqspi_get_reg(bank, CONF), regval);
 132 }
 133
 134 static int mrvlqspi_set_ss_state(struct flash_bank *bank, bool state, int timeout)
 135 {
 136         int retval;
 137         uint32_t regval;
 138         struct target *target = bank->target;
 139
 140         retval = target_read_u32(target,
 141                         mrvlqspi_get_reg(bank, CNTL), &regval);
 142         if (retval != ERROR_OK)
 143                 return retval;
 144
 145         if (state)
 146                 regval |= SS_EN;
 147         else
 148                 regval &= ~(SS_EN);
 149
 150         retval = target_write_u32(target,
 151                         mrvlqspi_get_reg(bank, CNTL), regval);
 152         if (retval != ERROR_OK)
 153                 return retval;
 154
 155         /* wait for xfer_ready to set */
 156         for (;;) {
 157                 retval = target_read_u32(target,
 158                                 mrvlqspi_get_reg(bank, CNTL), &regval);
 159                 if (retval != ERROR_OK)
 160                         return retval;
 161                 LOG_DEBUG("status: 0x%08" PRIx32, regval);
 162                 if ((regval & XFER_RDY) == XFER_RDY)
 163                         break;
 164                 if (timeout-- <= 0) {
 165                         LOG_ERROR("timed out waiting for flash");
 166                         return ERROR_FAIL;
 167                 }
 168                 alive_sleep(1);
 169         }
 170         return ERROR_OK;
 171 }
 172
 173 static int mrvlqspi_start_transfer(struct flash_bank *bank, bool rw_mode)
 174 {
 175         int retval;
 176         uint32_t regval;
 177         struct target *target = bank->target;
 178
 179         retval = mrvlqspi_set_ss_state(bank, QSPI_SS_ENABLE, QSPI_TIMEOUT);
 180         if (retval != ERROR_OK)
 181                 return retval;
 182
 183         retval = target_read_u32(target,
 184                         mrvlqspi_get_reg(bank, CONF), &regval);
 185         if (retval != ERROR_OK)
 186                 return retval;
 187
 188         if (rw_mode)
 189                 regval |= RW_EN;
 190         else
 191                 regval &= ~(RW_EN);
 192
 193         regval |= XFER_START;
 194
 195         retval = target_write_u32(target,
 196                         mrvlqspi_get_reg(bank, CONF), regval);
 197         if (retval != ERROR_OK)
 198                 return retval;
 199
 200         return ERROR_OK;
 201 }
 202
 203 static int mrvlqspi_stop_transfer(struct flash_bank *bank)
 204 {
 205         int retval;
 206         uint32_t regval;
 207         struct target *target = bank->target;
 208         int timeout = QSPI_TIMEOUT;
 209
 210         /* wait for xfer_ready and wfifo_empty to set */
 211         for (;;) {
 212                 retval = target_read_u32(target,
 213                                 mrvlqspi_get_reg(bank, CNTL), &regval);
 214                 if (retval != ERROR_OK)
 215                         return retval;
 216                 LOG_DEBUG("status: 0x%08" PRIx32, regval);
 217                 if ((regval & (XFER_RDY | WFIFO_EMPTY)) ==
 218                                         (XFER_RDY | WFIFO_EMPTY))
 219                         break;
 220                 if (timeout-- <= 0) {
 221                         LOG_ERROR("timed out waiting for flash");
 222                         return ERROR_FAIL;
 223                 }
 224                 alive_sleep(1);
 225         }
 226
 227         retval = target_read_u32(target,
 228                         mrvlqspi_get_reg(bank, CONF), &regval);
 229         if (retval != ERROR_OK)
 230                 return retval;
 231
 232         regval |= XFER_STOP;
 233
 234         retval = target_write_u32(target,
 235                         mrvlqspi_get_reg(bank, CONF), regval);
 236         if (retval != ERROR_OK)
 237                 return retval;
 238
 239         /* wait for xfer_start to reset */
 240         for (;;) {
 241                 retval = target_read_u32(target,
 242                                 mrvlqspi_get_reg(bank, CONF), &regval);
 243                 if (retval != ERROR_OK)
 244                         return retval;
 245                 LOG_DEBUG("status: 0x%08" PRIx32, regval);
 246                 if ((regval & XFER_START) == 0)
 247                         break;
 248                 if (timeout-- <= 0) {
 249                         LOG_ERROR("timed out waiting for flash");
 250                         return ERROR_FAIL;
 251                 }
 252                 alive_sleep(1);
 253         }
 254
 255         retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
 256         if (retval != ERROR_OK)
 257                 return retval;
 258
 259         return ERROR_OK;
 260 }
 261
 262 static int mrvlqspi_fifo_flush(struct flash_bank *bank, int timeout)
 263 {
 264         int retval;
 265         uint32_t val;
 266         struct target *target = bank->target;
 267
 268         retval = target_read_u32(target,
 269                         mrvlqspi_get_reg(bank, CONF), &val);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         val |= FIFO_FLUSH;
 274
 275         retval = target_write_u32(target,
 276                         mrvlqspi_get_reg(bank, CONF), val);
 277         if (retval != ERROR_OK)
 278                 return retval;
 279
 280         /* wait for fifo_flush to clear */
 281         for (;;) {
 282                 retval = target_read_u32(target,
 283                                 mrvlqspi_get_reg(bank, CONF), &val);
 284                 if (retval != ERROR_OK)
 285                         return retval;
 286                 LOG_DEBUG("status: 0x%08" PRIX32, val);
 287                 if ((val & FIFO_FLUSH) == 0)
 288                         break;
 289                 if (timeout-- <= 0) {
 290                         LOG_ERROR("timed out waiting for flash");
 291                         return ERROR_FAIL;
 292                 }
 293                 alive_sleep(1);
 294         }
 295         return ERROR_OK;
 296 }
 297
 298 static int mrvlqspi_read_byte(struct flash_bank *bank, uint8_t *data)
 299 {
 300         int retval;
 301         uint32_t val;
 302         struct target *target = bank->target;
 303
 304         /* wait for rfifo_empty to reset */
 305         for (;;) {
 306                 retval = target_read_u32(target,
 307                                 mrvlqspi_get_reg(bank, CNTL), &val);
 308                 if (retval != ERROR_OK)
 309                         return retval;
 310                 LOG_DEBUG("status: 0x%08" PRIx32, val);
 311                 if ((val & RFIFO_EMPTY) == 0)
 312                         break;
 313                 usleep(10);
 314         }
 315
 316         retval = target_read_u32(target,
 317                         mrvlqspi_get_reg(bank, DIN), &val);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         *data = val & 0xFF;
 322
 323         return ERROR_OK;
 324 }
 325
 326 static int mrvlqspi_flash_busy_status(struct flash_bank *bank, int timeout)
 327 {
 328         uint8_t val;
 329         int retval;
 330
 331         /* Flush read/write fifo's */
 332         retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 333         if (retval != ERROR_OK)
 334                 return retval;
 335
 336         /* Set instruction/addr count value */
 337         retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
 338         if (retval != ERROR_OK)
 339                 return retval;
 340
 341         /* Read flash status register in continuous manner */
 342         retval = mrvlqspi_set_din_cnt(bank, 0x0);
 343         if (retval != ERROR_OK)
 344                 return retval;
 345
 346         /* Set instruction */
 347         retval = mrvlqspi_set_instr(bank, INS_READ_STATUS);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         /* Set data and addr pin length */
 352         retval = mrvlqspi_set_conf(bank, 0x0);
 353         if (retval != ERROR_OK)
 354                 return retval;
 355
 356         /* Enable read mode transfer */
 357         retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
 358         if (retval != ERROR_OK)
 359                 return retval;
 360
 361         for (;;) {
 362                 retval = mrvlqspi_read_byte(bank, &val);
 363                 if (retval != ERROR_OK)
 364                         return retval;
 365                 if (!(val & 0x1))
 366                         break;
 367                 if (timeout-- <= 0) {
 368                         LOG_ERROR("timed out waiting for flash");
 369                         return ERROR_FAIL;
 370                 }
 371                 alive_sleep(1);
 372         }
 373
 374         return mrvlqspi_stop_transfer(bank);
 375 }
 376
 377 static int mrvlqspi_set_write_status(struct flash_bank *bank, bool mode)
 378 {
 379         int retval;
 380         uint32_t instr;
 381
 382         /* Flush read/write fifo's */
 383         retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 384         if (retval != ERROR_OK)
 385                 return retval;
 386
 387         /* Set instruction/addr count value */
 388         retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
 389         if (retval != ERROR_OK)
 390                 return retval;
 391
 392         if (mode)
 393                 instr = INS_WRITE_ENABLE;
 394         else
 395                 instr = INS_WRITE_DISABLE;
 396
 397         /* Set instruction */
 398         retval = mrvlqspi_set_instr(bank, instr);
 399         if (retval != ERROR_OK)
 400                 return retval;
 401
 402         retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
 403         if (retval != ERROR_OK)
 404                 return retval;
 405
 406         retval = mrvlqspi_stop_transfer(bank);
 407         if (retval != ERROR_OK)
 408                 return retval;
 409
 410         return retval;
 411 }
 412
 413 static int mrvlqspi_read_id(struct flash_bank *bank, uint32_t *id)
 414 {
 415         uint8_t id_buf[3] = {0, 0, 0};
 416         int retval, i;
 417
 418         LOG_DEBUG("Getting ID");
 419
 420         /* Flush read/write fifo's */
 421         retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 422         if (retval != ERROR_OK)
 423                 return retval;
 424
 425         /* Set instruction/addr count value */
 426         retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
 427         if (retval != ERROR_OK)
 428                 return retval;
 429
 430         /* Set count for number of bytes to read */
 431         retval = mrvlqspi_set_din_cnt(bank, 0x3);
 432         if (retval != ERROR_OK)
 433                 return retval;
 434
 435         /* Set instruction */
 436         retval = mrvlqspi_set_instr(bank, SPIFLASH_READ_ID);
 437         if (retval != ERROR_OK)
 438                 return retval;
 439
 440         /* Set data and addr pin length */
 441         retval = mrvlqspi_set_conf(bank, 0x0);
 442         if (retval != ERROR_OK)
 443                 return retval;
 444
 445         retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
 446         if (retval != ERROR_OK)
 447                 return retval;
 448
 449         for (i = 0; i < 3; i++) {
 450                 retval = mrvlqspi_read_byte(bank, &id_buf[i]);
 451                 if (retval != ERROR_OK)
 452                         return retval;
 453         }
 454
 455         LOG_DEBUG("ID is 0x%02" PRIx8 " 0x%02" PRIx8 " 0x%02" PRIx8,
 456                                         id_buf[0], id_buf[1], id_buf[2]);
 457         retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
 458         if (retval != ERROR_OK)
 459                 return retval;
 460
 461         *id = id_buf[2] << 16 | id_buf[1] << 8 | id_buf[0];
 462         return ERROR_OK;
 463 }
 464
 465 static int mrvlqspi_block_erase(struct flash_bank *bank, uint32_t offset)
 466 {
 467         int retval;
 468         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 469
 470         /* Set flash write enable */
 471         retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
 472         if (retval != ERROR_OK)
 473                 return retval;
 474
 475         /* Set instruction/addr count value */
 476         retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
 477         if (retval != ERROR_OK)
 478                 return retval;
 479
 480         /* Set read offset address */
 481         retval = mrvlqspi_set_addr(bank, offset);
 482         if (retval != ERROR_OK)
 483                 return retval;
 484
 485         /* Set instruction */
 486         retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->erase_cmd);
 487         if (retval != ERROR_OK)
 488                 return retval;
 489
 490         retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
 491         if (retval != ERROR_OK)
 492                 return retval;
 493
 494         retval = mrvlqspi_stop_transfer(bank);
 495         if (retval != ERROR_OK)
 496                 return retval;
 497
 498         return mrvlqspi_flash_busy_status(bank, BLOCK_ERASE_TIMEOUT);
 499 }
 500
 501 static int mrvlqspi_bulk_erase(struct flash_bank *bank)
 502 {
 503         int retval;
 504         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 505
 506         /* Set flash write enable */
 507         retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
 508         if (retval != ERROR_OK)
 509                 return retval;
 510
 511         /* Set instruction */
 512         retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->chip_erase_cmd);
 513         if (retval != ERROR_OK)
 514                 return retval;
 515
 516         retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
 517         if (retval != ERROR_OK)
 518                 return retval;
 519
 520         retval = mrvlqspi_stop_transfer(bank);
 521         if (retval != ERROR_OK)
 522                 return retval;
 523
 524         return mrvlqspi_flash_busy_status(bank, CHIP_ERASE_TIMEOUT);
 525 }
 526
 527 static int mrvlqspi_flash_erase(struct flash_bank *bank, int first, int last)
 528 {
 529         struct target *target = bank->target;
 530         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 531         int retval = ERROR_OK;
 532         int sector;
 533
 534         LOG_DEBUG("erase from sector %d to sector %d", first, last);
 535
 536         if (target->state != TARGET_HALTED) {
 537                 LOG_ERROR("Target not halted");
 538                 return ERROR_TARGET_NOT_HALTED;
 539         }
 540
 541         if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
 542                 LOG_ERROR("Flash sector invalid");
 543                 return ERROR_FLASH_SECTOR_INVALID;
 544         }
 545
 546         if (!(mrvlqspi_info->probed)) {
 547                 LOG_ERROR("Flash bank not probed");
 548                 return ERROR_FLASH_BANK_NOT_PROBED;
 549         }
 550
 551         for (sector = first; sector <= last; sector++) {
 552                 if (bank->sectors[sector].is_protected) {
 553                         LOG_ERROR("Flash sector %d protected", sector);
 554                         return ERROR_FAIL;
 555                 }
 556         }
 557
 558         /* If we're erasing the entire chip and the flash supports
 559          * it, use a bulk erase instead of going sector-by-sector. */
 560         if (first == 0 && last == (bank->num_sectors - 1)
 561                 && mrvlqspi_info->dev->chip_erase_cmd !=
 562                                         mrvlqspi_info->dev->erase_cmd) {
 563                 LOG_DEBUG("Chip supports the bulk erase command."\
 564                 " Will use bulk erase instead of sector-by-sector erase.");
 565                 retval = mrvlqspi_bulk_erase(bank);
 566                 if (retval == ERROR_OK) {
 567                         return retval;
 568                 } else
 569                         LOG_WARNING("Bulk flash erase failed."
 570                                 " Falling back to sector-by-sector erase.");
 571         }
 572
 573         for (sector = first; sector <= last; sector++) {
 574                 retval = mrvlqspi_block_erase(bank,
 575                                 sector * mrvlqspi_info->dev->sectorsize);
 576                 if (retval != ERROR_OK)
 577                         return retval;
 578         }
 579
 580         return retval;
 581 }
 582
 583 static int mrvlqspi_flash_write(struct flash_bank *bank, const uint8_t *buffer,
 584         uint32_t offset, uint32_t count)
 585 {
 586         struct target *target = bank->target;
 587         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 588         int retval = ERROR_OK;
 589         uint32_t page_size, fifo_size;
 590         struct working_area *fifo;
 591         struct reg_param reg_params[6];
 592         struct armv7m_algorithm armv7m_info;
 593         struct working_area *write_algorithm;
 594         int sector;
 595
 596         LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 597                 offset, count);
 598
 599         if (target->state != TARGET_HALTED) {
 600                 LOG_ERROR("Target not halted");
 601                 return ERROR_TARGET_NOT_HALTED;
 602         }
 603
 604         if (offset + count > mrvlqspi_info->dev->size_in_bytes) {
 605                 LOG_WARNING("Writes past end of flash. Extra data discarded.");
 606                 count = mrvlqspi_info->dev->size_in_bytes - offset;
 607         }
 608
 609         /* Check sector protection */
 610         for (sector = 0; sector < bank->num_sectors; sector++) {
 611                 /* Start offset in or before this sector? */
 612                 /* End offset in or behind this sector? */
 613                 if ((offset <
 614                         (bank->sectors[sector].offset + bank->sectors[sector].size))
 615                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 616                         && bank->sectors[sector].is_protected) {
 617                         LOG_ERROR("Flash sector %d protected", sector);
 618                         return ERROR_FAIL;
 619                 }
 620         }
 621
 622         page_size = mrvlqspi_info->dev->pagesize;
 623
 624         /* See contrib/loaders/flash/mrvlqspi.S for src */
 625         static const uint8_t mrvlqspi_flash_write_code[] = {
 626                 0x4f, 0xf0, 0x00, 0x0a, 0xa2, 0x44, 0x92, 0x45,
 627                 0x7f, 0xf6, 0xfc, 0xaf, 0x00, 0xf0, 0x6b, 0xf8,
 628                 0x5f, 0xf0, 0x01, 0x08, 0xc5, 0xf8, 0x1c, 0x80,
 629                 0x5f, 0xf0, 0x06, 0x08, 0xc5, 0xf8, 0x10, 0x80,
 630                 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0, 0x6b, 0xf8,
 631                 0x00, 0xf0, 0x7d, 0xf8, 0x5f, 0xf0, 0x31, 0x08,
 632                 0xc5, 0xf8, 0x1c, 0x80, 0x90, 0x46, 0xc5, 0xf8,
 633                 0x14, 0x80, 0x5f, 0xf0, 0x02, 0x08, 0xc5, 0xf8,
 634                 0x10, 0x80, 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0,
 635                 0x5a, 0xf8, 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1,
 636                 0x00, 0x0f, 0x00, 0xf0, 0x8b, 0x80, 0x47, 0x68,
 637                 0x47, 0x45, 0x3f, 0xf4, 0xf6, 0xaf, 0x17, 0xf8,
 638                 0x01, 0x9b, 0x00, 0xf0, 0x30, 0xf8, 0x8f, 0x42,
 639                 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x07, 0x47, 0x60,
 640                 0x01, 0x3b, 0x00, 0x2b, 0x00, 0xf0, 0x05, 0x80,
 641                 0x02, 0xf1, 0x01, 0x02, 0x92, 0x45, 0x7f, 0xf4,
 642                 0xe4, 0xaf, 0x00, 0xf0, 0x50, 0xf8, 0xa2, 0x44,
 643                 0x00, 0xf0, 0x2d, 0xf8, 0x5f, 0xf0, 0x01, 0x08,
 644                 0xc5, 0xf8, 0x1c, 0x80, 0x5f, 0xf0, 0x00, 0x08,
 645                 0xc5, 0xf8, 0x20, 0x80, 0x5f, 0xf0, 0x05, 0x08,
 646                 0xc5, 0xf8, 0x10, 0x80, 0x5f, 0xf0, 0x00, 0x09,
 647                 0x00, 0xf0, 0x29, 0xf8, 0x00, 0xf0, 0x13, 0xf8,
 648                 0x09, 0xf0, 0x01, 0x09, 0xb9, 0xf1, 0x00, 0x0f,
 649                 0xf8, 0xd1, 0x00, 0xf0, 0x34, 0xf8, 0x00, 0x2b,
 650                 0xa4, 0xd1, 0x00, 0xf0, 0x53, 0xb8, 0xd5, 0xf8,
 651                 0x00, 0x80, 0x5f, 0xea, 0x08, 0x68, 0xfa, 0xd4,
 652                 0xc5, 0xf8, 0x08, 0x90, 0x70, 0x47, 0xd5, 0xf8,
 653                 0x00, 0x80, 0x5f, 0xea, 0xc8, 0x68, 0xfa, 0xd4,
 654                 0xd5, 0xf8, 0x0c, 0x90, 0x70, 0x47, 0xd5, 0xf8,
 655                 0x04, 0x80, 0x48, 0xf4, 0x00, 0x78, 0xc5, 0xf8,
 656                 0x04, 0x80, 0xd5, 0xf8, 0x04, 0x80, 0x5f, 0xea,
 657                 0x88, 0x58, 0xfa, 0xd4, 0x70, 0x47, 0xd5, 0xf8,
 658                 0x00, 0x80, 0x48, 0xf0, 0x01, 0x08, 0xc5, 0xf8,
 659                 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea,
 660                 0x88, 0x78, 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80,
 661                 0x69, 0xf3, 0x4d, 0x38, 0x48, 0xf4, 0x00, 0x48,
 662                 0xc5, 0xf8, 0x04, 0x80, 0x70, 0x47, 0xd5, 0xf8,
 663                 0x00, 0x80, 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5,
 664                 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea, 0x48, 0x68,
 665                 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80, 0x48, 0xf4,
 666                 0x80, 0x48, 0xc5, 0xf8, 0x04, 0x80, 0xd5, 0xf8,
 667                 0x04, 0x80, 0x5f, 0xea, 0x08, 0x48, 0xfa, 0xd4,
 668                 0xd5, 0xf8, 0x00, 0x80, 0x28, 0xf0, 0x01, 0x08,
 669                 0xc5, 0xf8, 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80,
 670                 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5, 0x70, 0x47,
 671                 0x00, 0x20, 0x50, 0x60, 0x30, 0x46, 0x00, 0xbe
 672         };
 673
 674         if (target_alloc_working_area(target, sizeof(mrvlqspi_flash_write_code),
 675                         &write_algorithm) != ERROR_OK) {
 676                 LOG_ERROR("Insufficient working area. You must configure"\
 677                         " a working area > %zdB in order to write to SPIFI flash.",
 678                         sizeof(mrvlqspi_flash_write_code));
 679                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 680         }
 681
 682         retval = target_write_buffer(target, write_algorithm->address,
 683                         sizeof(mrvlqspi_flash_write_code),
 684                         mrvlqspi_flash_write_code);
 685         if (retval != ERROR_OK) {
 686                 target_free_working_area(target, write_algorithm);
 687                 return retval;
 688         }
 689
 690         /* FIFO allocation */
 691         fifo_size = target_get_working_area_avail(target);
 692
 693         if (fifo_size == 0) {
 694                 /* if we already allocated the writing code but failed to get fifo
 695                  * space, free the algorithm */
 696                 target_free_working_area(target, write_algorithm);
 697
 698                 LOG_ERROR("Insufficient working area. Please allocate at least"\
 699                         " %zdB of working area to enable flash writes.",
 700                         sizeof(mrvlqspi_flash_write_code) + 1
 701                 );
 702
 703                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 704         } else if (fifo_size < page_size)
 705                 LOG_WARNING("Working area size is limited; flash writes may be"\
 706                         " slow. Increase working area size to at least %zdB"\
 707                         " to reduce write times.",
 708                         (size_t)(sizeof(mrvlqspi_flash_write_code) + page_size)
 709                 );
 710
 711         if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
 712                 target_free_working_area(target, write_algorithm);
 713                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 714         }
 715
 716         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 717         armv7m_info.core_mode = ARM_MODE_THREAD;
 718
 719         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
 720         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
 721         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
 722         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (halfword-16bit) */
 723         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* page size */
 724         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);    /* qspi base address */
 725
 726         buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
 727         buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
 728         buf_set_u32(reg_params[2].value, 0, 32, offset);
 729         buf_set_u32(reg_params[3].value, 0, 32, count);
 730         buf_set_u32(reg_params[4].value, 0, 32, page_size);
 731         buf_set_u32(reg_params[5].value, 0, 32, (uint32_t) mrvlqspi_info->reg_base);
 732
 733         retval = target_run_flash_async_algorithm(target, buffer, count, 1,
 734                         0, NULL,
 735                         6, reg_params,
 736                         fifo->address, fifo->size,
 737                         write_algorithm->address, 0,
 738                         &armv7m_info
 739         );
 740
 741         if (retval != ERROR_OK)
 742                 LOG_ERROR("Error executing flash write algorithm");
 743
 744         target_free_working_area(target, fifo);
 745         target_free_working_area(target, write_algorithm);
 746
 747         destroy_reg_param(&reg_params[0]);
 748         destroy_reg_param(&reg_params[1]);
 749         destroy_reg_param(&reg_params[2]);
 750         destroy_reg_param(&reg_params[3]);
 751         destroy_reg_param(&reg_params[4]);
 752         destroy_reg_param(&reg_params[5]);
 753
 754         return retval;
 755 }
 756
 757 int mrvlqspi_flash_read(struct flash_bank *bank, uint8_t *buffer,
 758                                 uint32_t offset, uint32_t count)
 759 {
 760         struct target *target = bank->target;
 761         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 762         int retval;
 763         uint32_t i;
 764
 765         if (target->state != TARGET_HALTED) {
 766                 LOG_ERROR("Target not halted");
 767                 return ERROR_TARGET_NOT_HALTED;
 768         }
 769
 770         if (!(mrvlqspi_info->probed)) {
 771                 LOG_ERROR("Flash bank not probed");
 772                 return ERROR_FLASH_BANK_NOT_PROBED;
 773         }
 774
 775         /* Flush read/write fifo's */
 776         retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 777         if (retval != ERROR_OK)
 778                 return retval;
 779
 780         /* Set instruction/addr count value */
 781         retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
 782         if (retval != ERROR_OK)
 783                 return retval;
 784
 785         /* Set count for number of bytes to read */
 786         retval = mrvlqspi_set_din_cnt(bank, count);
 787         if (retval != ERROR_OK)
 788                 return retval;
 789
 790         /* Set read address */
 791         retval = mrvlqspi_set_addr(bank, offset);
 792         if (retval != ERROR_OK)
 793                 return retval;
 794
 795         /* Set instruction */
 796         retval = mrvlqspi_set_instr(bank, SPIFLASH_READ);
 797         if (retval != ERROR_OK)
 798                 return retval;
 799
 800         /* Set data and addr pin length */
 801         retval = mrvlqspi_set_conf(bank, 0x0);
 802         if (retval != ERROR_OK)
 803                 return retval;
 804
 805         retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
 806         if (retval != ERROR_OK)
 807                 return retval;
 808
 809         for (i = 0; i < count; i++) {
 810                 retval = mrvlqspi_read_byte(bank, &buffer[i]);
 811                 if (retval != ERROR_OK)
 812                         return retval;
 813         }
 814
 815         retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
 816         if (retval != ERROR_OK)
 817                 return retval;
 818
 819         return ERROR_OK;
 820 }
 821
 822 static int mrvlqspi_probe(struct flash_bank *bank)
 823 {
 824         struct target *target = bank->target;
 825         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 826         uint32_t id = 0;
 827         int retval;
 828         struct flash_sector *sectors;
 829
 830         /* If we've already probed, we should be fine to skip this time. */
 831         if (mrvlqspi_info->probed)
 832                 return ERROR_OK;
 833
 834         if (target->state != TARGET_HALTED) {
 835                 LOG_ERROR("Target not halted");
 836                 return ERROR_TARGET_NOT_HALTED;
 837         }
 838
 839         mrvlqspi_info->probed = 0;
 840         mrvlqspi_info->bank_num = bank->bank_number;
 841
 842         /* Read flash JEDEC ID */
 843         retval = mrvlqspi_read_id(bank, &id);
 844         if (retval != ERROR_OK)
 845                 return retval;
 846
 847         mrvlqspi_info->dev = NULL;
 848         for (const struct flash_device *p = flash_devices; p->name ; p++)
 849                 if (p->device_id == id) {
 850                         mrvlqspi_info->dev = p;
 851                         break;
 852                 }
 853
 854         if (!mrvlqspi_info->dev) {
 855                 LOG_ERROR("Unknown flash device ID 0x%08" PRIx32, id);
 856                 return ERROR_FAIL;
 857         }
 858
 859         LOG_INFO("Found flash device \'%s\' ID 0x%08" PRIx32,
 860                 mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
 861
 862         /* Set correct size value */
 863         bank->size = mrvlqspi_info->dev->size_in_bytes;
 864
 865         /* create and fill sectors array */
 866         bank->num_sectors = mrvlqspi_info->dev->size_in_bytes /
 867                                         mrvlqspi_info->dev->sectorsize;
 868         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 869         if (sectors == NULL) {
 870                 LOG_ERROR("not enough memory");
 871                 return ERROR_FAIL;
 872         }
 873
 874         for (int sector = 0; sector < bank->num_sectors; sector++) {
 875                 sectors[sector].offset =
 876                                 sector * mrvlqspi_info->dev->sectorsize;
 877                 sectors[sector].size = mrvlqspi_info->dev->sectorsize;
 878                 sectors[sector].is_erased = -1;
 879                 sectors[sector].is_protected = 0;
 880         }
 881
 882         bank->sectors = sectors;
 883         mrvlqspi_info->probed = 1;
 884
 885         return ERROR_OK;
 886 }
 887
 888 static int mrvlqspi_auto_probe(struct flash_bank *bank)
 889 {
 890         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 891         if (mrvlqspi_info->probed)
 892                 return ERROR_OK;
 893         return mrvlqspi_probe(bank);
 894 }
 895
 896 static int mrvlqspi_flash_erase_check(struct flash_bank *bank)
 897 {
 898         /* Not implemented yet */
 899         return ERROR_OK;
 900 }
 901
 902 static int mrvlqspi_protect_check(struct flash_bank *bank)
 903 {
 904         /* Not implemented yet */
 905         return ERROR_OK;
 906 }
 907
 908 int mrvlqspi_get_info(struct flash_bank *bank, char *buf, int buf_size)
 909 {
 910         struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
 911
 912         if (!(mrvlqspi_info->probed)) {
 913                 snprintf(buf, buf_size,
 914                         "\nQSPI flash bank not probed yet\n");
 915                 return ERROR_OK;
 916         }
 917
 918         snprintf(buf, buf_size, "\nQSPI flash information:\n"
 919                 "  Device \'%s\' ID 0x%08" PRIx32 "\n",
 920                 mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
 921
 922         return ERROR_OK;
 923 }
 924
 925 FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
 926 {
 927         struct mrvlqspi_flash_bank *mrvlqspi_info;
 928
 929         if (CMD_ARGC < 7)
 930                 return ERROR_COMMAND_SYNTAX_ERROR;
 931
 932         mrvlqspi_info = malloc(sizeof(struct mrvlqspi_flash_bank));
 933         if (mrvlqspi_info == NULL) {
 934                 LOG_ERROR("not enough memory");
 935                 return ERROR_FAIL;
 936         }
 937
 938         /* Get QSPI controller register map base address */
 939         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], mrvlqspi_info->reg_base);
 940         bank->driver_priv = mrvlqspi_info;
 941         mrvlqspi_info->probed = 0;
 942
 943         return ERROR_OK;
 944 }
 945
 946 struct flash_driver mrvlqspi_flash = {
 947         .name = "mrvlqspi",
 948         .flash_bank_command = mrvlqspi_flash_bank_command,
 949         .erase = mrvlqspi_flash_erase,
 950         .protect = NULL,
 951         .write = mrvlqspi_flash_write,
 952         .read = mrvlqspi_flash_read,
 953         .probe = mrvlqspi_probe,
 954         .auto_probe = mrvlqspi_auto_probe,
 955         .erase_check = mrvlqspi_flash_erase_check,
 956         .protect_check = mrvlqspi_protect_check,
 957         .info = mrvlqspi_get_info,
 958 };