git.sur5r.net Git - openocd/blob - src/flash/nor/stm32f1x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 /* stm32x register locations */
  37
  38 #define FLASH_REG_BASE_B0 0x40022000
  39 #define FLASH_REG_BASE_B1 0x40022040
  40
  41 #define STM32_FLASH_ACR     0x00
  42 #define STM32_FLASH_KEYR    0x04
  43 #define STM32_FLASH_OPTKEYR 0x08
  44 #define STM32_FLASH_SR      0x0C
  45 #define STM32_FLASH_CR      0x10
  46 #define STM32_FLASH_AR      0x14
  47 #define STM32_FLASH_OBR     0x1C
  48 #define STM32_FLASH_WRPR    0x20
  49
  50 /* TODO: Check if code using these really should be hard coded to bank 0.
  51  * There are valid cases, on dual flash devices the protection of the
  52  * second bank is done on the bank0 reg's. */
  53 #define STM32_FLASH_ACR_B0     0x40022000
  54 #define STM32_FLASH_KEYR_B0    0x40022004
  55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  56 #define STM32_FLASH_SR_B0      0x4002200C
  57 #define STM32_FLASH_CR_B0      0x40022010
  58 #define STM32_FLASH_AR_B0      0x40022014
  59 #define STM32_FLASH_OBR_B0     0x4002201C
  60 #define STM32_FLASH_WRPR_B0    0x40022020
  61
  62 /* option byte location */
  63
  64 #define STM32_OB_RDP            0x1FFFF800
  65 #define STM32_OB_USER           0x1FFFF802
  66 #define STM32_OB_DATA0          0x1FFFF804
  67 #define STM32_OB_DATA1          0x1FFFF806
  68 #define STM32_OB_WRP0           0x1FFFF808
  69 #define STM32_OB_WRP1           0x1FFFF80A
  70 #define STM32_OB_WRP2           0x1FFFF80C
  71 #define STM32_OB_WRP3           0x1FFFF80E
  72
  73 /* FLASH_CR register bits */
  74
  75 #define FLASH_PG                (1 << 0)
  76 #define FLASH_PER               (1 << 1)
  77 #define FLASH_MER               (1 << 2)
  78 #define FLASH_OPTPG             (1 << 4)
  79 #define FLASH_OPTER             (1 << 5)
  80 #define FLASH_STRT              (1 << 6)
  81 #define FLASH_LOCK              (1 << 7)
  82 #define FLASH_OPTWRE    (1 << 9)
  83
  84 /* FLASH_SR register bits */
  85
  86 #define FLASH_BSY               (1 << 0)
  87 #define FLASH_PGERR             (1 << 2)
  88 #define FLASH_WRPRTERR  (1 << 4)
  89 #define FLASH_EOP               (1 << 5)
  90
  91 /* STM32_FLASH_OBR bit definitions (reading) */
  92
  93 #define OPT_ERROR               0
  94 #define OPT_READOUT             1
  95 #define OPT_RDWDGSW             2
  96 #define OPT_RDRSTSTOP   3
  97 #define OPT_RDRSTSTDBY  4
  98 #define OPT_BFB2                5       /* dual flash bank only */
  99
 100 /* register unlock keys */
 101
 102 #define KEY1                    0x45670123
 103 #define KEY2                    0xCDEF89AB
 104
 105 struct stm32x_options {
 106         uint16_t RDP;
 107         uint16_t user_options;
 108         uint16_t protection[4];
 109 };
 110
 111 struct stm32x_flash_bank {
 112         struct stm32x_options option_bytes;
 113         struct working_area *write_algorithm;
 114         int ppage_size;
 115         int probed;
 116
 117         bool has_dual_banks;
 118         /* used to access dual flash bank stm32xl */
 119         uint32_t register_base;
 120 };
 121
 122 static int stm32x_mass_erase(struct flash_bank *bank);
 123 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 124
 125 /* flash bank stm32x <base> <size> 0 0 <target#>
 126  */
 127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 128 {
 129         struct stm32x_flash_bank *stm32x_info;
 130
 131         if (CMD_ARGC < 6)
 132                 return ERROR_COMMAND_SYNTAX_ERROR;
 133
 134         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 135
 136         bank->driver_priv = stm32x_info;
 137         stm32x_info->write_algorithm = NULL;
 138         stm32x_info->probed = 0;
 139         stm32x_info->has_dual_banks = false;
 140         stm32x_info->register_base = FLASH_REG_BASE_B0;
 141
 142         return ERROR_OK;
 143 }
 144
 145 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 146 {
 147         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 148         return reg + stm32x_info->register_base;
 149 }
 150
 151 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 152 {
 153         struct target *target = bank->target;
 154         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 155 }
 156
 157 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 158 {
 159         struct target *target = bank->target;
 160         uint32_t status;
 161         int retval = ERROR_OK;
 162
 163         /* wait for busy to clear */
 164         for (;;) {
 165                 retval = stm32x_get_flash_status(bank, &status);
 166                 if (retval != ERROR_OK)
 167                         return retval;
 168                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 169                 if ((status & FLASH_BSY) == 0)
 170                         break;
 171                 if (timeout-- <= 0) {
 172                         LOG_ERROR("timed out waiting for flash");
 173                         return ERROR_FAIL;
 174                 }
 175                 alive_sleep(1);
 176         }
 177
 178         if (status & FLASH_WRPRTERR) {
 179                 LOG_ERROR("stm32x device protected");
 180                 retval = ERROR_FAIL;
 181         }
 182
 183         if (status & FLASH_PGERR) {
 184                 LOG_ERROR("stm32x device programming failed");
 185                 retval = ERROR_FAIL;
 186         }
 187
 188         /* Clear but report errors */
 189         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 190                 /* If this operation fails, we ignore it and report the original
 191                  * retval
 192                  */
 193                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 194                                 FLASH_WRPRTERR | FLASH_PGERR);
 195         }
 196         return retval;
 197 }
 198
 199 int stm32x_check_operation_supported(struct flash_bank *bank)
 200 {
 201         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 202
 203         /* if we have a dual flash bank device then
 204          * we need to perform option byte stuff on bank0 only */
 205         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 206                 LOG_ERROR("Option Byte Operation's must use bank0");
 207                 return ERROR_FLASH_OPERATION_FAILED;
 208         }
 209
 210         return ERROR_OK;
 211 }
 212
 213 static int stm32x_read_options(struct flash_bank *bank)
 214 {
 215         uint32_t optiondata;
 216         struct stm32x_flash_bank *stm32x_info = NULL;
 217         struct target *target = bank->target;
 218
 219         stm32x_info = bank->driver_priv;
 220
 221         /* read current option bytes */
 222         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 223         if (retval != ERROR_OK)
 224                 return retval;
 225
 226         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
 227         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 228
 229         if (optiondata & (1 << OPT_READOUT))
 230                 LOG_INFO("Device Security Bit Set");
 231
 232         /* each bit refers to a 4bank protection */
 233         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236
 237         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 238         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 239         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 240         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 241
 242         return ERROR_OK;
 243 }
 244
 245 static int stm32x_erase_options(struct flash_bank *bank)
 246 {
 247         struct stm32x_flash_bank *stm32x_info = NULL;
 248         struct target *target = bank->target;
 249
 250         stm32x_info = bank->driver_priv;
 251
 252         /* read current options */
 253         stm32x_read_options(bank);
 254
 255         /* unlock flash registers */
 256         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 257         if (retval != ERROR_OK)
 258                 return retval;
 259
 260         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 261         if (retval != ERROR_OK)
 262                 return retval;
 263
 264         /* unlock option flash registers */
 265         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 266         if (retval != ERROR_OK)
 267                 return retval;
 268         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         /* erase option bytes */
 273         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 277         if (retval != ERROR_OK)
 278                 return retval;
 279
 280         retval = stm32x_wait_status_busy(bank, 10);
 281         if (retval != ERROR_OK)
 282                 return retval;
 283
 284         /* clear readout protection and complementary option bytes
 285          * this will also force a device unlock if set */
 286         stm32x_info->option_bytes.RDP = 0x5AA5;
 287
 288         return ERROR_OK;
 289 }
 290
 291 static int stm32x_write_options(struct flash_bank *bank)
 292 {
 293         struct stm32x_flash_bank *stm32x_info = NULL;
 294         struct target *target = bank->target;
 295
 296         stm32x_info = bank->driver_priv;
 297
 298         /* unlock flash registers */
 299         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 300         if (retval != ERROR_OK)
 301                 return retval;
 302         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 303         if (retval != ERROR_OK)
 304                 return retval;
 305
 306         /* unlock option flash registers */
 307         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 308         if (retval != ERROR_OK)
 309                 return retval;
 310         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 311         if (retval != ERROR_OK)
 312                 return retval;
 313
 314         /* program option bytes */
 315         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 316         if (retval != ERROR_OK)
 317                 return retval;
 318
 319         /* write user option byte */
 320         retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 321         if (retval != ERROR_OK)
 322                 return retval;
 323
 324         retval = stm32x_wait_status_busy(bank, 10);
 325         if (retval != ERROR_OK)
 326                 return retval;
 327
 328         /* write protection byte 1 */
 329         retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 330         if (retval != ERROR_OK)
 331                 return retval;
 332
 333         retval = stm32x_wait_status_busy(bank, 10);
 334         if (retval != ERROR_OK)
 335                 return retval;
 336
 337         /* write protection byte 2 */
 338         retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 339         if (retval != ERROR_OK)
 340                 return retval;
 341
 342         retval = stm32x_wait_status_busy(bank, 10);
 343         if (retval != ERROR_OK)
 344                 return retval;
 345
 346         /* write protection byte 3 */
 347         retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         retval = stm32x_wait_status_busy(bank, 10);
 352         if (retval != ERROR_OK)
 353                 return retval;
 354
 355         /* write protection byte 4 */
 356         retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 357         if (retval != ERROR_OK)
 358                 return retval;
 359
 360         retval = stm32x_wait_status_busy(bank, 10);
 361         if (retval != ERROR_OK)
 362                 return retval;
 363
 364         /* write readout protection bit */
 365         retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 366         if (retval != ERROR_OK)
 367                 return retval;
 368
 369         retval = stm32x_wait_status_busy(bank, 10);
 370         if (retval != ERROR_OK)
 371                 return retval;
 372
 373         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 374         if (retval != ERROR_OK)
 375                 return retval;
 376
 377         return ERROR_OK;
 378 }
 379
 380 static int stm32x_protect_check(struct flash_bank *bank)
 381 {
 382         struct target *target = bank->target;
 383         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 384
 385         uint32_t protection;
 386         int i, s;
 387         int num_bits;
 388         int set;
 389
 390         if (target->state != TARGET_HALTED) {
 391                 LOG_ERROR("Target not halted");
 392                 return ERROR_TARGET_NOT_HALTED;
 393         }
 394
 395         int retval = stm32x_check_operation_supported(bank);
 396         if (ERROR_OK != retval)
 397                 return retval;
 398
 399         /* medium density - each bit refers to a 4bank protection
 400          * high density - each bit refers to a 2bank protection */
 401         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 402         if (retval != ERROR_OK)
 403                 return retval;
 404
 405         /* medium density - each protection bit is for 4 * 1K pages
 406          * high density - each protection bit is for 2 * 2K pages */
 407         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 408
 409         if (stm32x_info->ppage_size == 2) {
 410                 /* high density flash/connectivity line protection */
 411
 412                 set = 1;
 413
 414                 if (protection & (1 << 31))
 415                         set = 0;
 416
 417                 /* bit 31 controls sector 62 - 255 protection for high density
 418                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 419                 for (s = 62; s < bank->num_sectors; s++)
 420                         bank->sectors[s].is_protected = set;
 421
 422                 if (bank->num_sectors > 61)
 423                         num_bits = 31;
 424
 425                 for (i = 0; i < num_bits; i++) {
 426                         set = 1;
 427
 428                         if (protection & (1 << i))
 429                                 set = 0;
 430
 431                         for (s = 0; s < stm32x_info->ppage_size; s++)
 432                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 433                 }
 434         } else {
 435                 /* low/medium density flash protection */
 436                 for (i = 0; i < num_bits; i++) {
 437                         set = 1;
 438
 439                         if (protection & (1 << i))
 440                                 set = 0;
 441
 442                         for (s = 0; s < stm32x_info->ppage_size; s++)
 443                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 444                 }
 445         }
 446
 447         return ERROR_OK;
 448 }
 449
 450 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 451 {
 452         struct target *target = bank->target;
 453         int i;
 454
 455         if (bank->target->state != TARGET_HALTED) {
 456                 LOG_ERROR("Target not halted");
 457                 return ERROR_TARGET_NOT_HALTED;
 458         }
 459
 460         if ((first == 0) && (last == (bank->num_sectors - 1)))
 461                 return stm32x_mass_erase(bank);
 462
 463         /* unlock flash registers */
 464         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 465         if (retval != ERROR_OK)
 466                 return retval;
 467         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 468         if (retval != ERROR_OK)
 469                 return retval;
 470
 471         for (i = first; i <= last; i++) {
 472                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 473                 if (retval != ERROR_OK)
 474                         return retval;
 475                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 476                                 bank->base + bank->sectors[i].offset);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479                 retval = target_write_u32(target,
 480                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 481                 if (retval != ERROR_OK)
 482                         return retval;
 483
 484                 retval = stm32x_wait_status_busy(bank, 100);
 485                 if (retval != ERROR_OK)
 486                         return retval;
 487
 488                 bank->sectors[i].is_erased = 1;
 489         }
 490
 491         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 492         if (retval != ERROR_OK)
 493                 return retval;
 494
 495         return ERROR_OK;
 496 }
 497
 498 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 499 {
 500         struct stm32x_flash_bank *stm32x_info = NULL;
 501         struct target *target = bank->target;
 502         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 503         int i, reg, bit;
 504         int status;
 505         uint32_t protection;
 506
 507         stm32x_info = bank->driver_priv;
 508
 509         if (target->state != TARGET_HALTED) {
 510                 LOG_ERROR("Target not halted");
 511                 return ERROR_TARGET_NOT_HALTED;
 512         }
 513
 514         int retval = stm32x_check_operation_supported(bank);
 515         if (ERROR_OK != retval)
 516                 return retval;
 517
 518         if ((first % stm32x_info->ppage_size) != 0) {
 519                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 520                                 stm32x_info->ppage_size);
 521                 first = first - (first % stm32x_info->ppage_size);
 522         }
 523         if (((last + 1) % stm32x_info->ppage_size) != 0) {
 524                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 525                                 stm32x_info->ppage_size);
 526                 last++;
 527                 last = last - (last % stm32x_info->ppage_size);
 528                 last--;
 529         }
 530
 531         /* medium density - each bit refers to a 4bank protection
 532          * high density - each bit refers to a 2bank protection */
 533         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 534         if (retval != ERROR_OK)
 535                 return retval;
 536
 537         prot_reg[0] = (uint16_t)protection;
 538         prot_reg[1] = (uint16_t)(protection >> 8);
 539         prot_reg[2] = (uint16_t)(protection >> 16);
 540         prot_reg[3] = (uint16_t)(protection >> 24);
 541
 542         if (stm32x_info->ppage_size == 2) {
 543                 /* high density flash */
 544
 545                 /* bit 7 controls sector 62 - 255 protection */
 546                 if (last > 61) {
 547                         if (set)
 548                                 prot_reg[3] &= ~(1 << 7);
 549                         else
 550                                 prot_reg[3] |= (1 << 7);
 551                 }
 552
 553                 if (first > 61)
 554                         first = 62;
 555                 if (last > 61)
 556                         last = 61;
 557
 558                 for (i = first; i <= last; i++) {
 559                         reg = (i / stm32x_info->ppage_size) / 8;
 560                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 561
 562                         if (set)
 563                                 prot_reg[reg] &= ~(1 << bit);
 564                         else
 565                                 prot_reg[reg] |= (1 << bit);
 566                 }
 567         } else {
 568                 /* medium density flash */
 569                 for (i = first; i <= last; i++) {
 570                         reg = (i / stm32x_info->ppage_size) / 8;
 571                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 572
 573                         if (set)
 574                                 prot_reg[reg] &= ~(1 << bit);
 575                         else
 576                                 prot_reg[reg] |= (1 << bit);
 577                 }
 578         }
 579
 580         status = stm32x_erase_options(bank);
 581         if (status != ERROR_OK)
 582                 return status;
 583
 584         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 585         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 586         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 587         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 588
 589         return stm32x_write_options(bank);
 590 }
 591
 592 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 593                 uint32_t offset, uint32_t count)
 594 {
 595         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 596         struct target *target = bank->target;
 597         uint32_t buffer_size = 16384;
 598         struct working_area *source;
 599         uint32_t address = bank->base + offset;
 600         struct reg_param reg_params[5];
 601         struct armv7m_algorithm armv7m_info;
 602         int retval = ERROR_OK;
 603
 604         /* see contrib/loaders/flash/stm32f1x.S for src */
 605
 606         static const uint8_t stm32x_flash_write_code[] = {
 607                 /* #define STM32_FLASH_SR_OFFSET 0x0C */
 608                 /* wait_fifo: */
 609                         0x16, 0x68,   /* ldr   r6, [r2, #0] */
 610                         0x00, 0x2e,   /* cmp   r6, #0 */
 611                         0x18, 0xd0,   /* beq   exit */
 612                         0x55, 0x68,   /* ldr   r5, [r2, #4] */
 613                         0xb5, 0x42,   /* cmp   r5, r6 */
 614                         0xf9, 0xd0,   /* beq   wait_fifo */
 615                         0x2e, 0x88,   /* ldrh  r6, [r5, #0] */
 616                         0x26, 0x80,   /* strh  r6, [r4, #0] */
 617                         0x02, 0x35,   /* adds  r5, #2 */
 618                         0x02, 0x34,   /* adds  r4, #2 */
 619                 /* busy: */
 620                         0xc6, 0x68,   /* ldr   r6, [r0, #STM32_FLASH_SR_OFFSET] */
 621                         0x01, 0x27,   /* movs  r7, #1 */
 622                         0x3e, 0x42,   /* tst   r6, r7 */
 623                         0xfb, 0xd1,   /* bne   busy */
 624                         0x14, 0x27,   /* movs  r7, #0x14 */
 625                         0x3e, 0x42,   /* tst   r6, r7 */
 626                         0x08, 0xd1,   /* bne   error */
 627                         0x9d, 0x42,   /* cmp   r5, r3 */
 628                         0x01, 0xd3,   /* bcc   no_wrap */
 629                         0x15, 0x46,   /* mov   r5, r2 */
 630                         0x08, 0x35,   /* adds  r5, #8 */
 631                 /* no_wrap: */
 632                         0x55, 0x60,   /* str   r5, [r2, #4] */
 633                         0x01, 0x39,   /* subs  r1, r1, #1 */
 634                         0x00, 0x29,   /* cmp   r1, #0 */
 635                         0x02, 0xd0,   /* beq   exit */
 636                         0xe5, 0xe7,   /* b     wait_fifo */
 637                 /* error: */
 638                         0x00, 0x20,   /* movs  r0, #0 */
 639                         0x50, 0x60,   /* str   r0, [r2, #4] */
 640                 /* exit: */
 641                         0x30, 0x46,   /* mov   r0, r6 */
 642                         0x00, 0xbe,   /* bkpt  #0 */
 643         };
 644
 645         /* flash write code */
 646         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 647                         &stm32x_info->write_algorithm) != ERROR_OK) {
 648                 LOG_WARNING("no working area available, can't do block memory writes");
 649                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 650         };
 651
 652         retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 653                         sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
 654         if (retval != ERROR_OK)
 655                 return retval;
 656
 657         /* memory buffer */
 658         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 659                 buffer_size /= 2;
 660                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 661                 if (buffer_size <= 256) {
 662                         /* if we already allocated the writing code, but failed to get a
 663                          * buffer, free the algorithm */
 664                         if (stm32x_info->write_algorithm)
 665                                 target_free_working_area(target, stm32x_info->write_algorithm);
 666
 667                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 668                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 669                 }
 670         };
 671
 672         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 673         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 674         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 675         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 676         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 677
 678         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 679         buf_set_u32(reg_params[1].value, 0, 32, count);
 680         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 681         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 682         buf_set_u32(reg_params[4].value, 0, 32, address);
 683
 684         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 685         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 686
 687         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 688                         0, NULL,
 689                         5, reg_params,
 690                         source->address, source->size,
 691                         stm32x_info->write_algorithm->address, 0,
 692                         &armv7m_info);
 693
 694         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 695                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 696                                 buf_get_u32(reg_params[4].value, 0, 32));
 697
 698                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 699                         LOG_ERROR("flash memory not erased before writing");
 700                         /* Clear but report errors */
 701                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 702                 }
 703
 704                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 705                         LOG_ERROR("flash memory write protected");
 706                         /* Clear but report errors */
 707                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 708                 }
 709         }
 710
 711         target_free_working_area(target, source);
 712         target_free_working_area(target, stm32x_info->write_algorithm);
 713
 714         destroy_reg_param(&reg_params[0]);
 715         destroy_reg_param(&reg_params[1]);
 716         destroy_reg_param(&reg_params[2]);
 717         destroy_reg_param(&reg_params[3]);
 718         destroy_reg_param(&reg_params[4]);
 719
 720         return retval;
 721 }
 722
 723 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 724                 uint32_t offset, uint32_t count)
 725 {
 726         struct target *target = bank->target;
 727         uint32_t words_remaining = (count / 2);
 728         uint32_t bytes_remaining = (count & 0x00000001);
 729         uint32_t address = bank->base + offset;
 730         uint32_t bytes_written = 0;
 731         int retval;
 732
 733         if (bank->target->state != TARGET_HALTED) {
 734                 LOG_ERROR("Target not halted");
 735                 return ERROR_TARGET_NOT_HALTED;
 736         }
 737
 738         if (offset & 0x1) {
 739                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 740                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 741         }
 742
 743         /* unlock flash registers */
 744         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 745         if (retval != ERROR_OK)
 746                 return retval;
 747         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 748         if (retval != ERROR_OK)
 749                 return retval;
 750
 751         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 752         if (retval != ERROR_OK)
 753                 return retval;
 754
 755         /* multiple half words (2-byte) to be programmed? */
 756         if (words_remaining > 0) {
 757                 /* try using a block write */
 758                 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 759                 if (retval != ERROR_OK) {
 760                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 761                                 /* if block write failed (no sufficient working area),
 762                                  * we use normal (slow) single dword accesses */
 763                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 764                         }
 765                 } else {
 766                         buffer += words_remaining * 2;
 767                         address += words_remaining * 2;
 768                         words_remaining = 0;
 769                 }
 770         }
 771
 772         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 773                 goto reset_pg_and_lock;
 774
 775         while (words_remaining > 0) {
 776                 uint16_t value;
 777                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 778
 779                 retval = target_write_u16(target, address, value);
 780                 if (retval != ERROR_OK)
 781                         goto reset_pg_and_lock;
 782
 783                 retval = stm32x_wait_status_busy(bank, 5);
 784                 if (retval != ERROR_OK)
 785                         goto reset_pg_and_lock;
 786
 787                 bytes_written += 2;
 788                 words_remaining--;
 789                 address += 2;
 790         }
 791
 792         if (bytes_remaining) {
 793                 uint16_t value = 0xffff;
 794                 memcpy(&value, buffer + bytes_written, bytes_remaining);
 795
 796                 retval = target_write_u16(target, address, value);
 797                 if (retval != ERROR_OK)
 798                         goto reset_pg_and_lock;
 799
 800                 retval = stm32x_wait_status_busy(bank, 5);
 801                 if (retval != ERROR_OK)
 802                         goto reset_pg_and_lock;
 803         }
 804
 805         return target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 806
 807 reset_pg_and_lock:
 808         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 809         return retval;
 810 }
 811
 812 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 813 {
 814         /* This check the device CPUID core register to detect
 815          * the M0 from the M3 devices. */
 816
 817         struct target *target = bank->target;
 818         uint32_t cpuid, device_id_register = 0;
 819
 820         /* Get the CPUID from the ARM Core
 821          * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
 822         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 823         if (retval != ERROR_OK)
 824                 return retval;
 825
 826         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 827                 /* 0xC20 is M0 devices */
 828                 device_id_register = 0x40015800;
 829         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 830                 /* 0xC23 is M3 devices */
 831                 device_id_register = 0xE0042000;
 832         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 833                 /* 0xC24 is M4 devices */
 834                 device_id_register = 0xE0042000;
 835         } else {
 836                 LOG_ERROR("Cannot identify target as a stm32x");
 837                 return ERROR_FAIL;
 838         }
 839
 840         /* read stm32 device id register */
 841         retval = target_read_u32(target, device_id_register, device_id);
 842         if (retval != ERROR_OK)
 843                 return retval;
 844
 845         return retval;
 846 }
 847
 848 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 849 {
 850         struct target *target = bank->target;
 851         uint32_t cpuid, flash_size_reg;
 852
 853         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 854         if (retval != ERROR_OK)
 855                 return retval;
 856
 857         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 858                 /* 0xC20 is M0 devices */
 859                 flash_size_reg = 0x1FFFF7CC;
 860         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 861                 /* 0xC23 is M3 devices */
 862                 flash_size_reg = 0x1FFFF7E0;
 863         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 864                 /* 0xC24 is M4 devices */
 865                 flash_size_reg = 0x1FFFF7CC;
 866         } else {
 867                 LOG_ERROR("Cannot identify target as a stm32x");
 868                 return ERROR_FAIL;
 869         }
 870
 871         retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 872         if (retval != ERROR_OK)
 873                 return retval;
 874
 875         return retval;
 876 }
 877
 878 static int stm32x_probe(struct flash_bank *bank)
 879 {
 880         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 881         int i;
 882         uint16_t flash_size_in_kb;
 883         uint32_t device_id;
 884         int page_size;
 885         uint32_t base_address = 0x08000000;
 886
 887         stm32x_info->probed = 0;
 888         stm32x_info->register_base = FLASH_REG_BASE_B0;
 889
 890         /* read stm32 device id register */
 891         int retval = stm32x_get_device_id(bank, &device_id);
 892         if (retval != ERROR_OK)
 893                 return retval;
 894
 895         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 896
 897         /* get flash size from target. */
 898         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 899         if (retval != ERROR_OK) {
 900                 LOG_WARNING("failed reading flash size, default to max target family");
 901                 /* failed reading flash size, default to max target family */
 902                 flash_size_in_kb = 0xffff;
 903         }
 904
 905         /* some variants read 0 for flash size register
 906          * use a max flash size as a default */
 907         if (flash_size_in_kb == 0)
 908                 flash_size_in_kb = 0xffff;
 909
 910         if ((device_id & 0xfff) == 0x410) {
 911                 /* medium density - we have 1k pages
 912                  * 4 pages for a protection area */
 913                 page_size = 1024;
 914                 stm32x_info->ppage_size = 4;
 915
 916                 /* check for early silicon */
 917                 if (flash_size_in_kb == 0xffff) {
 918                         /* number of sectors incorrect on revA */
 919                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 920                         flash_size_in_kb = 128;
 921                 }
 922         } else if ((device_id & 0xfff) == 0x412) {
 923                 /* low density - we have 1k pages
 924                  * 4 pages for a protection area */
 925                 page_size = 1024;
 926                 stm32x_info->ppage_size = 4;
 927
 928                 /* check for early silicon */
 929                 if (flash_size_in_kb == 0xffff) {
 930                         /* number of sectors incorrect on revA */
 931                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
 932                         flash_size_in_kb = 32;
 933                 }
 934         } else if ((device_id & 0xfff) == 0x414) {
 935                 /* high density - we have 2k pages
 936                  * 2 pages for a protection area */
 937                 page_size = 2048;
 938                 stm32x_info->ppage_size = 2;
 939
 940                 /* check for early silicon */
 941                 if (flash_size_in_kb == 0xffff) {
 942                         /* number of sectors incorrect on revZ */
 943                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
 944                         flash_size_in_kb = 512;
 945                 }
 946         } else if ((device_id & 0xfff) == 0x418) {
 947                 /* connectivity line density - we have 2k pages
 948                  * 2 pages for a protection area */
 949                 page_size = 2048;
 950                 stm32x_info->ppage_size = 2;
 951
 952                 /* check for early silicon */
 953                 if (flash_size_in_kb == 0xffff) {
 954                         /* number of sectors incorrect on revZ */
 955                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
 956                         flash_size_in_kb = 256;
 957                 }
 958         } else if ((device_id & 0xfff) == 0x420) {
 959                 /* value line density - we have 1k pages
 960                  * 4 pages for a protection area */
 961                 page_size = 1024;
 962                 stm32x_info->ppage_size = 4;
 963
 964                 /* check for early silicon */
 965                 if (flash_size_in_kb == 0xffff) {
 966                         /* number of sectors may be incorrect on early silicon */
 967                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 968                         flash_size_in_kb = 128;
 969                 }
 970         } else if ((device_id & 0xfff) == 0x422) {
 971                 /* stm32f30x - we have 2k pages
 972                  * 2 pages for a protection area */
 973                 page_size = 2048;
 974                 stm32x_info->ppage_size = 2;
 975
 976                 /* check for early silicon */
 977                 if (flash_size_in_kb == 0xffff) {
 978                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
 979                         flash_size_in_kb = 256;
 980                 }
 981         } else if ((device_id & 0xfff) == 0x428) {
 982                 /* value line High density - we have 2k pages
 983                  * 4 pages for a protection area */
 984                 page_size = 2048;
 985                 stm32x_info->ppage_size = 4;
 986
 987                 /* check for early silicon */
 988                 if (flash_size_in_kb == 0xffff) {
 989                         /* number of sectors may be incorrect on early silicon */
 990                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 991                         flash_size_in_kb = 128;
 992                 }
 993         } else if ((device_id & 0xfff) == 0x430) {
 994                 /* xl line density - we have 2k pages
 995                  * 2 pages for a protection area */
 996                 page_size = 2048;
 997                 stm32x_info->ppage_size = 2;
 998                 stm32x_info->has_dual_banks = true;
 999
1000                 /* check for early silicon */
1001                 if (flash_size_in_kb == 0xffff) {
1002                         /* number of sectors may be incorrect on early silicon */
1003                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
1004                         flash_size_in_kb = 1024;
1005                 }
1006
1007                 /* split reported size into matching bank */
1008                 if (bank->base != 0x08080000) {
1009                         /* bank 0 will be fixed 512k */
1010                         flash_size_in_kb = 512;
1011                 } else {
1012                         flash_size_in_kb -= 512;
1013                         /* bank1 also uses a register offset */
1014                         stm32x_info->register_base = FLASH_REG_BASE_B1;
1015                         base_address = 0x08080000;
1016                 }
1017         } else if ((device_id & 0xfff) == 0x432) {
1018                 /* stm32f37x - we have 2k pages
1019                  * 2 pages for a protection area */
1020                 page_size = 2048;
1021                 stm32x_info->ppage_size = 2;
1022
1023                 /* check for early silicon */
1024                 if (flash_size_in_kb == 0xffff) {
1025                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
1026                         flash_size_in_kb = 256;
1027                 }
1028         } else if ((device_id & 0xfff) == 0x440) {
1029                 /* stm32f0x - we have 1k pages
1030                  * 4 pages for a protection area */
1031                 page_size = 1024;
1032                 stm32x_info->ppage_size = 4;
1033
1034                 /* check for early silicon */
1035                 if (flash_size_in_kb == 0xffff) {
1036                         /* number of sectors incorrect on revZ */
1037                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 64k flash");
1038                         flash_size_in_kb = 64;
1039                 }
1040         } else {
1041                 LOG_WARNING("Cannot identify target as a STM32 family.");
1042                 return ERROR_FAIL;
1043         }
1044
1045         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1046
1047         /* did we assign flash size? */
1048         assert(flash_size_in_kb != 0xffff);
1049
1050         /* calculate numbers of pages */
1051         int num_pages = flash_size_in_kb * 1024 / page_size;
1052
1053         /* check that calculation result makes sense */
1054         assert(num_pages > 0);
1055
1056         if (bank->sectors) {
1057                 free(bank->sectors);
1058                 bank->sectors = NULL;
1059         }
1060
1061         bank->base = base_address;
1062         bank->size = (num_pages * page_size);
1063         bank->num_sectors = num_pages;
1064         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1065
1066         for (i = 0; i < num_pages; i++) {
1067                 bank->sectors[i].offset = i * page_size;
1068                 bank->sectors[i].size = page_size;
1069                 bank->sectors[i].is_erased = -1;
1070                 bank->sectors[i].is_protected = 1;
1071         }
1072
1073         stm32x_info->probed = 1;
1074
1075         return ERROR_OK;
1076 }
1077
1078 static int stm32x_auto_probe(struct flash_bank *bank)
1079 {
1080         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1081         if (stm32x_info->probed)
1082                 return ERROR_OK;
1083         return stm32x_probe(bank);
1084 }
1085
1086 #if 0
1087 COMMAND_HANDLER(stm32x_handle_part_id_command)
1088 {
1089         return ERROR_OK;
1090 }
1091 #endif
1092
1093 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1094 {
1095         uint32_t device_id;
1096         int printed;
1097
1098                 /* read stm32 device id register */
1099         int retval = stm32x_get_device_id(bank, &device_id);
1100         if (retval != ERROR_OK)
1101                 return retval;
1102
1103         if ((device_id & 0xfff) == 0x410) {
1104                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1105                 buf += printed;
1106                 buf_size -= printed;
1107
1108                 switch (device_id >> 16) {
1109                         case 0x0000:
1110                                 snprintf(buf, buf_size, "A");
1111                                 break;
1112
1113                         case 0x2000:
1114                                 snprintf(buf, buf_size, "B");
1115                                 break;
1116
1117                         case 0x2001:
1118                                 snprintf(buf, buf_size, "Z");
1119                                 break;
1120
1121                         case 0x2003:
1122                                 snprintf(buf, buf_size, "Y");
1123                                 break;
1124
1125                         default:
1126                                 snprintf(buf, buf_size, "unknown");
1127                                 break;
1128                 }
1129         } else if ((device_id & 0xfff) == 0x412) {
1130                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1131                 buf += printed;
1132                 buf_size -= printed;
1133
1134                 switch (device_id >> 16) {
1135                         case 0x1000:
1136                                 snprintf(buf, buf_size, "A");
1137                                 break;
1138
1139                         default:
1140                                 snprintf(buf, buf_size, "unknown");
1141                                 break;
1142                 }
1143         } else if ((device_id & 0xfff) == 0x414) {
1144                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1145                 buf += printed;
1146                 buf_size -= printed;
1147
1148                 switch (device_id >> 16) {
1149                         case 0x1000:
1150                                 snprintf(buf, buf_size, "A");
1151                                 break;
1152
1153                         case 0x1001:
1154                                 snprintf(buf, buf_size, "Z");
1155                                 break;
1156
1157                         default:
1158                                 snprintf(buf, buf_size, "unknown");
1159                                 break;
1160                 }
1161         } else if ((device_id & 0xfff) == 0x418) {
1162                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1163                 buf += printed;
1164                 buf_size -= printed;
1165
1166                 switch (device_id >> 16) {
1167                         case 0x1000:
1168                                 snprintf(buf, buf_size, "A");
1169                                 break;
1170
1171                         case 0x1001:
1172                                 snprintf(buf, buf_size, "Z");
1173                                 break;
1174
1175                         default:
1176                                 snprintf(buf, buf_size, "unknown");
1177                                 break;
1178                 }
1179         } else if ((device_id & 0xfff) == 0x420) {
1180                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1181                 buf += printed;
1182                 buf_size -= printed;
1183
1184                 switch (device_id >> 16) {
1185                         case 0x1000:
1186                                 snprintf(buf, buf_size, "A");
1187                                 break;
1188
1189                         case 0x1001:
1190                                 snprintf(buf, buf_size, "Z");
1191                                 break;
1192
1193                         default:
1194                                 snprintf(buf, buf_size, "unknown");
1195                                 break;
1196                 }
1197         } else if ((device_id & 0xfff) == 0x422) {
1198                 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1199                 buf += printed;
1200                 buf_size -= printed;
1201
1202                 switch (device_id >> 16) {
1203                         case 0x1000:
1204                                 snprintf(buf, buf_size, "1.0");
1205                                 break;
1206
1207                         default:
1208                                 snprintf(buf, buf_size, "unknown");
1209                                 break;
1210                 }
1211         } else if ((device_id & 0xfff) == 0x428) {
1212                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1213                 buf += printed;
1214                 buf_size -= printed;
1215
1216                 switch (device_id >> 16) {
1217                         case 0x1000:
1218                                 snprintf(buf, buf_size, "A");
1219                                 break;
1220
1221                         case 0x1001:
1222                                 snprintf(buf, buf_size, "Z");
1223                                 break;
1224
1225                         default:
1226                                 snprintf(buf, buf_size, "unknown");
1227                                 break;
1228                 }
1229         } else if ((device_id & 0xfff) == 0x430) {
1230                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1231                 buf += printed;
1232                 buf_size -= printed;
1233
1234                 switch (device_id >> 16) {
1235                         case 0x1000:
1236                                 snprintf(buf, buf_size, "A");
1237                                 break;
1238
1239                         default:
1240                                 snprintf(buf, buf_size, "unknown");
1241                                 break;
1242                 }
1243         } else if ((device_id & 0xfff) == 0x432) {
1244                 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1245                 buf += printed;
1246                 buf_size -= printed;
1247
1248                 switch (device_id >> 16) {
1249                         case 0x1000:
1250                                 snprintf(buf, buf_size, "1.0");
1251                                 break;
1252
1253                         default:
1254                                 snprintf(buf, buf_size, "unknown");
1255                                 break;
1256                 }
1257         } else if ((device_id & 0xfff) == 0x440) {
1258                 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1259                 buf += printed;
1260                 buf_size -= printed;
1261
1262                 switch (device_id >> 16) {
1263                         case 0x1000:
1264                                 snprintf(buf, buf_size, "1.0");
1265                                 break;
1266
1267                         case 0x2000:
1268                                 snprintf(buf, buf_size, "2.0");
1269                                 break;
1270
1271                         default:
1272                                 snprintf(buf, buf_size, "unknown");
1273                                 break;
1274                 }
1275         } else {
1276                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1277                 return ERROR_FAIL;
1278         }
1279
1280         return ERROR_OK;
1281 }
1282
1283 COMMAND_HANDLER(stm32x_handle_lock_command)
1284 {
1285         struct target *target = NULL;
1286         struct stm32x_flash_bank *stm32x_info = NULL;
1287
1288         if (CMD_ARGC < 1)
1289                 return ERROR_COMMAND_SYNTAX_ERROR;
1290
1291         struct flash_bank *bank;
1292         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1293         if (ERROR_OK != retval)
1294                 return retval;
1295
1296         stm32x_info = bank->driver_priv;
1297
1298         target = bank->target;
1299
1300         if (target->state != TARGET_HALTED) {
1301                 LOG_ERROR("Target not halted");
1302                 return ERROR_TARGET_NOT_HALTED;
1303         }
1304
1305         retval = stm32x_check_operation_supported(bank);
1306         if (ERROR_OK != retval)
1307                 return retval;
1308
1309         if (stm32x_erase_options(bank) != ERROR_OK) {
1310                 command_print(CMD_CTX, "stm32x failed to erase options");
1311                 return ERROR_OK;
1312         }
1313
1314         /* set readout protection */
1315         stm32x_info->option_bytes.RDP = 0;
1316
1317         if (stm32x_write_options(bank) != ERROR_OK) {
1318                 command_print(CMD_CTX, "stm32x failed to lock device");
1319                 return ERROR_OK;
1320         }
1321
1322         command_print(CMD_CTX, "stm32x locked");
1323
1324         return ERROR_OK;
1325 }
1326
1327 COMMAND_HANDLER(stm32x_handle_unlock_command)
1328 {
1329         struct target *target = NULL;
1330
1331         if (CMD_ARGC < 1)
1332                 return ERROR_COMMAND_SYNTAX_ERROR;
1333
1334         struct flash_bank *bank;
1335         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1336         if (ERROR_OK != retval)
1337                 return retval;
1338
1339         target = bank->target;
1340
1341         if (target->state != TARGET_HALTED) {
1342                 LOG_ERROR("Target not halted");
1343                 return ERROR_TARGET_NOT_HALTED;
1344         }
1345
1346         retval = stm32x_check_operation_supported(bank);
1347         if (ERROR_OK != retval)
1348                 return retval;
1349
1350         if (stm32x_erase_options(bank) != ERROR_OK) {
1351                 command_print(CMD_CTX, "stm32x failed to unlock device");
1352                 return ERROR_OK;
1353         }
1354
1355         if (stm32x_write_options(bank) != ERROR_OK) {
1356                 command_print(CMD_CTX, "stm32x failed to lock device");
1357                 return ERROR_OK;
1358         }
1359
1360         command_print(CMD_CTX, "stm32x unlocked.\n"
1361                         "INFO: a reset or power cycle is required "
1362                         "for the new settings to take effect.");
1363
1364         return ERROR_OK;
1365 }
1366
1367 COMMAND_HANDLER(stm32x_handle_options_read_command)
1368 {
1369         uint32_t optionbyte;
1370         struct target *target = NULL;
1371         struct stm32x_flash_bank *stm32x_info = NULL;
1372
1373         if (CMD_ARGC < 1)
1374                 return ERROR_COMMAND_SYNTAX_ERROR;
1375
1376         struct flash_bank *bank;
1377         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1378         if (ERROR_OK != retval)
1379                 return retval;
1380
1381         stm32x_info = bank->driver_priv;
1382
1383         target = bank->target;
1384
1385         if (target->state != TARGET_HALTED) {
1386                 LOG_ERROR("Target not halted");
1387                 return ERROR_TARGET_NOT_HALTED;
1388         }
1389
1390         retval = stm32x_check_operation_supported(bank);
1391         if (ERROR_OK != retval)
1392                 return retval;
1393
1394         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1395         if (retval != ERROR_OK)
1396                 return retval;
1397         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1398
1399         if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1400                 command_print(CMD_CTX, "Option Byte Complement Error");
1401
1402         if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1403                 command_print(CMD_CTX, "Readout Protection On");
1404         else
1405                 command_print(CMD_CTX, "Readout Protection Off");
1406
1407         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1408                 command_print(CMD_CTX, "Software Watchdog");
1409         else
1410                 command_print(CMD_CTX, "Hardware Watchdog");
1411
1412         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1413                 command_print(CMD_CTX, "Stop: No reset generated");
1414         else
1415                 command_print(CMD_CTX, "Stop: Reset generated");
1416
1417         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1418                 command_print(CMD_CTX, "Standby: No reset generated");
1419         else
1420                 command_print(CMD_CTX, "Standby: Reset generated");
1421
1422         if (stm32x_info->has_dual_banks) {
1423                 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1424                         command_print(CMD_CTX, "Boot: Bank 0");
1425                 else
1426                         command_print(CMD_CTX, "Boot: Bank 1");
1427         }
1428
1429         return ERROR_OK;
1430 }
1431
1432 COMMAND_HANDLER(stm32x_handle_options_write_command)
1433 {
1434         struct target *target = NULL;
1435         struct stm32x_flash_bank *stm32x_info = NULL;
1436         uint16_t optionbyte = 0xF8;
1437
1438         if (CMD_ARGC < 4)
1439                 return ERROR_COMMAND_SYNTAX_ERROR;
1440
1441         struct flash_bank *bank;
1442         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1443         if (ERROR_OK != retval)
1444                 return retval;
1445
1446         stm32x_info = bank->driver_priv;
1447
1448         target = bank->target;
1449
1450         if (target->state != TARGET_HALTED) {
1451                 LOG_ERROR("Target not halted");
1452                 return ERROR_TARGET_NOT_HALTED;
1453         }
1454
1455         retval = stm32x_check_operation_supported(bank);
1456         if (ERROR_OK != retval)
1457                 return retval;
1458
1459         /* REVISIT: ignores some options which we will display...
1460          * and doesn't insist on the specified syntax.
1461          */
1462
1463         /* OPT_RDWDGSW */
1464         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1465                 optionbyte |= (1 << 0);
1466         else    /* REVISIT must be "HWWDG" then ... */
1467                 optionbyte &= ~(1 << 0);
1468
1469         /* OPT_RDRSTSTOP */
1470         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1471                 optionbyte |= (1 << 1);
1472         else    /* REVISIT must be "RSTSTNDBY" then ... */
1473                 optionbyte &= ~(1 << 1);
1474
1475         /* OPT_RDRSTSTDBY */
1476         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1477                 optionbyte |= (1 << 2);
1478         else    /* REVISIT must be "RSTSTOP" then ... */
1479                 optionbyte &= ~(1 << 2);
1480
1481         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1482                 /* OPT_BFB2 */
1483                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1484                         optionbyte |= (1 << 3);
1485                 else
1486                         optionbyte &= ~(1 << 3);
1487         }
1488
1489         if (stm32x_erase_options(bank) != ERROR_OK) {
1490                 command_print(CMD_CTX, "stm32x failed to erase options");
1491                 return ERROR_OK;
1492         }
1493
1494         stm32x_info->option_bytes.user_options = optionbyte;
1495
1496         if (stm32x_write_options(bank) != ERROR_OK) {
1497                 command_print(CMD_CTX, "stm32x failed to write options");
1498                 return ERROR_OK;
1499         }
1500
1501         command_print(CMD_CTX, "stm32x write options complete.\n"
1502                                 "INFO: a reset or power cycle is required "
1503                                 "for the new settings to take effect.");
1504
1505         return ERROR_OK;
1506 }
1507
1508 static int stm32x_mass_erase(struct flash_bank *bank)
1509 {
1510         struct target *target = bank->target;
1511
1512         if (target->state != TARGET_HALTED) {
1513                 LOG_ERROR("Target not halted");
1514                 return ERROR_TARGET_NOT_HALTED;
1515         }
1516
1517         /* unlock option flash registers */
1518         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1519         if (retval != ERROR_OK)
1520                 return retval;
1521         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1522         if (retval != ERROR_OK)
1523                 return retval;
1524
1525         /* mass erase flash memory */
1526         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1527         if (retval != ERROR_OK)
1528                 return retval;
1529         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1530                         FLASH_MER | FLASH_STRT);
1531         if (retval != ERROR_OK)
1532                 return retval;
1533
1534         retval = stm32x_wait_status_busy(bank, 100);
1535         if (retval != ERROR_OK)
1536                 return retval;
1537
1538         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1539         if (retval != ERROR_OK)
1540                 return retval;
1541
1542         return ERROR_OK;
1543 }
1544
1545 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1546 {
1547         int i;
1548
1549         if (CMD_ARGC < 1)
1550                 return ERROR_COMMAND_SYNTAX_ERROR;
1551
1552         struct flash_bank *bank;
1553         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1554         if (ERROR_OK != retval)
1555                 return retval;
1556
1557         retval = stm32x_mass_erase(bank);
1558         if (retval == ERROR_OK) {
1559                 /* set all sectors as erased */
1560                 for (i = 0; i < bank->num_sectors; i++)
1561                         bank->sectors[i].is_erased = 1;
1562
1563                 command_print(CMD_CTX, "stm32x mass erase complete");
1564         } else
1565                 command_print(CMD_CTX, "stm32x mass erase failed");
1566
1567         return retval;
1568 }
1569
1570 static const struct command_registration stm32x_exec_command_handlers[] = {
1571         {
1572                 .name = "lock",
1573                 .handler = stm32x_handle_lock_command,
1574                 .mode = COMMAND_EXEC,
1575                 .usage = "bank_id",
1576                 .help = "Lock entire flash device.",
1577         },
1578         {
1579                 .name = "unlock",
1580                 .handler = stm32x_handle_unlock_command,
1581                 .mode = COMMAND_EXEC,
1582                 .usage = "bank_id",
1583                 .help = "Unlock entire protected flash device.",
1584         },
1585         {
1586                 .name = "mass_erase",
1587                 .handler = stm32x_handle_mass_erase_command,
1588                 .mode = COMMAND_EXEC,
1589                 .usage = "bank_id",
1590                 .help = "Erase entire flash device.",
1591         },
1592         {
1593                 .name = "options_read",
1594                 .handler = stm32x_handle_options_read_command,
1595                 .mode = COMMAND_EXEC,
1596                 .usage = "bank_id",
1597                 .help = "Read and display device option byte.",
1598         },
1599         {
1600                 .name = "options_write",
1601                 .handler = stm32x_handle_options_write_command,
1602                 .mode = COMMAND_EXEC,
1603                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1604                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1605                         "('RSTSTOP'|'NORSTSTOP')",
1606                 .help = "Replace bits in device option byte.",
1607         },
1608         COMMAND_REGISTRATION_DONE
1609 };
1610
1611 static const struct command_registration stm32x_command_handlers[] = {
1612         {
1613                 .name = "stm32f1x",
1614                 .mode = COMMAND_ANY,
1615                 .help = "stm32f1x flash command group",
1616                 .usage = "",
1617                 .chain = stm32x_exec_command_handlers,
1618         },
1619         COMMAND_REGISTRATION_DONE
1620 };
1621
1622 struct flash_driver stm32f1x_flash = {
1623         .name = "stm32f1x",
1624         .commands = stm32x_command_handlers,
1625         .flash_bank_command = stm32x_flash_bank_command,
1626         .erase = stm32x_erase,
1627         .protect = stm32x_protect,
1628         .write = stm32x_write,
1629         .read = default_flash_read,
1630         .probe = stm32x_probe,
1631         .auto_probe = stm32x_auto_probe,
1632         .erase_check = default_flash_blank_check,
1633         .protect_check = stm32x_protect_check,
1634         .info = get_stm32x_info,
1635 };