git.sur5r.net Git - openocd/blob - src/flash/nor/stm32f1x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   9  *   andreas.fritiofson@gmail.com                                          *
  10  *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include <helper/binarybuffer.h>
  33 #include <target/algorithm.h>
  34 #include <target/armv7m.h>
  35
  36 /* stm32x register locations */
  37
  38 #define FLASH_REG_BASE_B0 0x40022000
  39 #define FLASH_REG_BASE_B1 0x40022040
  40
  41 #define STM32_FLASH_ACR     0x00
  42 #define STM32_FLASH_KEYR    0x04
  43 #define STM32_FLASH_OPTKEYR 0x08
  44 #define STM32_FLASH_SR      0x0C
  45 #define STM32_FLASH_CR      0x10
  46 #define STM32_FLASH_AR      0x14
  47 #define STM32_FLASH_OBR     0x1C
  48 #define STM32_FLASH_WRPR    0x20
  49
  50 /* TODO: Check if code using these really should be hard coded to bank 0.
  51  * There are valid cases, on dual flash devices the protection of the
  52  * second bank is done on the bank0 reg's. */
  53 #define STM32_FLASH_ACR_B0     0x40022000
  54 #define STM32_FLASH_KEYR_B0    0x40022004
  55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
  56 #define STM32_FLASH_SR_B0      0x4002200C
  57 #define STM32_FLASH_CR_B0      0x40022010
  58 #define STM32_FLASH_AR_B0      0x40022014
  59 #define STM32_FLASH_OBR_B0     0x4002201C
  60 #define STM32_FLASH_WRPR_B0    0x40022020
  61
  62 /* option byte location */
  63
  64 #define STM32_OB_RDP            0x1FFFF800
  65 #define STM32_OB_USER           0x1FFFF802
  66 #define STM32_OB_DATA0          0x1FFFF804
  67 #define STM32_OB_DATA1          0x1FFFF806
  68 #define STM32_OB_WRP0           0x1FFFF808
  69 #define STM32_OB_WRP1           0x1FFFF80A
  70 #define STM32_OB_WRP2           0x1FFFF80C
  71 #define STM32_OB_WRP3           0x1FFFF80E
  72
  73 /* FLASH_CR register bits */
  74
  75 #define FLASH_PG                (1 << 0)
  76 #define FLASH_PER               (1 << 1)
  77 #define FLASH_MER               (1 << 2)
  78 #define FLASH_OPTPG             (1 << 4)
  79 #define FLASH_OPTER             (1 << 5)
  80 #define FLASH_STRT              (1 << 6)
  81 #define FLASH_LOCK              (1 << 7)
  82 #define FLASH_OPTWRE    (1 << 9)
  83
  84 /* FLASH_SR register bits */
  85
  86 #define FLASH_BSY               (1 << 0)
  87 #define FLASH_PGERR             (1 << 2)
  88 #define FLASH_WRPRTERR  (1 << 4)
  89 #define FLASH_EOP               (1 << 5)
  90
  91 /* STM32_FLASH_OBR bit definitions (reading) */
  92
  93 #define OPT_ERROR               0
  94 #define OPT_READOUT             1
  95 #define OPT_RDWDGSW             2
  96 #define OPT_RDRSTSTOP   3
  97 #define OPT_RDRSTSTDBY  4
  98 #define OPT_BFB2                5       /* dual flash bank only */
  99
 100 /* register unlock keys */
 101
 102 #define KEY1                    0x45670123
 103 #define KEY2                    0xCDEF89AB
 104
 105 /* timeout values */
 106
 107 #define FLASH_WRITE_TIMEOUT 10
 108 #define FLASH_ERASE_TIMEOUT 100
 109
 110 struct stm32x_options {
 111         uint16_t RDP;
 112         uint16_t user_options;
 113         uint16_t user_data;
 114         uint16_t protection[4];
 115 };
 116
 117 struct stm32x_flash_bank {
 118         struct stm32x_options option_bytes;
 119         int ppage_size;
 120         int probed;
 121
 122         bool has_dual_banks;
 123         /* used to access dual flash bank stm32xl */
 124         uint32_t register_base;
 125         uint16_t default_rdp;
 126         int user_data_offset;
 127 };
 128
 129 static int stm32x_mass_erase(struct flash_bank *bank);
 130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
 131 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 132                 uint32_t offset, uint32_t count);
 133
 134 /* flash bank stm32x <base> <size> 0 0 <target#>
 135  */
 136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 137 {
 138         struct stm32x_flash_bank *stm32x_info;
 139
 140         if (CMD_ARGC < 6)
 141                 return ERROR_COMMAND_SYNTAX_ERROR;
 142
 143         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 144
 145         bank->driver_priv = stm32x_info;
 146         stm32x_info->probed = 0;
 147         stm32x_info->has_dual_banks = false;
 148         stm32x_info->register_base = FLASH_REG_BASE_B0;
 149
 150         return ERROR_OK;
 151 }
 152
 153 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 154 {
 155         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 156         return reg + stm32x_info->register_base;
 157 }
 158
 159 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 160 {
 161         struct target *target = bank->target;
 162         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 163 }
 164
 165 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 166 {
 167         struct target *target = bank->target;
 168         uint32_t status;
 169         int retval = ERROR_OK;
 170
 171         /* wait for busy to clear */
 172         for (;;) {
 173                 retval = stm32x_get_flash_status(bank, &status);
 174                 if (retval != ERROR_OK)
 175                         return retval;
 176                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 177                 if ((status & FLASH_BSY) == 0)
 178                         break;
 179                 if (timeout-- <= 0) {
 180                         LOG_ERROR("timed out waiting for flash");
 181                         return ERROR_FAIL;
 182                 }
 183                 alive_sleep(1);
 184         }
 185
 186         if (status & FLASH_WRPRTERR) {
 187                 LOG_ERROR("stm32x device protected");
 188                 retval = ERROR_FAIL;
 189         }
 190
 191         if (status & FLASH_PGERR) {
 192                 LOG_ERROR("stm32x device programming failed");
 193                 retval = ERROR_FAIL;
 194         }
 195
 196         /* Clear but report errors */
 197         if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
 198                 /* If this operation fails, we ignore it and report the original
 199                  * retval
 200                  */
 201                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 202                                 FLASH_WRPRTERR | FLASH_PGERR);
 203         }
 204         return retval;
 205 }
 206
 207 int stm32x_check_operation_supported(struct flash_bank *bank)
 208 {
 209         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 210
 211         /* if we have a dual flash bank device then
 212          * we need to perform option byte stuff on bank0 only */
 213         if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
 214                 LOG_ERROR("Option Byte Operation's must use bank0");
 215                 return ERROR_FLASH_OPERATION_FAILED;
 216         }
 217
 218         return ERROR_OK;
 219 }
 220
 221 static int stm32x_read_options(struct flash_bank *bank)
 222 {
 223         uint32_t optiondata;
 224         struct stm32x_flash_bank *stm32x_info = NULL;
 225         struct target *target = bank->target;
 226
 227         stm32x_info = bank->driver_priv;
 228
 229         /* read current option bytes */
 230         int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
 231         if (retval != ERROR_OK)
 232                 return retval;
 233
 234         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF0 | ((optiondata >> 2) & 0x0f);
 235         stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
 236         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 237
 238         if (optiondata & (1 << OPT_READOUT))
 239                 LOG_INFO("Device Security Bit Set");
 240
 241         /* each bit refers to a 4bank protection */
 242         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 247         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 248         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 249         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 250
 251         return ERROR_OK;
 252 }
 253
 254 static int stm32x_erase_options(struct flash_bank *bank)
 255 {
 256         struct stm32x_flash_bank *stm32x_info = NULL;
 257         struct target *target = bank->target;
 258
 259         stm32x_info = bank->driver_priv;
 260
 261         /* read current options */
 262         stm32x_read_options(bank);
 263
 264         /* unlock flash registers */
 265         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 266         if (retval != ERROR_OK)
 267                 return retval;
 268
 269         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 270         if (retval != ERROR_OK)
 271                 return retval;
 272
 273         /* unlock option flash registers */
 274         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 275         if (retval != ERROR_OK)
 276                 return retval;
 277         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 278         if (retval != ERROR_OK)
 279                 return retval;
 280
 281         /* erase option bytes */
 282         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
 283         if (retval != ERROR_OK)
 284                 return retval;
 285         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 286         if (retval != ERROR_OK)
 287                 return retval;
 288
 289         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 290         if (retval != ERROR_OK)
 291                 return retval;
 292
 293         /* clear readout protection and complementary option bytes
 294          * this will also force a device unlock if set */
 295         stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
 296
 297         return ERROR_OK;
 298 }
 299
 300 static int stm32x_write_options(struct flash_bank *bank)
 301 {
 302         struct stm32x_flash_bank *stm32x_info = NULL;
 303         struct target *target = bank->target;
 304
 305         stm32x_info = bank->driver_priv;
 306
 307         /* unlock flash registers */
 308         int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
 309         if (retval != ERROR_OK)
 310                 return retval;
 311         retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
 312         if (retval != ERROR_OK)
 313                 return retval;
 314
 315         /* unlock option flash registers */
 316         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
 317         if (retval != ERROR_OK)
 318                 return retval;
 319         retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
 320         if (retval != ERROR_OK)
 321                 return retval;
 322
 323         /* program option bytes */
 324         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
 325         if (retval != ERROR_OK)
 326                 return retval;
 327
 328         uint8_t opt_bytes[16];
 329
 330         target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
 331         target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
 332         target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
 333         target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
 334         target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
 335         target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
 336         target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
 337         target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
 338
 339         uint32_t offset = STM32_OB_RDP - bank->base;
 340         retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
 341         if (retval != ERROR_OK) {
 342                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 343                         LOG_ERROR("working area required to erase options bytes");
 344                 return retval;
 345         }
 346
 347         retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
 348         if (retval != ERROR_OK)
 349                 return retval;
 350
 351         return ERROR_OK;
 352 }
 353
 354 static int stm32x_protect_check(struct flash_bank *bank)
 355 {
 356         struct target *target = bank->target;
 357         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 358
 359         uint32_t protection;
 360         int i, s;
 361         int num_bits;
 362         int set;
 363
 364         if (target->state != TARGET_HALTED) {
 365                 LOG_ERROR("Target not halted");
 366                 return ERROR_TARGET_NOT_HALTED;
 367         }
 368
 369         int retval = stm32x_check_operation_supported(bank);
 370         if (ERROR_OK != retval)
 371                 return retval;
 372
 373         /* medium density - each bit refers to a 4bank protection
 374          * high density - each bit refers to a 2bank protection */
 375         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 376         if (retval != ERROR_OK)
 377                 return retval;
 378
 379         /* medium density - each protection bit is for 4 * 1K pages
 380          * high density - each protection bit is for 2 * 2K pages */
 381         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 382
 383         if (stm32x_info->ppage_size == 2) {
 384                 /* high density flash/connectivity line protection */
 385
 386                 set = 1;
 387
 388                 if (protection & (1 << 31))
 389                         set = 0;
 390
 391                 /* bit 31 controls sector 62 - 255 protection for high density
 392                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 393                 for (s = 62; s < bank->num_sectors; s++)
 394                         bank->sectors[s].is_protected = set;
 395
 396                 if (bank->num_sectors > 61)
 397                         num_bits = 31;
 398
 399                 for (i = 0; i < num_bits; i++) {
 400                         set = 1;
 401
 402                         if (protection & (1 << i))
 403                                 set = 0;
 404
 405                         for (s = 0; s < stm32x_info->ppage_size; s++)
 406                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 407                 }
 408         } else {
 409                 /* low/medium density flash protection */
 410                 for (i = 0; i < num_bits; i++) {
 411                         set = 1;
 412
 413                         if (protection & (1 << i))
 414                                 set = 0;
 415
 416                         for (s = 0; s < stm32x_info->ppage_size; s++)
 417                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 418                 }
 419         }
 420
 421         return ERROR_OK;
 422 }
 423
 424 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 425 {
 426         struct target *target = bank->target;
 427         int i;
 428
 429         if (bank->target->state != TARGET_HALTED) {
 430                 LOG_ERROR("Target not halted");
 431                 return ERROR_TARGET_NOT_HALTED;
 432         }
 433
 434         if ((first == 0) && (last == (bank->num_sectors - 1)))
 435                 return stm32x_mass_erase(bank);
 436
 437         /* unlock flash registers */
 438         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 439         if (retval != ERROR_OK)
 440                 return retval;
 441         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 442         if (retval != ERROR_OK)
 443                 return retval;
 444
 445         for (i = first; i <= last; i++) {
 446                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 447                 if (retval != ERROR_OK)
 448                         return retval;
 449                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 450                                 bank->base + bank->sectors[i].offset);
 451                 if (retval != ERROR_OK)
 452                         return retval;
 453                 retval = target_write_u32(target,
 454                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 455                 if (retval != ERROR_OK)
 456                         return retval;
 457
 458                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 459                 if (retval != ERROR_OK)
 460                         return retval;
 461
 462                 bank->sectors[i].is_erased = 1;
 463         }
 464
 465         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 466         if (retval != ERROR_OK)
 467                 return retval;
 468
 469         return ERROR_OK;
 470 }
 471
 472 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 473 {
 474         struct stm32x_flash_bank *stm32x_info = NULL;
 475         struct target *target = bank->target;
 476         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 477         int i, reg, bit;
 478         int status;
 479         uint32_t protection;
 480
 481         stm32x_info = bank->driver_priv;
 482
 483         if (target->state != TARGET_HALTED) {
 484                 LOG_ERROR("Target not halted");
 485                 return ERROR_TARGET_NOT_HALTED;
 486         }
 487
 488         int retval = stm32x_check_operation_supported(bank);
 489         if (ERROR_OK != retval)
 490                 return retval;
 491
 492         if ((first % stm32x_info->ppage_size) != 0) {
 493                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 494                                 stm32x_info->ppage_size);
 495                 first = first - (first % stm32x_info->ppage_size);
 496         }
 497         if (((last + 1) % stm32x_info->ppage_size) != 0) {
 498                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 499                                 stm32x_info->ppage_size);
 500                 last++;
 501                 last = last - (last % stm32x_info->ppage_size);
 502                 last--;
 503         }
 504
 505         /* medium density - each bit refers to a 4bank protection
 506          * high density - each bit refers to a 2bank protection */
 507         retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
 508         if (retval != ERROR_OK)
 509                 return retval;
 510
 511         prot_reg[0] = (uint16_t)protection;
 512         prot_reg[1] = (uint16_t)(protection >> 8);
 513         prot_reg[2] = (uint16_t)(protection >> 16);
 514         prot_reg[3] = (uint16_t)(protection >> 24);
 515
 516         if (stm32x_info->ppage_size == 2) {
 517                 /* high density flash */
 518
 519                 /* bit 7 controls sector 62 - 255 protection */
 520                 if (last > 61) {
 521                         if (set)
 522                                 prot_reg[3] &= ~(1 << 7);
 523                         else
 524                                 prot_reg[3] |= (1 << 7);
 525                 }
 526
 527                 if (first > 61)
 528                         first = 62;
 529                 if (last > 61)
 530                         last = 61;
 531
 532                 for (i = first; i <= last; i++) {
 533                         reg = (i / stm32x_info->ppage_size) / 8;
 534                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 535
 536                         if (set)
 537                                 prot_reg[reg] &= ~(1 << bit);
 538                         else
 539                                 prot_reg[reg] |= (1 << bit);
 540                 }
 541         } else {
 542                 /* medium density flash */
 543                 for (i = first; i <= last; i++) {
 544                         reg = (i / stm32x_info->ppage_size) / 8;
 545                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 546
 547                         if (set)
 548                                 prot_reg[reg] &= ~(1 << bit);
 549                         else
 550                                 prot_reg[reg] |= (1 << bit);
 551                 }
 552         }
 553
 554         status = stm32x_erase_options(bank);
 555         if (status != ERROR_OK)
 556                 return status;
 557
 558         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 559         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 560         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 561         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 562
 563         return stm32x_write_options(bank);
 564 }
 565
 566 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 567                 uint32_t offset, uint32_t count)
 568 {
 569         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 570         struct target *target = bank->target;
 571         uint32_t buffer_size = 16384;
 572         struct working_area *write_algorithm;
 573         struct working_area *source;
 574         uint32_t address = bank->base + offset;
 575         struct reg_param reg_params[5];
 576         struct armv7m_algorithm armv7m_info;
 577         int retval = ERROR_OK;
 578
 579         /* see contrib/loaders/flash/stm32f1x.S for src */
 580
 581         static const uint8_t stm32x_flash_write_code[] = {
 582                 /* #define STM32_FLASH_SR_OFFSET 0x0C */
 583                 /* wait_fifo: */
 584                         0x16, 0x68,   /* ldr   r6, [r2, #0] */
 585                         0x00, 0x2e,   /* cmp   r6, #0 */
 586                         0x18, 0xd0,   /* beq   exit */
 587                         0x55, 0x68,   /* ldr   r5, [r2, #4] */
 588                         0xb5, 0x42,   /* cmp   r5, r6 */
 589                         0xf9, 0xd0,   /* beq   wait_fifo */
 590                         0x2e, 0x88,   /* ldrh  r6, [r5, #0] */
 591                         0x26, 0x80,   /* strh  r6, [r4, #0] */
 592                         0x02, 0x35,   /* adds  r5, #2 */
 593                         0x02, 0x34,   /* adds  r4, #2 */
 594                 /* busy: */
 595                         0xc6, 0x68,   /* ldr   r6, [r0, #STM32_FLASH_SR_OFFSET] */
 596                         0x01, 0x27,   /* movs  r7, #1 */
 597                         0x3e, 0x42,   /* tst   r6, r7 */
 598                         0xfb, 0xd1,   /* bne   busy */
 599                         0x14, 0x27,   /* movs  r7, #0x14 */
 600                         0x3e, 0x42,   /* tst   r6, r7 */
 601                         0x08, 0xd1,   /* bne   error */
 602                         0x9d, 0x42,   /* cmp   r5, r3 */
 603                         0x01, 0xd3,   /* bcc   no_wrap */
 604                         0x15, 0x46,   /* mov   r5, r2 */
 605                         0x08, 0x35,   /* adds  r5, #8 */
 606                 /* no_wrap: */
 607                         0x55, 0x60,   /* str   r5, [r2, #4] */
 608                         0x01, 0x39,   /* subs  r1, r1, #1 */
 609                         0x00, 0x29,   /* cmp   r1, #0 */
 610                         0x02, 0xd0,   /* beq   exit */
 611                         0xe5, 0xe7,   /* b     wait_fifo */
 612                 /* error: */
 613                         0x00, 0x20,   /* movs  r0, #0 */
 614                         0x50, 0x60,   /* str   r0, [r2, #4] */
 615                 /* exit: */
 616                         0x30, 0x46,   /* mov   r0, r6 */
 617                         0x00, 0xbe,   /* bkpt  #0 */
 618         };
 619
 620         /* flash write code */
 621         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 622                         &write_algorithm) != ERROR_OK) {
 623                 LOG_WARNING("no working area available, can't do block memory writes");
 624                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 625         };
 626
 627         retval = target_write_buffer(target, write_algorithm->address,
 628                         sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
 629         if (retval != ERROR_OK)
 630                 return retval;
 631
 632         /* memory buffer */
 633         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
 634                 buffer_size /= 2;
 635                 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
 636                 if (buffer_size <= 256) {
 637                         /* we already allocated the writing code, but failed to get a
 638                          * buffer, free the algorithm */
 639                         target_free_working_area(target, write_algorithm);
 640
 641                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 642                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 643                 }
 644         };
 645
 646         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
 647         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* count (halfword-16bit) */
 648         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* buffer start */
 649         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* buffer end */
 650         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
 651
 652         buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
 653         buf_set_u32(reg_params[1].value, 0, 32, count);
 654         buf_set_u32(reg_params[2].value, 0, 32, source->address);
 655         buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 656         buf_set_u32(reg_params[4].value, 0, 32, address);
 657
 658         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 659         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 660
 661         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 662                         0, NULL,
 663                         5, reg_params,
 664                         source->address, source->size,
 665                         write_algorithm->address, 0,
 666                         &armv7m_info);
 667
 668         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 669                 LOG_ERROR("flash write failed at address 0x%"PRIx32,
 670                                 buf_get_u32(reg_params[4].value, 0, 32));
 671
 672                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 673                         LOG_ERROR("flash memory not erased before writing");
 674                         /* Clear but report errors */
 675                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 676                 }
 677
 678                 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 679                         LOG_ERROR("flash memory write protected");
 680                         /* Clear but report errors */
 681                         target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 682                 }
 683         }
 684
 685         target_free_working_area(target, source);
 686         target_free_working_area(target, write_algorithm);
 687
 688         destroy_reg_param(&reg_params[0]);
 689         destroy_reg_param(&reg_params[1]);
 690         destroy_reg_param(&reg_params[2]);
 691         destroy_reg_param(&reg_params[3]);
 692         destroy_reg_param(&reg_params[4]);
 693
 694         return retval;
 695 }
 696
 697 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 698                 uint32_t offset, uint32_t count)
 699 {
 700         struct target *target = bank->target;
 701         uint8_t *new_buffer = NULL;
 702
 703         if (bank->target->state != TARGET_HALTED) {
 704                 LOG_ERROR("Target not halted");
 705                 return ERROR_TARGET_NOT_HALTED;
 706         }
 707
 708         if (offset & 0x1) {
 709                 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 710                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 711         }
 712
 713         /* If there's an odd number of bytes, the data has to be padded. Duplicate
 714          * the buffer and use the normal code path with a single block write since
 715          * it's probably cheaper than to special case the last odd write using
 716          * discrete accesses. */
 717         if (count & 1) {
 718                 new_buffer = malloc(count + 1);
 719                 if (new_buffer == NULL) {
 720                         LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 721                         return ERROR_FAIL;
 722                 }
 723                 LOG_INFO("odd number of bytes to write, padding with 0xff");
 724                 buffer = memcpy(new_buffer, buffer, count);
 725                 buffer[count++] = 0xff;
 726         }
 727
 728         uint32_t words_remaining = count / 2;
 729         int retval, retval2;
 730
 731         /* unlock flash registers */
 732         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 733         if (retval != ERROR_OK)
 734                 goto cleanup;
 735         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 736         if (retval != ERROR_OK)
 737                 goto cleanup;
 738
 739         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 740         if (retval != ERROR_OK)
 741                 goto cleanup;
 742
 743         /* try using a block write */
 744         retval = stm32x_write_block(bank, buffer, offset, words_remaining);
 745
 746         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 747                 /* if block write failed (no sufficient working area),
 748                  * we use normal (slow) single halfword accesses */
 749                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 750
 751                 while (words_remaining > 0) {
 752                         uint16_t value;
 753                         memcpy(&value, buffer, sizeof(uint16_t));
 754
 755                         retval = target_write_u16(target, bank->base + offset, value);
 756                         if (retval != ERROR_OK)
 757                                 goto reset_pg_and_lock;
 758
 759                         retval = stm32x_wait_status_busy(bank, 5);
 760                         if (retval != ERROR_OK)
 761                                 goto reset_pg_and_lock;
 762
 763                         words_remaining--;
 764                         buffer += 2;
 765                         offset += 2;
 766                 }
 767         }
 768
 769 reset_pg_and_lock:
 770         retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 771         if (retval == ERROR_OK)
 772                 retval = retval2;
 773
 774 cleanup:
 775         if (new_buffer)
 776                 free(new_buffer);
 777
 778         return retval;
 779 }
 780
 781 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 782 {
 783         /* This check the device CPUID core register to detect
 784          * the M0 from the M3 devices. */
 785
 786         struct target *target = bank->target;
 787         uint32_t cpuid, device_id_register = 0;
 788
 789         /* Get the CPUID from the ARM Core
 790          * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
 791         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 792         if (retval != ERROR_OK)
 793                 return retval;
 794
 795         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 796                 /* 0xC20 is M0 devices */
 797                 device_id_register = 0x40015800;
 798         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 799                 /* 0xC23 is M3 devices */
 800                 device_id_register = 0xE0042000;
 801         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 802                 /* 0xC24 is M4 devices */
 803                 device_id_register = 0xE0042000;
 804         } else {
 805                 LOG_ERROR("Cannot identify target as a stm32x");
 806                 return ERROR_FAIL;
 807         }
 808
 809         /* read stm32 device id register */
 810         retval = target_read_u32(target, device_id_register, device_id);
 811         if (retval != ERROR_OK)
 812                 return retval;
 813
 814         return retval;
 815 }
 816
 817 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 818 {
 819         struct target *target = bank->target;
 820         uint32_t cpuid, flash_size_reg;
 821
 822         int retval = target_read_u32(target, 0xE000ED00, &cpuid);
 823         if (retval != ERROR_OK)
 824                 return retval;
 825
 826         if (((cpuid >> 4) & 0xFFF) == 0xC20) {
 827                 /* 0xC20 is M0 devices */
 828                 flash_size_reg = 0x1FFFF7CC;
 829         } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
 830                 /* 0xC23 is M3 devices */
 831                 flash_size_reg = 0x1FFFF7E0;
 832         } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
 833                 /* 0xC24 is M4 devices */
 834                 flash_size_reg = 0x1FFFF7CC;
 835         } else {
 836                 LOG_ERROR("Cannot identify target as a stm32x");
 837                 return ERROR_FAIL;
 838         }
 839
 840         retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
 841         if (retval != ERROR_OK)
 842                 return retval;
 843
 844         return retval;
 845 }
 846
 847 static int stm32x_probe(struct flash_bank *bank)
 848 {
 849         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 850         int i;
 851         uint16_t flash_size_in_kb;
 852         uint16_t max_flash_size_in_kb;
 853         uint32_t device_id;
 854         int page_size;
 855         uint32_t base_address = 0x08000000;
 856
 857         stm32x_info->probed = 0;
 858         stm32x_info->register_base = FLASH_REG_BASE_B0;
 859         stm32x_info->user_data_offset = 10;
 860
 861         /* default factory protection level */
 862         stm32x_info->default_rdp = 0x5AA5;
 863
 864         /* read stm32 device id register */
 865         int retval = stm32x_get_device_id(bank, &device_id);
 866         if (retval != ERROR_OK)
 867                 return retval;
 868
 869         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 870
 871         /* set page size, protection granularity and max flash size depending on family */
 872         switch (device_id & 0xfff) {
 873         case 0x410: /* medium density */
 874                 page_size = 1024;
 875                 stm32x_info->ppage_size = 4;
 876                 max_flash_size_in_kb = 128;
 877                 break;
 878         case 0x412: /* low density */
 879                 page_size = 1024;
 880                 stm32x_info->ppage_size = 4;
 881                 max_flash_size_in_kb = 32;
 882                 break;
 883         case 0x414: /* high density */
 884                 page_size = 2048;
 885                 stm32x_info->ppage_size = 2;
 886                 max_flash_size_in_kb = 512;
 887                 break;
 888         case 0x418: /* connectivity line density */
 889                 page_size = 2048;
 890                 stm32x_info->ppage_size = 2;
 891                 max_flash_size_in_kb = 256;
 892                 break;
 893         case 0x420: /* value line density */
 894                 page_size = 1024;
 895                 stm32x_info->ppage_size = 4;
 896                 max_flash_size_in_kb = 128;
 897                 break;
 898         case 0x422: /* stm32f30x */
 899                 page_size = 2048;
 900                 stm32x_info->ppage_size = 2;
 901                 max_flash_size_in_kb = 256;
 902                 stm32x_info->user_data_offset = 16;
 903                 stm32x_info->default_rdp = 0x55AA;
 904                 break;
 905         case 0x428: /* value line High density */
 906                 page_size = 2048;
 907                 stm32x_info->ppage_size = 4;
 908                 max_flash_size_in_kb = 128;
 909                 break;
 910         case 0x430: /* xl line density (dual flash banks) */
 911                 page_size = 2048;
 912                 stm32x_info->ppage_size = 2;
 913                 max_flash_size_in_kb = 1024;
 914                 stm32x_info->has_dual_banks = true;
 915                 break;
 916         case 0x432: /* stm32f37x */
 917                 page_size = 2048;
 918                 stm32x_info->ppage_size = 2;
 919                 max_flash_size_in_kb = 256;
 920                 stm32x_info->user_data_offset = 16;
 921                 stm32x_info->default_rdp = 0x55AA;
 922                 break;
 923         case 0x440: /* stm32f0x */
 924                 page_size = 1024;
 925                 stm32x_info->ppage_size = 4;
 926                 max_flash_size_in_kb = 64;
 927                 stm32x_info->user_data_offset = 16;
 928                 stm32x_info->default_rdp = 0x55AA;
 929                 break;
 930         default:
 931                 LOG_WARNING("Cannot identify target as a STM32 family.");
 932                 return ERROR_FAIL;
 933         }
 934
 935         /* get flash size from target. */
 936         retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 937
 938         /* failed reading flash size or flash size invalid (early silicon),
 939          * default to max target family */
 940         if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
 941                 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
 942                         max_flash_size_in_kb);
 943                 flash_size_in_kb = max_flash_size_in_kb;
 944         }
 945
 946         if (stm32x_info->has_dual_banks) {
 947                 /* split reported size into matching bank */
 948                 if (bank->base != 0x08080000) {
 949                         /* bank 0 will be fixed 512k */
 950                         flash_size_in_kb = 512;
 951                 } else {
 952                         flash_size_in_kb -= 512;
 953                         /* bank1 also uses a register offset */
 954                         stm32x_info->register_base = FLASH_REG_BASE_B1;
 955                         base_address = 0x08080000;
 956                 }
 957         }
 958
 959         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 960
 961         /* did we assign flash size? */
 962         assert(flash_size_in_kb != 0xffff);
 963
 964         /* calculate numbers of pages */
 965         int num_pages = flash_size_in_kb * 1024 / page_size;
 966
 967         /* check that calculation result makes sense */
 968         assert(num_pages > 0);
 969
 970         if (bank->sectors) {
 971                 free(bank->sectors);
 972                 bank->sectors = NULL;
 973         }
 974
 975         bank->base = base_address;
 976         bank->size = (num_pages * page_size);
 977         bank->num_sectors = num_pages;
 978         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 979
 980         for (i = 0; i < num_pages; i++) {
 981                 bank->sectors[i].offset = i * page_size;
 982                 bank->sectors[i].size = page_size;
 983                 bank->sectors[i].is_erased = -1;
 984                 bank->sectors[i].is_protected = 1;
 985         }
 986
 987         stm32x_info->probed = 1;
 988
 989         return ERROR_OK;
 990 }
 991
 992 static int stm32x_auto_probe(struct flash_bank *bank)
 993 {
 994         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 995         if (stm32x_info->probed)
 996                 return ERROR_OK;
 997         return stm32x_probe(bank);
 998 }
 999
1000 #if 0
1001 COMMAND_HANDLER(stm32x_handle_part_id_command)
1002 {
1003         return ERROR_OK;
1004 }
1005 #endif
1006
1007 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1008 {
1009         uint32_t device_id;
1010         int printed;
1011
1012                 /* read stm32 device id register */
1013         int retval = stm32x_get_device_id(bank, &device_id);
1014         if (retval != ERROR_OK)
1015                 return retval;
1016
1017         if ((device_id & 0xfff) == 0x410) {
1018                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1019                 buf += printed;
1020                 buf_size -= printed;
1021
1022                 switch (device_id >> 16) {
1023                         case 0x0000:
1024                                 snprintf(buf, buf_size, "A");
1025                                 break;
1026
1027                         case 0x2000:
1028                                 snprintf(buf, buf_size, "B");
1029                                 break;
1030
1031                         case 0x2001:
1032                                 snprintf(buf, buf_size, "Z");
1033                                 break;
1034
1035                         case 0x2003:
1036                                 snprintf(buf, buf_size, "Y");
1037                                 break;
1038
1039                         default:
1040                                 snprintf(buf, buf_size, "unknown");
1041                                 break;
1042                 }
1043         } else if ((device_id & 0xfff) == 0x412) {
1044                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1045                 buf += printed;
1046                 buf_size -= printed;
1047
1048                 switch (device_id >> 16) {
1049                         case 0x1000:
1050                                 snprintf(buf, buf_size, "A");
1051                                 break;
1052
1053                         default:
1054                                 snprintf(buf, buf_size, "unknown");
1055                                 break;
1056                 }
1057         } else if ((device_id & 0xfff) == 0x414) {
1058                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1059                 buf += printed;
1060                 buf_size -= printed;
1061
1062                 switch (device_id >> 16) {
1063                         case 0x1000:
1064                                 snprintf(buf, buf_size, "A");
1065                                 break;
1066
1067                         case 0x1001:
1068                                 snprintf(buf, buf_size, "Z");
1069                                 break;
1070
1071                         default:
1072                                 snprintf(buf, buf_size, "unknown");
1073                                 break;
1074                 }
1075         } else if ((device_id & 0xfff) == 0x418) {
1076                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1077                 buf += printed;
1078                 buf_size -= printed;
1079
1080                 switch (device_id >> 16) {
1081                         case 0x1000:
1082                                 snprintf(buf, buf_size, "A");
1083                                 break;
1084
1085                         case 0x1001:
1086                                 snprintf(buf, buf_size, "Z");
1087                                 break;
1088
1089                         default:
1090                                 snprintf(buf, buf_size, "unknown");
1091                                 break;
1092                 }
1093         } else if ((device_id & 0xfff) == 0x420) {
1094                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1095                 buf += printed;
1096                 buf_size -= printed;
1097
1098                 switch (device_id >> 16) {
1099                         case 0x1000:
1100                                 snprintf(buf, buf_size, "A");
1101                                 break;
1102
1103                         case 0x1001:
1104                                 snprintf(buf, buf_size, "Z");
1105                                 break;
1106
1107                         default:
1108                                 snprintf(buf, buf_size, "unknown");
1109                                 break;
1110                 }
1111         } else if ((device_id & 0xfff) == 0x422) {
1112                 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1113                 buf += printed;
1114                 buf_size -= printed;
1115
1116                 switch (device_id >> 16) {
1117                         case 0x1000:
1118                                 snprintf(buf, buf_size, "A");
1119                                 break;
1120
1121                         case 0x1001:
1122                                 snprintf(buf, buf_size, "Z");
1123                                 break;
1124
1125                         case 0x2000:
1126                                 snprintf(buf, buf_size, "B");
1127                                 break;
1128
1129                         default:
1130                                 snprintf(buf, buf_size, "unknown");
1131                                 break;
1132                 }
1133         } else if ((device_id & 0xfff) == 0x428) {
1134                 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1135                 buf += printed;
1136                 buf_size -= printed;
1137
1138                 switch (device_id >> 16) {
1139                         case 0x1000:
1140                                 snprintf(buf, buf_size, "A");
1141                                 break;
1142
1143                         case 0x1001:
1144                                 snprintf(buf, buf_size, "Z");
1145                                 break;
1146
1147                         default:
1148                                 snprintf(buf, buf_size, "unknown");
1149                                 break;
1150                 }
1151         } else if ((device_id & 0xfff) == 0x430) {
1152                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1153                 buf += printed;
1154                 buf_size -= printed;
1155
1156                 switch (device_id >> 16) {
1157                         case 0x1000:
1158                                 snprintf(buf, buf_size, "A");
1159                                 break;
1160
1161                         default:
1162                                 snprintf(buf, buf_size, "unknown");
1163                                 break;
1164                 }
1165         } else if ((device_id & 0xfff) == 0x432) {
1166                 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1167                 buf += printed;
1168                 buf_size -= printed;
1169
1170                 switch (device_id >> 16) {
1171                         case 0x1000:
1172                                 snprintf(buf, buf_size, "A");
1173                                 break;
1174
1175                         case 0x2000:
1176                                 snprintf(buf, buf_size, "B");
1177                                 break;
1178
1179                         default:
1180                                 snprintf(buf, buf_size, "unknown");
1181                                 break;
1182                 }
1183         } else if ((device_id & 0xfff) == 0x440) {
1184                 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1185                 buf += printed;
1186                 buf_size -= printed;
1187
1188                 switch (device_id >> 16) {
1189                         case 0x1000:
1190                                 snprintf(buf, buf_size, "1.0");
1191                                 break;
1192
1193                         case 0x2000:
1194                                 snprintf(buf, buf_size, "2.0");
1195                                 break;
1196
1197                         default:
1198                                 snprintf(buf, buf_size, "unknown");
1199                                 break;
1200                 }
1201         } else {
1202                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1203                 return ERROR_FAIL;
1204         }
1205
1206         return ERROR_OK;
1207 }
1208
1209 COMMAND_HANDLER(stm32x_handle_lock_command)
1210 {
1211         struct target *target = NULL;
1212         struct stm32x_flash_bank *stm32x_info = NULL;
1213
1214         if (CMD_ARGC < 1)
1215                 return ERROR_COMMAND_SYNTAX_ERROR;
1216
1217         struct flash_bank *bank;
1218         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1219         if (ERROR_OK != retval)
1220                 return retval;
1221
1222         stm32x_info = bank->driver_priv;
1223
1224         target = bank->target;
1225
1226         if (target->state != TARGET_HALTED) {
1227                 LOG_ERROR("Target not halted");
1228                 return ERROR_TARGET_NOT_HALTED;
1229         }
1230
1231         retval = stm32x_check_operation_supported(bank);
1232         if (ERROR_OK != retval)
1233                 return retval;
1234
1235         if (stm32x_erase_options(bank) != ERROR_OK) {
1236                 command_print(CMD_CTX, "stm32x failed to erase options");
1237                 return ERROR_OK;
1238         }
1239
1240         /* set readout protection */
1241         stm32x_info->option_bytes.RDP = 0;
1242
1243         if (stm32x_write_options(bank) != ERROR_OK) {
1244                 command_print(CMD_CTX, "stm32x failed to lock device");
1245                 return ERROR_OK;
1246         }
1247
1248         command_print(CMD_CTX, "stm32x locked");
1249
1250         return ERROR_OK;
1251 }
1252
1253 COMMAND_HANDLER(stm32x_handle_unlock_command)
1254 {
1255         struct target *target = NULL;
1256
1257         if (CMD_ARGC < 1)
1258                 return ERROR_COMMAND_SYNTAX_ERROR;
1259
1260         struct flash_bank *bank;
1261         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1262         if (ERROR_OK != retval)
1263                 return retval;
1264
1265         target = bank->target;
1266
1267         if (target->state != TARGET_HALTED) {
1268                 LOG_ERROR("Target not halted");
1269                 return ERROR_TARGET_NOT_HALTED;
1270         }
1271
1272         retval = stm32x_check_operation_supported(bank);
1273         if (ERROR_OK != retval)
1274                 return retval;
1275
1276         if (stm32x_erase_options(bank) != ERROR_OK) {
1277                 command_print(CMD_CTX, "stm32x failed to unlock device");
1278                 return ERROR_OK;
1279         }
1280
1281         if (stm32x_write_options(bank) != ERROR_OK) {
1282                 command_print(CMD_CTX, "stm32x failed to lock device");
1283                 return ERROR_OK;
1284         }
1285
1286         command_print(CMD_CTX, "stm32x unlocked.\n"
1287                         "INFO: a reset or power cycle is required "
1288                         "for the new settings to take effect.");
1289
1290         return ERROR_OK;
1291 }
1292
1293 COMMAND_HANDLER(stm32x_handle_options_read_command)
1294 {
1295         uint32_t optionbyte;
1296         struct target *target = NULL;
1297         struct stm32x_flash_bank *stm32x_info = NULL;
1298
1299         if (CMD_ARGC < 1)
1300                 return ERROR_COMMAND_SYNTAX_ERROR;
1301
1302         struct flash_bank *bank;
1303         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1304         if (ERROR_OK != retval)
1305                 return retval;
1306
1307         stm32x_info = bank->driver_priv;
1308
1309         target = bank->target;
1310
1311         if (target->state != TARGET_HALTED) {
1312                 LOG_ERROR("Target not halted");
1313                 return ERROR_TARGET_NOT_HALTED;
1314         }
1315
1316         retval = stm32x_check_operation_supported(bank);
1317         if (ERROR_OK != retval)
1318                 return retval;
1319
1320         retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1321         if (retval != ERROR_OK)
1322                 return retval;
1323         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1324
1325         if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1326                 command_print(CMD_CTX, "Option Byte Complement Error");
1327
1328         if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1329                 command_print(CMD_CTX, "Readout Protection On");
1330         else
1331                 command_print(CMD_CTX, "Readout Protection Off");
1332
1333         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1334                 command_print(CMD_CTX, "Software Watchdog");
1335         else
1336                 command_print(CMD_CTX, "Hardware Watchdog");
1337
1338         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1339                 command_print(CMD_CTX, "Stop: No reset generated");
1340         else
1341                 command_print(CMD_CTX, "Stop: Reset generated");
1342
1343         if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1344                 command_print(CMD_CTX, "Standby: No reset generated");
1345         else
1346                 command_print(CMD_CTX, "Standby: Reset generated");
1347
1348         if (stm32x_info->has_dual_banks) {
1349                 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1350                         command_print(CMD_CTX, "Boot: Bank 0");
1351                 else
1352                         command_print(CMD_CTX, "Boot: Bank 1");
1353         }
1354
1355         command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1356                         (optionbyte >> stm32x_info->user_data_offset) & 0xff);
1357         command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1358                         (optionbyte >> (stm32x_info->user_data_offset + 8)) & 0xff);
1359
1360         return ERROR_OK;
1361 }
1362
1363 COMMAND_HANDLER(stm32x_handle_options_write_command)
1364 {
1365         struct target *target = NULL;
1366         struct stm32x_flash_bank *stm32x_info = NULL;
1367         uint32_t optionbyte = 0xF0;
1368
1369         if (CMD_ARGC < 4)
1370                 return ERROR_COMMAND_SYNTAX_ERROR;
1371
1372         struct flash_bank *bank;
1373         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1374         if (ERROR_OK != retval)
1375                 return retval;
1376
1377         stm32x_info = bank->driver_priv;
1378
1379         target = bank->target;
1380
1381         if (target->state != TARGET_HALTED) {
1382                 LOG_ERROR("Target not halted");
1383                 return ERROR_TARGET_NOT_HALTED;
1384         }
1385
1386         retval = stm32x_check_operation_supported(bank);
1387         if (ERROR_OK != retval)
1388                 return retval;
1389
1390         /* REVISIT: ignores some options which we will display...
1391          * and doesn't insist on the specified syntax.
1392          */
1393
1394         /* OPT_RDWDGSW */
1395         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1396                 optionbyte |= (1 << 0);
1397         else    /* REVISIT must be "HWWDG" then ... */
1398                 optionbyte &= ~(1 << 0);
1399
1400         /* OPT_RDRSTSTOP */
1401         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1402                 optionbyte |= (1 << 1);
1403         else    /* REVISIT must be "RSTSTNDBY" then ... */
1404                 optionbyte &= ~(1 << 1);
1405
1406         /* OPT_RDRSTSTDBY */
1407         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1408                 optionbyte |= (1 << 2);
1409         else    /* REVISIT must be "RSTSTOP" then ... */
1410                 optionbyte &= ~(1 << 2);
1411
1412         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks) {
1413                 /* OPT_BFB2 */
1414                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1415                         optionbyte |= (1 << 3);
1416                 else
1417                         optionbyte &= ~(1 << 3);
1418         }
1419
1420         if (stm32x_erase_options(bank) != ERROR_OK) {
1421                 command_print(CMD_CTX, "stm32x failed to erase options");
1422                 return ERROR_OK;
1423         }
1424
1425         stm32x_info->option_bytes.user_options = optionbyte;
1426
1427         if (stm32x_write_options(bank) != ERROR_OK) {
1428                 command_print(CMD_CTX, "stm32x failed to write options");
1429                 return ERROR_OK;
1430         }
1431
1432         command_print(CMD_CTX, "stm32x write options complete.\n"
1433                                 "INFO: a reset or power cycle is required "
1434                                 "for the new settings to take effect.");
1435
1436         return ERROR_OK;
1437 }
1438
1439 static int stm32x_mass_erase(struct flash_bank *bank)
1440 {
1441         struct target *target = bank->target;
1442
1443         if (target->state != TARGET_HALTED) {
1444                 LOG_ERROR("Target not halted");
1445                 return ERROR_TARGET_NOT_HALTED;
1446         }
1447
1448         /* unlock option flash registers */
1449         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1450         if (retval != ERROR_OK)
1451                 return retval;
1452         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1453         if (retval != ERROR_OK)
1454                 return retval;
1455
1456         /* mass erase flash memory */
1457         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1458         if (retval != ERROR_OK)
1459                 return retval;
1460         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1461                         FLASH_MER | FLASH_STRT);
1462         if (retval != ERROR_OK)
1463                 return retval;
1464
1465         retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1466         if (retval != ERROR_OK)
1467                 return retval;
1468
1469         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1470         if (retval != ERROR_OK)
1471                 return retval;
1472
1473         return ERROR_OK;
1474 }
1475
1476 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1477 {
1478         int i;
1479
1480         if (CMD_ARGC < 1)
1481                 return ERROR_COMMAND_SYNTAX_ERROR;
1482
1483         struct flash_bank *bank;
1484         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1485         if (ERROR_OK != retval)
1486                 return retval;
1487
1488         retval = stm32x_mass_erase(bank);
1489         if (retval == ERROR_OK) {
1490                 /* set all sectors as erased */
1491                 for (i = 0; i < bank->num_sectors; i++)
1492                         bank->sectors[i].is_erased = 1;
1493
1494                 command_print(CMD_CTX, "stm32x mass erase complete");
1495         } else
1496                 command_print(CMD_CTX, "stm32x mass erase failed");
1497
1498         return retval;
1499 }
1500
1501 static const struct command_registration stm32x_exec_command_handlers[] = {
1502         {
1503                 .name = "lock",
1504                 .handler = stm32x_handle_lock_command,
1505                 .mode = COMMAND_EXEC,
1506                 .usage = "bank_id",
1507                 .help = "Lock entire flash device.",
1508         },
1509         {
1510                 .name = "unlock",
1511                 .handler = stm32x_handle_unlock_command,
1512                 .mode = COMMAND_EXEC,
1513                 .usage = "bank_id",
1514                 .help = "Unlock entire protected flash device.",
1515         },
1516         {
1517                 .name = "mass_erase",
1518                 .handler = stm32x_handle_mass_erase_command,
1519                 .mode = COMMAND_EXEC,
1520                 .usage = "bank_id",
1521                 .help = "Erase entire flash device.",
1522         },
1523         {
1524                 .name = "options_read",
1525                 .handler = stm32x_handle_options_read_command,
1526                 .mode = COMMAND_EXEC,
1527                 .usage = "bank_id",
1528                 .help = "Read and display device option byte.",
1529         },
1530         {
1531                 .name = "options_write",
1532                 .handler = stm32x_handle_options_write_command,
1533                 .mode = COMMAND_EXEC,
1534                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1535                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1536                         "('RSTSTOP'|'NORSTSTOP')",
1537                 .help = "Replace bits in device option byte.",
1538         },
1539         COMMAND_REGISTRATION_DONE
1540 };
1541
1542 static const struct command_registration stm32x_command_handlers[] = {
1543         {
1544                 .name = "stm32f1x",
1545                 .mode = COMMAND_ANY,
1546                 .help = "stm32f1x flash command group",
1547                 .usage = "",
1548                 .chain = stm32x_exec_command_handlers,
1549         },
1550         COMMAND_REGISTRATION_DONE
1551 };
1552
1553 struct flash_driver stm32f1x_flash = {
1554         .name = "stm32f1x",
1555         .commands = stm32x_command_handlers,
1556         .flash_bank_command = stm32x_flash_bank_command,
1557         .erase = stm32x_erase,
1558         .protect = stm32x_protect,
1559         .write = stm32x_write,
1560         .read = default_flash_read,
1561         .probe = stm32x_probe,
1562         .auto_probe = stm32x_auto_probe,
1563         .erase_check = default_flash_blank_check,
1564         .protect_check = stm32x_protect_check,
1565         .info = get_stm32x_info,
1566 };