git.sur5r.net Git - openocd/blob - src/flash/nor/stm32f2x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2011 Øyvind Harboe                                      *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "imp.h"
  31 #include <helper/binarybuffer.h>
  32 #include <target/algorithm.h>
  33 #include <target/armv7m.h>
  34
  35 /* Regarding performance:
  36  *
  37  * Short story - it might be best to leave the performance at
  38  * current levels.
  39  *
  40  * You may see a jump in speed if you change to using
  41  * 32bit words for the block programming.
  42  *
  43  * Its a shame you cannot use the double word as its
  44  * even faster - but you require external VPP for that mode.
  45  *
  46  * Having said all that 16bit writes give us the widest vdd
  47  * operating range, so may be worth adding a note to that effect.
  48  *
  49  */
  50
  51 /* Danger!!!! The STM32F1x and STM32F2x series actually have
  52  * quite different flash controllers.
  53  *
  54  * What's more scary is that the names of the registers and their
  55  * addresses are the same, but the actual bits and what they do are
  56  * can be very different.
  57  *
  58  * To reduce testing complexity and dangers of regressions,
  59  * a seperate file is used for stm32fx2x.
  60  *
  61  * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
  62  *
  63  * What's the protection page size???
  64  *
  65  * Tested with STM3220F-EVAL board.
  66  *
  67  * STM32F21xx series for reference.
  68  *
  69  * RM0033
  70  * http://www.st.com/internet/mcu/product/250192.jsp
  71  *
  72  * PM0059
  73  * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/PROGRAMMING_MANUAL/CD00233952.pdf
  74  *
  75  * STM32F1x series - notice that this code was copy, pasted and knocked
  76  * into a stm32f2x driver, so in case something has been converted or
  77  * bugs haven't been fixed, here are the original manuals:
  78  *
  79  * RM0008 - Reference manual
  80  *
  81  * RM0042, the Flash programming manual for low-, medium- high-density and
  82  * connectivity line STM32F10x devices
  83  *
  84  * PM0068, the Flash programming manual for XL-density STM32F10x devices.
  85  *
  86  */
  87
  88  // Erase time can be as high as 1000ms, 10x this and it's toast...
  89 #define FLASH_ERASE_TIMEOUT 10000
  90 #define FLASH_WRITE_TIMEOUT 5
  91
  92
  93 #define STM32_FLASH_BASE        0x40023c00
  94 #define STM32_FLASH_ACR         0x40023c00
  95 #define STM32_FLASH_KEYR        0x40023c04
  96 #define STM32_FLASH_OPTKEYR     0x40023c08
  97 #define STM32_FLASH_SR          0x40023c0C
  98 #define STM32_FLASH_CR          0x40023c10
  99 #define STM32_FLASH_OPTCR       0x40023c14
 100 #define STM32_FLASH_OBR         0x40023c1C
 101
 102
 103
 104 /* option byte location */
 105
 106 #define STM32_OB_RDP            0x1FFFF800
 107 #define STM32_OB_USER           0x1FFFF802
 108 #define STM32_OB_DATA0          0x1FFFF804
 109 #define STM32_OB_DATA1          0x1FFFF806
 110 #define STM32_OB_WRP0           0x1FFFF808
 111 #define STM32_OB_WRP1           0x1FFFF80A
 112 #define STM32_OB_WRP2           0x1FFFF80C
 113 #define STM32_OB_WRP3           0x1FFFF80E
 114
 115 /* FLASH_CR register bits */
 116
 117 #define FLASH_PG                (1 << 0)
 118 #define FLASH_SER               (1 << 1)
 119 #define FLASH_MER               (1 << 2)
 120 #define FLASH_STRT              (1 << 16)
 121 #define FLASH_PSIZE_8   (0 << 8)
 122 #define FLASH_PSIZE_16  (1 << 8)
 123 #define FLASH_PSIZE_32  (2 << 8)
 124 #define FLASH_PSIZE_64  (3 << 8)
 125 #define FLASH_SNB(a)    ((a) << 3)
 126 #define FLASH_LOCK              (1 << 31)
 127
 128 /* FLASH_SR register bits */
 129
 130 #define FLASH_BSY               (1 << 16)
 131 #define FLASH_PGSERR    (1 << 7) // Programming sequence error
 132 #define FLASH_PGPERR    (1 << 6) // Programming parallelism error
 133 #define FLASH_PGAERR    (1 << 5) // Programming alignment error
 134 #define FLASH_WRPERR    (1 << 4) // Write protection error
 135 #define FLASH_OPERR             (1 << 1) // Operation error
 136
 137 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR| FLASH_WRPERR| FLASH_OPERR)
 138
 139 /* STM32_FLASH_OBR bit definitions (reading) */
 140
 141 #define OPT_ERROR               0
 142 #define OPT_READOUT             1
 143 #define OPT_RDWDGSW             2
 144 #define OPT_RDRSTSTOP   3
 145 #define OPT_RDRSTSTDBY  4
 146 #define OPT_BFB2                5       /* dual flash bank only */
 147
 148 /* register unlock keys */
 149
 150 #define KEY1                    0x45670123
 151 #define KEY2                    0xCDEF89AB
 152
 153 struct stm32x_flash_bank
 154 {
 155         struct working_area *write_algorithm;
 156         int probed;
 157 };
 158
 159
 160 /* flash bank stm32x <base> <size> 0 0 <target#>
 161  */
 162 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 163 {
 164         struct stm32x_flash_bank *stm32x_info;
 165
 166         if (CMD_ARGC < 6)
 167         {
 168                 return ERROR_COMMAND_SYNTAX_ERROR;
 169         }
 170
 171         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 172         bank->driver_priv = stm32x_info;
 173
 174         stm32x_info->write_algorithm = NULL;
 175         stm32x_info->probed = 0;
 176
 177         return ERROR_OK;
 178 }
 179
 180 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 181 {
 182         return reg;
 183 }
 184
 185 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 186 {
 187         struct target *target = bank->target;
 188         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 189 }
 190
 191 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 192 {
 193         struct target *target = bank->target;
 194         uint32_t status;
 195         int retval = ERROR_OK;
 196
 197         /* wait for busy to clear */
 198         for (;;)
 199         {
 200                 retval = stm32x_get_flash_status(bank, &status);
 201                 if (retval != ERROR_OK)
 202                         return retval;
 203                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 204                 if ((status & FLASH_BSY) == 0)
 205                         break;
 206                 if (timeout-- <= 0)
 207                 {
 208                         LOG_ERROR("timed out waiting for flash");
 209                         return ERROR_FAIL;
 210                 }
 211                 alive_sleep(1);
 212         }
 213
 214
 215         if (status & FLASH_WRPERR)
 216         {
 217                 LOG_ERROR("stm32x device protected");
 218                 retval = ERROR_FAIL;
 219         }
 220
 221         /* Clear but report errors */
 222         if (status & FLASH_ERROR)
 223         {
 224                 /* If this operation fails, we ignore it and report the original
 225                  * retval
 226                  */
 227                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 228                                 status & FLASH_ERROR);
 229         }
 230         return retval;
 231 }
 232
 233 static int stm32x_unlock_reg(struct target *target)
 234 {
 235         uint32_t ctrl;
 236
 237         /* unlock flash registers */
 238         int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 239         if (retval != ERROR_OK)
 240                 return retval;
 241
 242         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 243         if (retval != ERROR_OK)
 244                 return retval;
 245
 246         retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 247         if (retval != ERROR_OK)
 248                 return retval;
 249
 250         if (ctrl & FLASH_LOCK) {
 251                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %x", ctrl);
 252                 return ERROR_TARGET_FAILURE;
 253         }
 254
 255         return ERROR_OK;
 256 }
 257
 258 static int stm32x_protect_check(struct flash_bank *bank)
 259 {
 260         return ERROR_OK;
 261 }
 262
 263 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 264 {
 265         struct target *target = bank->target;
 266         int i;
 267
 268         if (bank->target->state != TARGET_HALTED)
 269         {
 270                 LOG_ERROR("Target not halted");
 271                 return ERROR_TARGET_NOT_HALTED;
 272         }
 273
 274         int retval;
 275         retval = stm32x_unlock_reg(target);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278
 279         /*
 280         Sector Erase
 281         To erase a sector, follow the procedure below:
 282         1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
 283           FLASH_SR register
 284         2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block)
 285           you wish to erase (SNB) in the FLASH_CR register
 286         3. Set the STRT bit in the FLASH_CR register
 287         4. Wait for the BSY bit to be cleared
 288          */
 289
 290         for (i = first; i <= last; i++)
 291         {
 292                 retval = target_write_u32(target,
 293                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT);
 294                 if (retval != ERROR_OK)
 295                         return retval;
 296
 297                 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 298                 if (retval != ERROR_OK)
 299                         return retval;
 300
 301                 bank->sectors[i].is_erased = 1;
 302         }
 303
 304         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 305         if (retval != ERROR_OK)
 306                 return retval;
 307
 308         return ERROR_OK;
 309 }
 310
 311 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 312 {
 313         return ERROR_OK;
 314 }
 315
 316 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 317                 uint32_t offset, uint32_t count)
 318 {
 319         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 320         struct target *target = bank->target;
 321         uint32_t buffer_size = 16384;
 322         struct working_area *source;
 323         uint32_t address = bank->base + offset;
 324         struct reg_param reg_params[5];
 325         struct armv7m_algorithm armv7m_info;
 326         int retval = ERROR_OK;
 327
 328         /* see contrib/loaders/flash/stm32f2x.S for src */
 329
 330         static const uint16_t stm32x_flash_write_code_16[] = {
 331                 /* 00000000 <write>: */
 332                 0x4b07,                         /* ldr          r3, [pc, #28] (20 <STM32_PROG16>) */
 333                 0x6123,                         /* str          r3, [r4, #16] */
 334                 0xf830, 0x3b02,         /* ldrh.w       r3, [r0], #2 */
 335                 0xf821, 0x3b02,         /* strh.w       r3, [r1], #2 */
 336
 337                 /* 0000000c <busy>: */
 338                 0x68e3,                         /* ldr          r3, [r4, #12] */
 339                 0xf413, 0x3f80,         /* tst.w        r3, #65536      ; 0x10000 */
 340                 0xd0fb,                         /* beq.n        c <busy> */
 341                 0xf013, 0x0ff0,         /* tst.w        r3, #240        ; 0xf0 */
 342                 0xd101,                         /* bne.n        1e <exit> */
 343                 0x3a01,                         /* subs         r2, #1 */
 344                 0xd1f0,                         /* bne.n        0 <write> */
 345                                                         /* 0000001e <exit>: */
 346                 0xbe00,                         /* bkpt         0x0000 */
 347
 348                 /* 00000020 <STM32_PROG16>: */
 349                 0x0101, 0x0000,         /* .word        0x00000101 */
 350         };
 351
 352         /* Flip endian */
 353         uint8_t stm32x_flash_write_code[sizeof(stm32x_flash_write_code_16)*2];
 354         for (unsigned i = 0; i < sizeof(stm32x_flash_write_code_16) / 2; i++)
 355         {
 356                 stm32x_flash_write_code[i*2 + 0] = stm32x_flash_write_code_16[i] & 0xff;
 357                 stm32x_flash_write_code[i*2 + 1] = (stm32x_flash_write_code_16[i] >> 8) & 0xff;
 358         }
 359
 360         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 361                         &stm32x_info->write_algorithm) != ERROR_OK)
 362         {
 363                 LOG_WARNING("no working area available, can't do block memory writes");
 364                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 365         };
 366
 367         if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 368                         sizeof(stm32x_flash_write_code),
 369                         (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
 370                 return retval;
 371
 372         /* memory buffer */
 373         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
 374         {
 375                 buffer_size /= 2;
 376                 if (buffer_size <= 256)
 377                 {
 378                         /* if we already allocated the writing code, but failed to get a
 379                          * buffer, free the algorithm */
 380                         if (stm32x_info->write_algorithm)
 381                                 target_free_working_area(target, stm32x_info->write_algorithm);
 382
 383                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 384                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 385                 }
 386         };
 387
 388         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 389         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 390
 391         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 392         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 393         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 394         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
 395         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
 396
 397         while (count > 0)
 398         {
 399                 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
 400                                 (buffer_size / 2) : count;
 401
 402                 if ((retval = target_write_buffer(target, source->address,
 403                                 thisrun_count * 2, buffer)) != ERROR_OK)
 404                         break;
 405
 406                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 407                 buf_set_u32(reg_params[1].value, 0, 32, address);
 408                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 409                 // R3 is a return value only
 410                 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
 411
 412                 if ((retval = target_run_algorithm(target, 0, NULL,
 413                                 sizeof(reg_params) / sizeof(*reg_params),
 414                                 reg_params,
 415                                 stm32x_info->write_algorithm->address,
 416                                 0,
 417                                 10000, &armv7m_info)) != ERROR_OK)
 418                 {
 419                         LOG_ERROR("error executing stm32x flash write algorithm");
 420                         break;
 421                 }
 422
 423                 uint32_t error = buf_get_u32(reg_params[3].value, 0, 32) & FLASH_ERROR;
 424
 425                 if (error & FLASH_WRPERR)
 426                 {
 427                         LOG_ERROR("flash memory write protected");
 428                 }
 429
 430                 if (error != 0)
 431                 {
 432                         LOG_ERROR("flash write failed = %08x", error);
 433                         /* Clear but report errors */
 434                         target_write_u32(target, STM32_FLASH_SR, error);
 435                         retval = ERROR_FAIL;
 436                         break;
 437                 }
 438
 439                 buffer += thisrun_count * 2;
 440                 address += thisrun_count * 2;
 441                 count -= thisrun_count;
 442         }
 443
 444         target_free_working_area(target, source);
 445         target_free_working_area(target, stm32x_info->write_algorithm);
 446
 447         destroy_reg_param(&reg_params[0]);
 448         destroy_reg_param(&reg_params[1]);
 449         destroy_reg_param(&reg_params[2]);
 450         destroy_reg_param(&reg_params[3]);
 451         destroy_reg_param(&reg_params[4]);
 452
 453         return retval;
 454 }
 455
 456 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 457                 uint32_t offset, uint32_t count)
 458 {
 459         struct target *target = bank->target;
 460         uint32_t words_remaining = (count / 2);
 461         uint32_t bytes_remaining = (count & 0x00000001);
 462         uint32_t address = bank->base + offset;
 463         uint32_t bytes_written = 0;
 464         int retval;
 465
 466         if (bank->target->state != TARGET_HALTED)
 467         {
 468                 LOG_ERROR("Target not halted");
 469                 return ERROR_TARGET_NOT_HALTED;
 470         }
 471
 472         if (offset & 0x1)
 473         {
 474                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 475                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 476         }
 477
 478         retval = stm32x_unlock_reg(target);
 479         if (retval != ERROR_OK)
 480                 return retval;
 481
 482         /* multiple half words (2-byte) to be programmed? */
 483         if (words_remaining > 0)
 484         {
 485                 /* try using a block write */
 486                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 487                 {
 488                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 489                         {
 490                                 /* if block write failed (no sufficient working area),
 491                                  * we use normal (slow) single dword accesses */
 492                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 493                         }
 494                 }
 495                 else
 496                 {
 497                         buffer += words_remaining * 2;
 498                         address += words_remaining * 2;
 499                         words_remaining = 0;
 500                 }
 501         }
 502
 503         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 504                 return retval;
 505
 506         /*
 507         Standard programming
 508         The Flash memory programming sequence is as follows:
 509         1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
 510           FLASH_SR register.
 511         2. Set the PG bit in the FLASH_CR register
 512         3. Perform the data write operation(s) to the desired memory address (inside main
 513           memory block or OTP area):
 514         – – Half-word access in case of x16 parallelism
 515         – Word access in case of x32 parallelism
 516         –
 517         4.
 518         Byte access in case of x8 parallelism
 519         Double word access in case of x64 parallelism
 520         Wait for the BSY bit to be cleared
 521         */
 522         while (words_remaining > 0)
 523         {
 524                 uint16_t value;
 525                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 526
 527                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 528                                 FLASH_PG | FLASH_PSIZE_16);
 529                 if (retval != ERROR_OK)
 530                         return retval;
 531
 532                 retval = target_write_u16(target, address, value);
 533                 if (retval != ERROR_OK)
 534                         return retval;
 535
 536                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 537                 if (retval != ERROR_OK)
 538                         return retval;
 539
 540                 bytes_written += 2;
 541                 words_remaining--;
 542                 address += 2;
 543         }
 544
 545         if (bytes_remaining)
 546         {
 547                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 548                                 FLASH_PG | FLASH_PSIZE_8);
 549                 if (retval != ERROR_OK)
 550                         return retval;
 551                 retval = target_write_u8(target, address, buffer[bytes_written]);
 552                 if (retval != ERROR_OK)
 553                         return retval;
 554
 555                 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
 556                 if (retval != ERROR_OK)
 557                         return retval;
 558         }
 559
 560         return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 561 }
 562
 563 static void setup_sector(struct flash_bank *bank, int start, int num, int size)
 564 {
 565         for (int i = start; i < (start + num) ; i++)
 566         {
 567                 bank->sectors[i].offset = bank->size;
 568                 bank->sectors[i].size = size;
 569                 bank->size += bank->sectors[i].size;
 570         }
 571 }
 572
 573 static int stm32x_probe(struct flash_bank *bank)
 574 {
 575         struct target *target = bank->target;
 576         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 577         int i;
 578         uint16_t num_pages;
 579         uint32_t device_id;
 580         uint32_t base_address = 0x08000000;
 581
 582         stm32x_info->probed = 0;
 583
 584         /* read stm32 device id register */
 585         int retval = target_read_u32(target, 0xE0042000, &device_id);
 586         if (retval != ERROR_OK)
 587                 return retval;
 588         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 589
 590         if ((device_id & 0x7ff) != 0x411)
 591         {
 592                 LOG_WARNING("Cannot identify target as a STM32 family, try the other STM32 drivers.");
 593                 return ERROR_FAIL;
 594         }
 595
 596         /* sectors sizes vary, handle this in a different code path
 597          * than the rest.
 598          */
 599         // Uhhh.... what to use here?
 600
 601         /* calculate numbers of pages*/
 602         num_pages = 4 + 1 + 7;
 603
 604         if (bank->sectors)
 605         {
 606                 free(bank->sectors);
 607                 bank->sectors = NULL;
 608         }
 609
 610         bank->base = base_address;
 611         bank->num_sectors = num_pages;
 612         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 613
 614         bank->size = 0;
 615         setup_sector(bank, 0, 4, 16 * 1024);
 616         setup_sector(bank, 4, 1, 64 * 1024);
 617         setup_sector(bank, 4+1, 7, 128 * 1024);
 618
 619         for (i = 0; i < num_pages; i++)
 620         {
 621                 bank->sectors[i].is_erased = -1;
 622                 bank->sectors[i].is_protected = 0;
 623         }
 624
 625         LOG_INFO("flash size = %dkBytes", bank->size / 1024);
 626
 627         stm32x_info->probed = 1;
 628
 629         return ERROR_OK;
 630 }
 631
 632 static int stm32x_auto_probe(struct flash_bank *bank)
 633 {
 634         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 635         if (stm32x_info->probed)
 636                 return ERROR_OK;
 637         return stm32x_probe(bank);
 638 }
 639
 640 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 641 {
 642         struct target *target = bank->target;
 643         uint32_t device_id;
 644         int printed;
 645
 646         /* read stm32 device id register */
 647         int retval = target_read_u32(target, 0xE0042000, &device_id);
 648         if (retval != ERROR_OK)
 649                 return retval;
 650
 651         if ((device_id & 0x7ff) == 0x411)
 652         {
 653                 printed = snprintf(buf, buf_size, "stm32x (1mByte part) - Rev: ");
 654                 buf += printed;
 655                 buf_size -= printed;
 656
 657                 switch (device_id >> 16)
 658                 {
 659                         case 0x1000:
 660                                 snprintf(buf, buf_size, "A");
 661                                 break;
 662
 663                         case 0x2000:
 664                                 snprintf(buf, buf_size, "B");
 665                                 break;
 666
 667                         case 0x1001:
 668                                 snprintf(buf, buf_size, "Z");
 669                                 break;
 670
 671                         case 0x2001:
 672                                 snprintf(buf, buf_size, "Y");
 673                                 break;
 674
 675                         default:
 676                                 snprintf(buf, buf_size, "unknown");
 677                                 break;
 678                 }
 679         }
 680         else
 681         {
 682                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
 683                 return ERROR_FAIL;
 684         }
 685
 686         return ERROR_OK;
 687 }
 688
 689 static int stm32x_mass_erase(struct flash_bank *bank)
 690 {
 691         int retval;
 692         struct target *target = bank->target;
 693
 694         if (target->state != TARGET_HALTED) {
 695                 LOG_ERROR("Target not halted");
 696                 return ERROR_TARGET_NOT_HALTED;
 697         }
 698
 699         retval = stm32x_unlock_reg(target);
 700         if (retval != ERROR_OK)
 701                 return retval;
 702
 703         /* mass erase flash memory */
 704         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
 705         if (retval != ERROR_OK)
 706                 return retval;
 707         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
 708                 FLASH_MER | FLASH_STRT);
 709         if (retval != ERROR_OK)
 710                 return retval;
 711
 712         retval = stm32x_wait_status_busy(bank, 30000);
 713         if (retval != ERROR_OK)
 714                 return retval;
 715
 716         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 717         if (retval != ERROR_OK)
 718                 return retval;
 719
 720         return ERROR_OK;
 721 }
 722
 723 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
 724 {
 725         int i;
 726
 727         if (CMD_ARGC < 1) {
 728                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
 729                 return ERROR_COMMAND_SYNTAX_ERROR;
 730         }
 731
 732         struct flash_bank *bank;
 733         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 734         if (ERROR_OK != retval)
 735                 return retval;
 736
 737         retval = stm32x_mass_erase(bank);
 738         if (retval == ERROR_OK) {
 739                 /* set all sectors as erased */
 740                 for (i = 0; i < bank->num_sectors; i++)
 741                         bank->sectors[i].is_erased = 1;
 742
 743                 command_print(CMD_CTX, "stm32x mass erase complete");
 744         } else {
 745                 command_print(CMD_CTX, "stm32x mass erase failed");
 746         }
 747
 748         return retval;
 749 }
 750
 751 static const struct command_registration stm32x_exec_command_handlers[] = {
 752         {
 753                 .name = "mass_erase",
 754                 .handler = stm32x_handle_mass_erase_command,
 755                 .mode = COMMAND_EXEC,
 756                 .usage = "bank_id",
 757                 .help = "Erase entire flash device.",
 758         },
 759         COMMAND_REGISTRATION_DONE
 760 };
 761
 762 static const struct command_registration stm32x_command_handlers[] = {
 763         {
 764                 .name = "stm32f2x",
 765                 .mode = COMMAND_ANY,
 766                 .help = "stm32f2x flash command group",
 767                 .chain = stm32x_exec_command_handlers,
 768         },
 769         COMMAND_REGISTRATION_DONE
 770 };
 771
 772 struct flash_driver stm32f2x_flash = {
 773         .name = "stm32f2x",
 774         .commands = stm32x_command_handlers,
 775         .flash_bank_command = stm32x_flash_bank_command,
 776         .erase = stm32x_erase,
 777         .protect = stm32x_protect,
 778         .write = stm32x_write,
 779         .read = default_flash_read,
 780         .probe = stm32x_probe,
 781         .auto_probe = stm32x_auto_probe,
 782         .erase_check = default_flash_mem_blank_check,
 783         .protect_check = stm32x_protect_check,
 784         .info = get_stm32x_info,
 785 };