git.sur5r.net Git - openocd/blob - src/flash/nor/stm32l4x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Uwe Bonnes                                      *
   3  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
   4  *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.                                        *
  18  ***************************************************************************/
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "imp.h"
  25 #include <helper/binarybuffer.h>
  26 #include <target/algorithm.h>
  27 #include <target/armv7m.h>
  28
  29 /* STM32L4xxx series for reference.
  30  *
  31  * RM0351
  32  * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00083560.pdf
  33  *
  34  * STM32L476RG Datasheet (for erase timing)
  35  * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00108832.pdf
  36  *
  37  *
  38  * The device has normally two banks, but on 512 and 256 kiB devices an
  39  * option byte is available to map all sectors to the first bank.
  40  * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
  41  * handlers do!
  42  *
  43  */
  44
  45 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
  46
  47 #define FLASH_ERASE_TIMEOUT 250
  48
  49 #define STM32_FLASH_BASE    0x40022000
  50 #define STM32_FLASH_ACR     0x40022000
  51 #define STM32_FLASH_KEYR    0x40022008
  52 #define STM32_FLASH_OPTKEYR 0x4002200c
  53 #define STM32_FLASH_SR      0x40022010
  54 #define STM32_FLASH_CR      0x40022014
  55 #define STM32_FLASH_OPTR    0x40022020
  56 #define STM32_FLASH_WRP1AR  0x4002202c
  57 #define STM32_FLASH_WRP2AR  0x40022030
  58 #define STM32_FLASH_WRP1BR  0x4002204c
  59 #define STM32_FLASH_WRP2BR  0x40022050
  60
  61 /* FLASH_CR register bits */
  62
  63 #define FLASH_PG       (1 << 0)
  64 #define FLASH_PER      (1 << 1)
  65 #define FLASH_MER1     (1 << 2)
  66 #define FLASH_PAGE_SHIFT     3
  67 #define FLASH_CR_BKER  (1 << 11)
  68 #define FLASH_MER2     (1 << 15)
  69 #define FLASH_STRT     (1 << 16)
  70 #define FLASH_EOPIE    (1 << 24)
  71 #define FLASH_ERRIE    (1 << 25)
  72 #define FLASH_OPTLOCK  (1 << 30)
  73 #define FLASH_LOCK     (1 << 31)
  74
  75 /* FLASH_SR register bits */
  76
  77 #define FLASH_BSY      (1 << 16)
  78 /* Fast programming not used => related errors not used*/
  79 #define FLASH_PGSERR   (1 << 7) /* Programming sequence error */
  80 #define FLASH_SIZERR   (1 << 6) /* Size  error */
  81 #define FLASH_PGAERR   (1 << 5) /* Programming alignment error */
  82 #define FLASH_WRPERR   (1 << 4) /* Write protection error */
  83 #define FLASH_PROGERR  (1 << 3) /* Programming error */
  84 #define FLASH_OPERR    (1 << 1) /* Operation error */
  85 #define FLASH_EOP      (1 << 0) /* End of operation */
  86
  87 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
  88
  89 /* STM32_FLASH_OBR bit definitions (reading) */
  90
  91 #define OPT_DUALBANK   21       /* dual flash bank only */
  92
  93 /* register unlock keys */
  94
  95 #define KEY1           0x45670123
  96 #define KEY2           0xCDEF89AB
  97
  98 /* option register unlock key */
  99 #define OPTKEY1        0x08192A3B
 100 #define OPTKEY2        0x4C5D6E7F
 101
 102
 103 /* other registers */
 104 #define DBGMCU_IDCODE   0xE0042000
 105 #define FLASH_SIZE_REG  0x1FFF75E0
 106
 107 struct stm32l4_options {
 108         uint8_t RDP;
 109         uint16_t bank_b_start;
 110         uint8_t user_options;
 111         uint8_t wpr1a_start;
 112         uint8_t wpr1a_end;
 113         uint8_t wpr1b_start;
 114         uint8_t wpr1b_end;
 115         uint8_t wpr2a_start;
 116         uint8_t wpr2a_end;
 117         uint8_t wpr2b_start;
 118         uint8_t wpr2b_end;
 119     /* Fixme: Handle PCROP */
 120 };
 121
 122 struct stm32l4_flash_bank {
 123         struct stm32l4_options option_bytes;
 124         int probed;
 125 };
 126
 127 /* flash bank stm32l4x <base> <size> 0 0 <target#>
 128  */
 129 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
 130 {
 131         struct stm32l4_flash_bank *stm32l4_info;
 132
 133         if (CMD_ARGC < 6)
 134                 return ERROR_COMMAND_SYNTAX_ERROR;
 135
 136         stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
 137         if (!stm32l4_info)
 138                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 139         bank->driver_priv = stm32l4_info;
 140
 141         stm32l4_info->probed = 0;
 142
 143         return ERROR_OK;
 144 }
 145
 146 static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 147 {
 148         return reg;
 149 }
 150
 151 static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
 152 {
 153         struct target *target = bank->target;
 154         return target_read_u32(
 155                 target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
 156 }
 157
 158 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 159 {
 160         struct target *target = bank->target;
 161         uint32_t status;
 162         int retval = ERROR_OK;
 163
 164         /* wait for busy to clear */
 165         for (;;) {
 166                 retval = stm32l4_get_flash_status(bank, &status);
 167                 if (retval != ERROR_OK)
 168                         return retval;
 169                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 170                 if ((status & FLASH_BSY) == 0)
 171                         break;
 172                 if (timeout-- <= 0) {
 173                         LOG_ERROR("timed out waiting for flash");
 174                         return ERROR_FAIL;
 175                 }
 176                 alive_sleep(1);
 177         }
 178
 179
 180         if (status & FLASH_WRPERR) {
 181                 LOG_ERROR("stm32x device protected");
 182                 retval = ERROR_FAIL;
 183         }
 184
 185         /* Clear but report errors */
 186         if (status & FLASH_ERROR) {
 187                 /* If this operation fails, we ignore it and report the original
 188                  * retval
 189                  */
 190                 target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
 191                                 status & FLASH_ERROR);
 192         }
 193         return retval;
 194 }
 195
 196 static int stm32l4_unlock_reg(struct target *target)
 197 {
 198         uint32_t ctrl;
 199
 200         /* first check if not already unlocked
 201          * otherwise writing on STM32_FLASH_KEYR will fail
 202          */
 203         int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 204         if (retval != ERROR_OK)
 205                 return retval;
 206
 207         if ((ctrl & FLASH_LOCK) == 0)
 208                 return ERROR_OK;
 209
 210         /* unlock flash registers */
 211         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 212         if (retval != ERROR_OK)
 213                 return retval;
 214
 215         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 216         if (retval != ERROR_OK)
 217                 return retval;
 218
 219         retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 220         if (retval != ERROR_OK)
 221                 return retval;
 222
 223         if (ctrl & FLASH_LOCK) {
 224                 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 225                 return ERROR_TARGET_FAILURE;
 226         }
 227
 228         return ERROR_OK;
 229 }
 230
 231 static int stm32l4_unlock_option_reg(struct target *target)
 232 {
 233         uint32_t ctrl;
 234
 235         int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 236         if (retval != ERROR_OK)
 237                 return retval;
 238
 239         if ((ctrl & FLASH_OPTLOCK) == 0)
 240                 return ERROR_OK;
 241
 242         /* unlock option registers */
 243         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
 244         if (retval != ERROR_OK)
 245                 return retval;
 246
 247         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
 248         if (retval != ERROR_OK)
 249                 return retval;
 250
 251         retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
 252         if (retval != ERROR_OK)
 253                 return retval;
 254
 255         if (ctrl & FLASH_OPTLOCK) {
 256                 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
 257                 return ERROR_TARGET_FAILURE;
 258         }
 259
 260         return ERROR_OK;
 261 }
 262
 263 static int stm32l4_read_options(struct flash_bank *bank)
 264 {
 265         uint32_t optiondata;
 266         struct stm32l4_flash_bank *stm32l4_info = NULL;
 267         struct target *target = bank->target;
 268
 269         stm32l4_info = bank->driver_priv;
 270
 271         /* read current option bytes */
 272         int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
 273         if (retval != ERROR_OK)
 274                 return retval;
 275
 276         stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
 277         stm32l4_info->option_bytes.RDP = optiondata & 0xff;
 278
 279         retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
 280         if (retval != ERROR_OK)
 281                 return retval;
 282         stm32l4_info->option_bytes.wpr1a_start =  optiondata         & 0xff;
 283         stm32l4_info->option_bytes.wpr1a_end   = (optiondata >> 16)  & 0xff;
 284
 285         retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
 286         if (retval != ERROR_OK)
 287                 return retval;
 288         stm32l4_info->option_bytes.wpr2a_start =  optiondata         & 0xff;
 289         stm32l4_info->option_bytes.wpr2a_end   = (optiondata >> 16)  & 0xff;
 290
 291         retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
 292         if (retval != ERROR_OK)
 293                 return retval;
 294         stm32l4_info->option_bytes.wpr1b_start =  optiondata         & 0xff;
 295         stm32l4_info->option_bytes.wpr1b_end   = (optiondata >> 16)  & 0xff;
 296
 297         retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
 298         if (retval != ERROR_OK)
 299                 return retval;
 300         stm32l4_info->option_bytes.wpr2b_start =  optiondata         & 0xff;
 301         stm32l4_info->option_bytes.wpr2b_end   = (optiondata >> 16)  & 0xff;
 302
 303         if (stm32l4_info->option_bytes.RDP != 0xAA)
 304                 LOG_INFO("Device Security Bit Set");
 305
 306         return ERROR_OK;
 307 }
 308
 309 static int stm32l4_write_options(struct flash_bank *bank)
 310 {
 311         struct stm32l4_flash_bank *stm32l4_info = NULL;
 312         struct target *target = bank->target;
 313         uint32_t optiondata;
 314
 315         stm32l4_info = bank->driver_priv;
 316
 317         (void) optiondata;
 318         (void) stm32l4_info;
 319
 320         int retval = stm32l4_unlock_option_reg(target);
 321         if (retval != ERROR_OK)
 322                 return retval;
 323         /* FIXME: Implement Option writing!*/
 324         return ERROR_OK;
 325 }
 326
 327 static int stm32l4_protect_check(struct flash_bank *bank)
 328 {
 329         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 330
 331         /* read write protection settings */
 332         int retval = stm32l4_read_options(bank);
 333         if (retval != ERROR_OK) {
 334                 LOG_DEBUG("unable to read option bytes");
 335                 return retval;
 336         }
 337
 338         for (int i = 0; i < bank->num_sectors; i++) {
 339                 if (i < stm32l4_info->option_bytes.bank_b_start) {
 340                         if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
 341                                  (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
 342                                 ((i >= stm32l4_info->option_bytes.wpr2a_start) &&
 343                                  (i <= stm32l4_info->option_bytes.wpr2a_end)))
 344                                 bank->sectors[i].is_protected = 1;
 345                         else
 346                                 bank->sectors[i].is_protected = 0;
 347                 } else {
 348                         uint8_t snb;
 349                         snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
 350                         if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
 351                                  (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
 352                                 ((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
 353                                  (snb <= stm32l4_info->option_bytes.wpr2b_end)))
 354                                 bank->sectors[i].is_protected = 1;
 355                         else
 356                                 bank->sectors[i].is_protected = 0;
 357                 }
 358         }
 359         return ERROR_OK;
 360 }
 361
 362 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 363 {
 364         struct target *target = bank->target;
 365         int i;
 366
 367         assert(first < bank->num_sectors);
 368         assert(last < bank->num_sectors);
 369
 370         if (bank->target->state != TARGET_HALTED) {
 371                 LOG_ERROR("Target not halted");
 372                 return ERROR_TARGET_NOT_HALTED;
 373         }
 374
 375         int retval;
 376         retval = stm32l4_unlock_reg(target);
 377         if (retval != ERROR_OK)
 378                 return retval;
 379
 380         /*
 381         Sector Erase
 382         To erase a sector, follow the procedure below:
 383         1. Check that no Flash memory operation is ongoing by
 384        checking the BSY bit in the FLASH_SR register
 385         2. Set the PER bit and select the page and bank
 386            you wish to erase  in the FLASH_CR register
 387         3. Set the STRT bit in the FLASH_CR register
 388         4. Wait for the BSY bit to be cleared
 389          */
 390         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 391
 392         for (i = first; i <= last; i++) {
 393                 uint32_t erase_flags;
 394                 erase_flags = FLASH_PER | FLASH_STRT;
 395
 396                 if  (i >= stm32l4_info->option_bytes.bank_b_start) {
 397                         uint8_t snb;
 398                         snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
 399                         erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 400                 } else
 401                         erase_flags |= i << FLASH_PAGE_SHIFT;
 402                 retval = target_write_u32(target,
 403                                 stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
 404                 if (retval != ERROR_OK)
 405                         return retval;
 406
 407                 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 408                 if (retval != ERROR_OK)
 409                         return retval;
 410
 411                 bank->sectors[i].is_erased = 1;
 412         }
 413
 414         retval = target_write_u32(
 415                 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 416         if (retval != ERROR_OK)
 417                 return retval;
 418
 419         return ERROR_OK;
 420 }
 421
 422 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
 423 {
 424         struct target *target = bank->target;
 425         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 426
 427         if (target->state != TARGET_HALTED) {
 428                 LOG_ERROR("Target not halted");
 429                 return ERROR_TARGET_NOT_HALTED;
 430         }
 431
 432         /* read protection settings */
 433         int retval = stm32l4_read_options(bank);
 434         if (retval != ERROR_OK) {
 435                 LOG_DEBUG("unable to read option bytes");
 436                 return retval;
 437         }
 438
 439         (void)stm32l4_info;
 440         /* FIXME: Write First and last in a valid WRPxx_start/end combo*/
 441         retval = stm32l4_write_options(bank);
 442         if (retval != ERROR_OK)
 443                 return retval;
 444
 445         return ERROR_OK;
 446 }
 447
 448 /* Count is in halfwords */
 449 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 450                 uint32_t offset, uint32_t count)
 451 {
 452         struct target *target = bank->target;
 453         uint32_t buffer_size = 16384;
 454         struct working_area *write_algorithm;
 455         struct working_area *source;
 456         uint32_t address = bank->base + offset;
 457         struct reg_param reg_params[5];
 458         struct armv7m_algorithm armv7m_info;
 459         int retval = ERROR_OK;
 460
 461         /* See contrib/loaders/flash/stm32l4x.S for source and
 462          * hints how to generate the data!
 463          */
 464
 465         static const uint8_t stm32l4_flash_write_code[] = {
 466                 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f, 0x1e, 0xd0, 0x45, 0x68,
 467                 0xb8, 0xeb, 0x05, 0x06, 0x07, 0x2e, 0xf5, 0xd3, 0xdf, 0xf8, 0x34, 0x60,
 468                 0x66, 0x61, 0xf5, 0xe8, 0x02, 0x67, 0xe2, 0xe8, 0x02, 0x67, 0xbf, 0xf3,
 469                 0x4f, 0x8f, 0x26, 0x69, 0x16, 0xf4, 0x80, 0x3f, 0xfb, 0xd1, 0x16, 0xf0,
 470                 0xfa, 0x0f, 0x07, 0xd1, 0x8d, 0x42, 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x05,
 471                 0x45, 0x60, 0x01, 0x3b, 0x13, 0xb1, 0xdd, 0xe7, 0x00, 0x21, 0x41, 0x60,
 472                 0x30, 0x46, 0x00, 0xbe, 0x01, 0x00, 0x00, 0x00
 473         };
 474
 475         if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
 476                         &write_algorithm) != ERROR_OK) {
 477                 LOG_WARNING("no working area available, can't do block memory writes");
 478                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 479         }
 480
 481         retval = target_write_buffer(target, write_algorithm->address,
 482                         sizeof(stm32l4_flash_write_code),
 483                         stm32l4_flash_write_code);
 484         if (retval != ERROR_OK)
 485                 return retval;
 486
 487         /* memory buffer */
 488         while (target_alloc_working_area_try(target, buffer_size, &source) !=
 489                    ERROR_OK) {
 490                 buffer_size /= 2;
 491                 if (buffer_size <= 256) {
 492                         /* we already allocated the writing code, but failed to get a
 493                          * buffer, free the algorithm */
 494                         target_free_working_area(target, write_algorithm);
 495
 496                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 497                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 498                 }
 499         }
 500
 501         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 502         armv7m_info.core_mode = ARM_MODE_THREAD;
 503
 504         init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
 505         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);    /* buffer end */
 506         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);    /* target address */
 507         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);    /* count (double word-64bit) */
 508         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);    /* flash base */
 509
 510         buf_set_u32(reg_params[0].value, 0, 32, source->address);
 511         buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
 512         buf_set_u32(reg_params[2].value, 0, 32, address);
 513         buf_set_u32(reg_params[3].value, 0, 32, count / 4);
 514         buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
 515
 516         retval = target_run_flash_async_algorithm(target, buffer, count, 2,
 517                         0, NULL,
 518                         5, reg_params,
 519                         source->address, source->size,
 520                         write_algorithm->address, 0,
 521                         &armv7m_info);
 522
 523         if (retval == ERROR_FLASH_OPERATION_FAILED) {
 524                 LOG_ERROR("error executing stm32l4 flash write algorithm");
 525
 526                 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
 527
 528                 if (error & FLASH_WRPERR)
 529                         LOG_ERROR("flash memory write protected");
 530
 531                 if (error != 0) {
 532                         LOG_ERROR("flash write failed = %08" PRIx32, error);
 533                         /* Clear but report errors */
 534                         target_write_u32(target, STM32_FLASH_SR, error);
 535                         retval = ERROR_FAIL;
 536                 }
 537         }
 538
 539         target_free_working_area(target, source);
 540         target_free_working_area(target, write_algorithm);
 541
 542         destroy_reg_param(&reg_params[0]);
 543         destroy_reg_param(&reg_params[1]);
 544         destroy_reg_param(&reg_params[2]);
 545         destroy_reg_param(&reg_params[3]);
 546         destroy_reg_param(&reg_params[4]);
 547
 548         return retval;
 549 }
 550
 551 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
 552                 uint32_t offset, uint32_t count)
 553 {
 554         struct target *target = bank->target;
 555         int retval;
 556
 557         if (bank->target->state != TARGET_HALTED) {
 558                 LOG_ERROR("Target not halted");
 559                 return ERROR_TARGET_NOT_HALTED;
 560         }
 561
 562         if (offset & 0x7) {
 563                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
 564                                         offset);
 565                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 566         }
 567
 568         if (count & 0x7) {
 569                 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
 570                                         count & 7);
 571                 count = (count + 7) & ~7;
 572                 /* This pads the write chunk with random bytes by overrunning the
 573                  * write buffer. Padding with the erased pattern 0xff is purely
 574                  * cosmetical, as 8-byte flash words are ECC secured and the first
 575                  * write will program the ECC bits. A second write would need
 576                  * to reprogramm these ECC bits.
 577                  * But this can only be done after erase!
 578                  */
 579         }
 580
 581         retval = stm32l4_unlock_reg(target);
 582         if (retval != ERROR_OK)
 583                 return retval;
 584
 585         /* Only full double words (8-byte) can be programmed*/
 586         retval = stm32l4_write_block(bank, buffer, offset, count / 2);
 587         if (retval != ERROR_OK) {
 588                 LOG_WARNING("block write failed");
 589                 return retval;
 590                 }
 591
 592         LOG_WARNING("block write succeeded");
 593         return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 594 }
 595
 596 static int stm32l4_probe(struct flash_bank *bank)
 597 {
 598         struct target *target = bank->target;
 599         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 600         int i;
 601         uint16_t flash_size_in_kb = 0xffff;
 602         uint32_t device_id;
 603         uint32_t options;
 604         uint32_t base_address = 0x08000000;
 605
 606         stm32l4_info->probed = 0;
 607
 608         /* read stm32 device id register */
 609         int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
 610         if (retval != ERROR_OK)
 611                 return retval;
 612         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 613
 614         /* set max flash size depending on family */
 615         switch (device_id & 0xfff) {
 616         case 0x415:
 617                 break;
 618         default:
 619                 LOG_WARNING("Cannot identify target as a STM32L4 family.");
 620                 return ERROR_FAIL;
 621         }
 622
 623         /* get flash size from target. */
 624         retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
 625
 626         /* get options to for DUAL BANK. */
 627         retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
 628
 629         /* only devices with < 1024 kiB may be set to single bank dual banks */
 630         if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
 631                 stm32l4_info->option_bytes.bank_b_start = 256;
 632         else
 633                 stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
 634
 635         LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 636
 637         /* did we assign flash size? */
 638         assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
 639
 640         /* calculate numbers of pages */
 641         int num_pages = flash_size_in_kb / 2;
 642
 643         /* check that calculation result makes sense */
 644         assert(num_pages > 0);
 645
 646         if (bank->sectors) {
 647                 free(bank->sectors);
 648                 bank->sectors = NULL;
 649         }
 650
 651         bank->base = base_address;
 652         bank->size = num_pages * (1 << 11);
 653         bank->num_sectors = num_pages;
 654         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 655         if (!bank->sectors)
 656                 return ERROR_FAIL; /* Checkme: What better error to use?*/
 657
 658         for (i = 0; i < num_pages; i++) {
 659                 bank->sectors[i].offset = i << 11;
 660                 bank->sectors[i].size = 1 << 11;
 661                 bank->sectors[i].is_erased = -1;
 662                 bank->sectors[i].is_protected = 1;
 663         }
 664
 665         stm32l4_info->probed = 1;
 666
 667         return ERROR_OK;
 668 }
 669
 670 static int stm32l4_auto_probe(struct flash_bank *bank)
 671 {
 672         struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 673         if (stm32l4_info->probed)
 674                 return ERROR_OK;
 675         return stm32l4_probe(bank);
 676 }
 677
 678 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
 679 {
 680         struct target *target = bank->target;
 681         uint32_t dbgmcu_idcode;
 682
 683         /* read stm32 device id register */
 684         int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
 685         if (retval != ERROR_OK)
 686                 return retval;
 687
 688         uint16_t device_id = dbgmcu_idcode & 0xffff;
 689         uint8_t rev_id = dbgmcu_idcode >> 28;
 690         uint8_t rev_minor = 0;
 691         int i;
 692
 693         for (i = 16; i < 28; i++) {
 694                 if (dbgmcu_idcode & (1 << i))
 695                         rev_minor++;
 696                 else
 697                         break;
 698         }
 699
 700         const char *device_str;
 701
 702         switch (device_id) {
 703         case 0x6415:
 704                 device_str = "STM32L4xx";
 705                 break;
 706
 707         default:
 708                 snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
 709                 return ERROR_FAIL;
 710         }
 711
 712         snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
 713                          device_str, rev_id, rev_minor);
 714
 715         return ERROR_OK;
 716 }
 717
 718 COMMAND_HANDLER(stm32l4_handle_lock_command)
 719 {
 720         struct target *target = NULL;
 721         struct stm32l4_flash_bank *stm32l4_info = NULL;
 722
 723         if (CMD_ARGC < 1)
 724                 return ERROR_COMMAND_SYNTAX_ERROR;
 725
 726         struct flash_bank *bank;
 727         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 728         if (ERROR_OK != retval)
 729                 return retval;
 730
 731         stm32l4_info = bank->driver_priv;
 732         target = bank->target;
 733
 734         if (target->state != TARGET_HALTED) {
 735                 LOG_ERROR("Target not halted");
 736                 return ERROR_TARGET_NOT_HALTED;
 737         }
 738
 739         if (stm32l4_read_options(bank) != ERROR_OK) {
 740                 command_print(CMD_CTX, "%s failed to read options",
 741                                           bank->driver->name);
 742                 return ERROR_OK;
 743         }
 744
 745         /* set readout protection */
 746         stm32l4_info->option_bytes.RDP = 0;
 747
 748         if (stm32l4_write_options(bank) != ERROR_OK) {
 749                 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
 750                 return ERROR_OK;
 751         }
 752
 753         command_print(CMD_CTX, "%s locked", bank->driver->name);
 754
 755         return ERROR_OK;
 756 }
 757
 758 COMMAND_HANDLER(stm32l4_handle_unlock_command)
 759 {
 760         struct target *target = NULL;
 761         struct stm32l4_flash_bank *stm32l4_info = NULL;
 762
 763         if (CMD_ARGC < 1)
 764                 return ERROR_COMMAND_SYNTAX_ERROR;
 765
 766         struct flash_bank *bank;
 767         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 768         if (ERROR_OK != retval)
 769                 return retval;
 770
 771         stm32l4_info = bank->driver_priv;
 772         target = bank->target;
 773
 774         if (target->state != TARGET_HALTED) {
 775                 LOG_ERROR("Target not halted");
 776                 return ERROR_TARGET_NOT_HALTED;
 777         }
 778
 779         if (stm32l4_read_options(bank) != ERROR_OK) {
 780                 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
 781                 return ERROR_OK;
 782         }
 783
 784         /* clear readout protection and complementary option bytes
 785          * this will also force a device unlock if set */
 786         stm32l4_info->option_bytes.RDP = 0xAA;
 787
 788         if (stm32l4_write_options(bank) != ERROR_OK) {
 789                 command_print(CMD_CTX, "%s failed to unlock device",
 790                                           bank->driver->name);
 791                 return ERROR_OK;
 792         }
 793
 794         command_print(CMD_CTX, "%s unlocked.\n"
 795                         "INFO: a reset or power cycle is required "
 796                         "for the new settings to take effect.", bank->driver->name);
 797
 798         return ERROR_OK;
 799 }
 800
 801 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
 802 {
 803         int retval;
 804         struct target *target = bank->target;
 805
 806         if (target->state != TARGET_HALTED) {
 807                 LOG_ERROR("Target not halted");
 808                 return ERROR_TARGET_NOT_HALTED;
 809         }
 810
 811         retval = stm32l4_unlock_reg(target);
 812         if (retval != ERROR_OK)
 813                 return retval;
 814
 815         /* mass erase flash memory */
 816         retval = target_write_u32(
 817                 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
 818         if (retval != ERROR_OK)
 819                 return retval;
 820         retval = target_write_u32(
 821                 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
 822                 action | FLASH_STRT);
 823         if (retval != ERROR_OK)
 824                 return retval;
 825
 826         retval = stm32l4_wait_status_busy(bank,  FLASH_ERASE_TIMEOUT);
 827         if (retval != ERROR_OK)
 828                 return retval;
 829
 830         retval = target_write_u32(
 831                 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 832         if (retval != ERROR_OK)
 833                 return retval;
 834
 835         return ERROR_OK;
 836 }
 837
 838 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
 839 {
 840         int i;
 841         uint32_t action;
 842
 843         if (CMD_ARGC < 1) {
 844                 command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
 845                 return ERROR_COMMAND_SYNTAX_ERROR;
 846         }
 847
 848         struct flash_bank *bank;
 849         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 850         if (ERROR_OK != retval)
 851                 return retval;
 852
 853         action =  FLASH_MER1 |  FLASH_MER2;
 854         retval = stm32l4_mass_erase(bank, action);
 855         if (retval == ERROR_OK) {
 856                 /* set all sectors as erased */
 857                 for (i = 0; i < bank->num_sectors; i++)
 858                         bank->sectors[i].is_erased = 1;
 859
 860                 command_print(CMD_CTX, "stm32x mass erase complete");
 861         } else {
 862                 command_print(CMD_CTX, "stm32x mass erase failed");
 863         }
 864
 865         return retval;
 866 }
 867
 868 static const struct command_registration stm32l4_exec_command_handlers[] = {
 869         {
 870                 .name = "lock",
 871                 .handler = stm32l4_handle_lock_command,
 872                 .mode = COMMAND_EXEC,
 873                 .usage = "bank_id",
 874                 .help = "Lock entire flash device.",
 875         },
 876         {
 877                 .name = "unlock",
 878                 .handler = stm32l4_handle_unlock_command,
 879                 .mode = COMMAND_EXEC,
 880                 .usage = "bank_id",
 881                 .help = "Unlock entire protected flash device.",
 882         },
 883         {
 884                 .name = "mass_erase",
 885                 .handler = stm32l4_handle_mass_erase_command,
 886                 .mode = COMMAND_EXEC,
 887                 .usage = "bank_id",
 888                 .help = "Erase entire flash device.",
 889         },
 890         COMMAND_REGISTRATION_DONE
 891 };
 892
 893 static const struct command_registration stm32l4_command_handlers[] = {
 894         {
 895                 .name = "stm32l4x",
 896                 .mode = COMMAND_ANY,
 897                 .help = "stm32l4x flash command group",
 898                 .usage = "",
 899                 .chain = stm32l4_exec_command_handlers,
 900         },
 901         COMMAND_REGISTRATION_DONE
 902 };
 903
 904 struct flash_driver stm32l4x_flash = {
 905         .name = "stm32l4x",
 906         .commands = stm32l4_command_handlers,
 907         .flash_bank_command = stm32l4_flash_bank_command,
 908         .erase = stm32l4_erase,
 909         .protect = stm32l4_protect,
 910         .write = stm32l4_write,
 911         .read = default_flash_read,
 912         .probe = stm32l4_probe,
 913         .auto_probe = stm32l4_auto_probe,
 914         .erase_check = default_flash_blank_check,
 915         .protect_check = stm32l4_protect_check,
 916         .info = get_stm32l4_info,
 917 };