git.sur5r.net Git - openocd/blob - src/flash/nor/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "imp.h"
  28 #include <helper/binarybuffer.h>
  29 #include <target/algorithm.h>
  30 #include <target/armv7m.h>
  31
  32 /* stm32x register locations */
  33
  34 #define STM32_FLASH_ACR         0x40022000
  35 #define STM32_FLASH_KEYR        0x40022004
  36 #define STM32_FLASH_OPTKEYR     0x40022008
  37 #define STM32_FLASH_SR          0x4002200C
  38 #define STM32_FLASH_CR          0x40022010
  39 #define STM32_FLASH_AR          0x40022014
  40 #define STM32_FLASH_OBR         0x4002201C
  41 #define STM32_FLASH_WRPR        0x40022020
  42
  43 /* option byte location */
  44
  45 #define STM32_OB_RDP            0x1FFFF800
  46 #define STM32_OB_USER           0x1FFFF802
  47 #define STM32_OB_DATA0          0x1FFFF804
  48 #define STM32_OB_DATA1          0x1FFFF806
  49 #define STM32_OB_WRP0           0x1FFFF808
  50 #define STM32_OB_WRP1           0x1FFFF80A
  51 #define STM32_OB_WRP2           0x1FFFF80C
  52 #define STM32_OB_WRP3           0x1FFFF80E
  53
  54 /* FLASH_CR register bits */
  55
  56 #define FLASH_PG                (1 << 0)
  57 #define FLASH_PER               (1 << 1)
  58 #define FLASH_MER               (1 << 2)
  59 #define FLASH_OPTPG             (1 << 4)
  60 #define FLASH_OPTER             (1 << 5)
  61 #define FLASH_STRT              (1 << 6)
  62 #define FLASH_LOCK              (1 << 7)
  63 #define FLASH_OPTWRE    (1 << 9)
  64
  65 /* FLASH_SR register bits */
  66
  67 #define FLASH_BSY               (1 << 0)
  68 #define FLASH_PGERR             (1 << 2)
  69 #define FLASH_WRPRTERR  (1 << 4)
  70 #define FLASH_EOP               (1 << 5)
  71
  72 /* STM32_FLASH_OBR bit definitions (reading) */
  73
  74 #define OPT_ERROR               0
  75 #define OPT_READOUT             1
  76 #define OPT_RDWDGSW             2
  77 #define OPT_RDRSTSTOP   3
  78 #define OPT_RDRSTSTDBY  4
  79 #define OPT_BFB2                5       /* dual flash bank only */
  80
  81 /* register unlock keys */
  82
  83 #define KEY1                    0x45670123
  84 #define KEY2                    0xCDEF89AB
  85
  86 /* we use an offset to access the second bank on dual flash devices
  87  * strangely the protection of the second bank is done on the bank0 reg's */
  88
  89 #define FLASH_OFFSET_B0 0x00
  90 #define FLASH_OFFSET_B1 0x40
  91
  92 struct stm32x_options
  93 {
  94         uint16_t RDP;
  95         uint16_t user_options;
  96         uint16_t protection[4];
  97 };
  98
  99 struct stm32x_flash_bank
 100 {
 101         struct stm32x_options option_bytes;
 102         struct working_area *write_algorithm;
 103         int ppage_size;
 104         int probed;
 105
 106         bool has_dual_banks;
 107         /* used to access dual flash bank stm32xl
 108          * 0x00 will address bank 0 flash
 109          * 0x40 will address bank 1 flash */
 110         int register_offset;
 111 };
 112
 113 static int stm32x_mass_erase(struct flash_bank *bank);
 114
 115 /* flash bank stm32x <base> <size> 0 0 <target#>
 116  */
 117 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
 118 {
 119         struct stm32x_flash_bank *stm32x_info;
 120
 121         if (CMD_ARGC < 6)
 122         {
 123                 LOG_WARNING("incomplete flash_bank stm32x configuration");
 124                 return ERROR_FLASH_BANK_INVALID;
 125         }
 126
 127         stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
 128         bank->driver_priv = stm32x_info;
 129
 130         stm32x_info->write_algorithm = NULL;
 131         stm32x_info->probed = 0;
 132         stm32x_info->has_dual_banks = false;
 133         stm32x_info->register_offset = FLASH_OFFSET_B0;
 134
 135         return ERROR_OK;
 136 }
 137
 138 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
 139 {
 140         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 141         return reg + stm32x_info->register_offset;
 142 }
 143
 144 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
 145 {
 146         struct target *target = bank->target;
 147         return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
 148 }
 149
 150 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 151 {
 152         struct target *target = bank->target;
 153         uint32_t status;
 154         int retval = ERROR_OK;
 155
 156         /* wait for busy to clear */
 157         for (;;)
 158         {
 159                 retval = stm32x_get_flash_status(bank, &status);
 160                 if (retval != ERROR_OK)
 161                         return retval;
 162                 LOG_DEBUG("status: 0x%" PRIx32 "", status);
 163                 if ((status & FLASH_BSY) == 0)
 164                         break;
 165                 if (timeout-- <= 0)
 166                 {
 167                         LOG_ERROR("timed out waiting for flash");
 168                         return ERROR_FAIL;
 169                 }
 170                 alive_sleep(1);
 171         }
 172
 173         if (status & FLASH_WRPRTERR)
 174         {
 175                 LOG_ERROR("stm32x device protected");
 176                 retval = ERROR_FAIL;
 177         }
 178
 179         if (status & FLASH_PGERR)
 180         {
 181                 LOG_ERROR("stm32x device programming failed");
 182                 retval = ERROR_FAIL;
 183         }
 184
 185         /* Clear but report errors */
 186         if (status & (FLASH_WRPRTERR | FLASH_PGERR))
 187         {
 188                 /* If this operation fails, we ignore it and report the original
 189                  * retval
 190                  */
 191                 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
 192                                 FLASH_WRPRTERR | FLASH_PGERR);
 193         }
 194         return retval;
 195 }
 196
 197 int stm32x_check_operation_supported(struct flash_bank *bank)
 198 {
 199         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 200
 201         /* if we have a dual flash bank device then
 202          * we need to perform option byte stuff on bank0 only */
 203         if (stm32x_info->register_offset != FLASH_OFFSET_B0)
 204         {
 205                 LOG_ERROR("Option Byte Operation's must use bank0");
 206                 return ERROR_FLASH_OPERATION_FAILED;
 207         }
 208
 209         return ERROR_OK;
 210 }
 211
 212 static int stm32x_read_options(struct flash_bank *bank)
 213 {
 214         uint32_t optiondata;
 215         struct stm32x_flash_bank *stm32x_info = NULL;
 216         struct target *target = bank->target;
 217
 218         stm32x_info = bank->driver_priv;
 219
 220         /* read current option bytes */
 221         int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 222         if (retval != ERROR_OK)
 223                 return retval;
 224
 225         stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
 226         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 227
 228         if (optiondata & (1 << OPT_READOUT))
 229                 LOG_INFO("Device Security Bit Set");
 230
 231         /* each bit refers to a 4bank protection */
 232         retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235
 236         stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
 237         stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
 238         stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
 239         stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
 240
 241         return ERROR_OK;
 242 }
 243
 244 static int stm32x_erase_options(struct flash_bank *bank)
 245 {
 246         struct stm32x_flash_bank *stm32x_info = NULL;
 247         struct target *target = bank->target;
 248
 249         stm32x_info = bank->driver_priv;
 250
 251         /* read current options */
 252         stm32x_read_options(bank);
 253
 254         /* unlock flash registers */
 255         int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 256         if (retval != ERROR_OK)
 257                 return retval;
 258
 259         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         /* unlock option flash registers */
 264         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 265         if (retval != ERROR_OK)
 266                 return retval;
 267         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 268         if (retval != ERROR_OK)
 269                 return retval;
 270
 271         /* erase option bytes */
 272         retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
 273         if (retval != ERROR_OK)
 274                 return retval;
 275         retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
 276         if (retval != ERROR_OK)
 277                 return retval;
 278
 279         retval = stm32x_wait_status_busy(bank, 10);
 280         if (retval != ERROR_OK)
 281                 return retval;
 282
 283         /* clear readout protection and complementary option bytes
 284          * this will also force a device unlock if set */
 285         stm32x_info->option_bytes.RDP = 0x5AA5;
 286
 287         return ERROR_OK;
 288 }
 289
 290 static int stm32x_write_options(struct flash_bank *bank)
 291 {
 292         struct stm32x_flash_bank *stm32x_info = NULL;
 293         struct target *target = bank->target;
 294
 295         stm32x_info = bank->driver_priv;
 296
 297         /* unlock flash registers */
 298         int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 299         if (retval != ERROR_OK)
 300                 return retval;
 301         retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 302         if (retval != ERROR_OK)
 303                 return retval;
 304
 305         /* unlock option flash registers */
 306         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 307         if (retval != ERROR_OK)
 308                 return retval;
 309         retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         /* program option bytes */
 314         retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
 315         if (retval != ERROR_OK)
 316                 return retval;
 317
 318         /* write user option byte */
 319         retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 320         if (retval != ERROR_OK)
 321                 return retval;
 322
 323         retval = stm32x_wait_status_busy(bank, 10);
 324         if (retval != ERROR_OK)
 325                 return retval;
 326
 327         /* write protection byte 1 */
 328         retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 329         if (retval != ERROR_OK)
 330                 return retval;
 331
 332         retval = stm32x_wait_status_busy(bank, 10);
 333         if (retval != ERROR_OK)
 334                 return retval;
 335
 336         /* write protection byte 2 */
 337         retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 338         if (retval != ERROR_OK)
 339                 return retval;
 340
 341         retval = stm32x_wait_status_busy(bank, 10);
 342         if (retval != ERROR_OK)
 343                 return retval;
 344
 345         /* write protection byte 3 */
 346         retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 347         if (retval != ERROR_OK)
 348                 return retval;
 349
 350         retval = stm32x_wait_status_busy(bank, 10);
 351         if (retval != ERROR_OK)
 352                 return retval;
 353
 354         /* write protection byte 4 */
 355         retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 356         if (retval != ERROR_OK)
 357                 return retval;
 358
 359         retval = stm32x_wait_status_busy(bank, 10);
 360         if (retval != ERROR_OK)
 361                 return retval;
 362
 363         /* write readout protection bit */
 364         retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 365         if (retval != ERROR_OK)
 366                 return retval;
 367
 368         retval = stm32x_wait_status_busy(bank, 10);
 369         if (retval != ERROR_OK)
 370                 return retval;
 371
 372         retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 373         if (retval != ERROR_OK)
 374                 return retval;
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int stm32x_protect_check(struct flash_bank *bank)
 380 {
 381         struct target *target = bank->target;
 382         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 383
 384         uint32_t protection;
 385         int i, s;
 386         int num_bits;
 387         int set;
 388
 389         if (target->state != TARGET_HALTED)
 390         {
 391                 LOG_ERROR("Target not halted");
 392                 return ERROR_TARGET_NOT_HALTED;
 393         }
 394
 395         int retval = stm32x_check_operation_supported(bank);
 396         if (ERROR_OK != retval)
 397                 return retval;
 398
 399         /* medium density - each bit refers to a 4bank protection
 400          * high density - each bit refers to a 2bank protection */
 401         retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
 402         if (retval != ERROR_OK)
 403                 return retval;
 404
 405         /* medium density - each protection bit is for 4 * 1K pages
 406          * high density - each protection bit is for 2 * 2K pages */
 407         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 408
 409         if (stm32x_info->ppage_size == 2)
 410         {
 411                 /* high density flash/connectivity line protection */
 412
 413                 set = 1;
 414
 415                 if (protection & (1 << 31))
 416                         set = 0;
 417
 418                 /* bit 31 controls sector 62 - 255 protection for high density
 419                  * bit 31 controls sector 62 - 127 protection for connectivity line */
 420                 for (s = 62; s < bank->num_sectors; s++)
 421                 {
 422                         bank->sectors[s].is_protected = set;
 423                 }
 424
 425                 if (bank->num_sectors > 61)
 426                         num_bits = 31;
 427
 428                 for (i = 0; i < num_bits; i++)
 429                 {
 430                         set = 1;
 431
 432                         if (protection & (1 << i))
 433                                 set = 0;
 434
 435                         for (s = 0; s < stm32x_info->ppage_size; s++)
 436                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 437                 }
 438         }
 439         else
 440         {
 441                 /* low/medium density flash protection */
 442                 for (i = 0; i < num_bits; i++)
 443                 {
 444                         set = 1;
 445
 446                         if (protection & (1 << i))
 447                                 set = 0;
 448
 449                         for (s = 0; s < stm32x_info->ppage_size; s++)
 450                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 451                 }
 452         }
 453
 454         return ERROR_OK;
 455 }
 456
 457 static int stm32x_erase(struct flash_bank *bank, int first, int last)
 458 {
 459         struct target *target = bank->target;
 460         int i;
 461
 462         if (bank->target->state != TARGET_HALTED)
 463         {
 464                 LOG_ERROR("Target not halted");
 465                 return ERROR_TARGET_NOT_HALTED;
 466         }
 467
 468         if ((first == 0) && (last == (bank->num_sectors - 1)))
 469         {
 470                 return stm32x_mass_erase(bank);
 471         }
 472
 473         /* unlock flash registers */
 474         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 475         if (retval != ERROR_OK)
 476                 return retval;
 477         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 478         if (retval != ERROR_OK)
 479                 return retval;
 480
 481         for (i = first; i <= last; i++)
 482         {
 483                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
 484                 if (retval != ERROR_OK)
 485                         return retval;
 486                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
 487                                 bank->base + bank->sectors[i].offset);
 488                 if (retval != ERROR_OK)
 489                         return retval;
 490                 retval = target_write_u32(target,
 491                                 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
 492                 if (retval != ERROR_OK)
 493                         return retval;
 494
 495                 retval = stm32x_wait_status_busy(bank, 100);
 496                 if (retval != ERROR_OK)
 497                         return retval;
 498
 499                 bank->sectors[i].is_erased = 1;
 500         }
 501
 502         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 503         if (retval != ERROR_OK)
 504                 return retval;
 505
 506         return ERROR_OK;
 507 }
 508
 509 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
 510 {
 511         struct stm32x_flash_bank *stm32x_info = NULL;
 512         struct target *target = bank->target;
 513         uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 514         int i, reg, bit;
 515         int status;
 516         uint32_t protection;
 517
 518         stm32x_info = bank->driver_priv;
 519
 520         if (target->state != TARGET_HALTED)
 521         {
 522                 LOG_ERROR("Target not halted");
 523                 return ERROR_TARGET_NOT_HALTED;
 524         }
 525
 526         int retval = stm32x_check_operation_supported(bank);
 527         if (ERROR_OK != retval)
 528                 return retval;
 529
 530         if ((first % stm32x_info->ppage_size) != 0)
 531         {
 532                 LOG_WARNING("aligned start protect sector to a %d sector boundary",
 533                                 stm32x_info->ppage_size);
 534                 first = first - (first % stm32x_info->ppage_size);
 535         }
 536         if (((last + 1) % stm32x_info->ppage_size) != 0)
 537         {
 538                 LOG_WARNING("aligned end protect sector to a %d sector boundary",
 539                                 stm32x_info->ppage_size);
 540                 last++;
 541                 last = last - (last % stm32x_info->ppage_size);
 542                 last--;
 543         }
 544
 545         /* medium density - each bit refers to a 4bank protection
 546          * high density - each bit refers to a 2bank protection */
 547         retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
 548         if (retval != ERROR_OK)
 549                 return retval;
 550
 551         prot_reg[0] = (uint16_t)protection;
 552         prot_reg[1] = (uint16_t)(protection >> 8);
 553         prot_reg[2] = (uint16_t)(protection >> 16);
 554         prot_reg[3] = (uint16_t)(protection >> 24);
 555
 556         if (stm32x_info->ppage_size == 2)
 557         {
 558                 /* high density flash */
 559
 560                 /* bit 7 controls sector 62 - 255 protection */
 561                 if (last > 61)
 562                 {
 563                         if (set)
 564                                 prot_reg[3] &= ~(1 << 7);
 565                         else
 566                                 prot_reg[3] |= (1 << 7);
 567                 }
 568
 569                 if (first > 61)
 570                         first = 62;
 571                 if (last > 61)
 572                         last = 61;
 573
 574                 for (i = first; i <= last; i++)
 575                 {
 576                         reg = (i / stm32x_info->ppage_size) / 8;
 577                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 578
 579                         if (set)
 580                                 prot_reg[reg] &= ~(1 << bit);
 581                         else
 582                                 prot_reg[reg] |= (1 << bit);
 583                 }
 584         }
 585         else
 586         {
 587                 /* medium density flash */
 588                 for (i = first; i <= last; i++)
 589                 {
 590                         reg = (i / stm32x_info->ppage_size) / 8;
 591                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 592
 593                         if (set)
 594                                 prot_reg[reg] &= ~(1 << bit);
 595                         else
 596                                 prot_reg[reg] |= (1 << bit);
 597                 }
 598         }
 599
 600         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 601                 return status;
 602
 603         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 604         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 605         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 606         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 607
 608         return stm32x_write_options(bank);
 609 }
 610
 611 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 612                 uint32_t offset, uint32_t count)
 613 {
 614         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 615         struct target *target = bank->target;
 616         uint32_t buffer_size = 16384;
 617         struct working_area *source;
 618         uint32_t address = bank->base + offset;
 619         struct reg_param reg_params[4];
 620         struct armv7m_algorithm armv7m_info;
 621         int retval = ERROR_OK;
 622
 623         /* see contib/loaders/flash/stm32x.s for src */
 624
 625         static const uint8_t stm32x_flash_write_code[] = {
 626                                                                         /* #define STM32_FLASH_CR_OFFSET        0x10 */
 627                                                                         /* #define STM32_FLASH_SR_OFFSET        0x0C */
 628                                                                         /* write: */
 629                 0x08, 0x4c,                                     /* ldr  r4, STM32_FLASH_BASE */
 630                 0x1c, 0x44,                                     /* add  r4, r3 */
 631                                                                         /* write_half_word: */
 632                 0x01, 0x23,                                     /* movs r3, #0x01 */
 633                 0x23, 0x61,                                     /* str  r3, [r4, #STM32_FLASH_CR_OFFSET] */
 634                 0x30, 0xf8, 0x02, 0x3b,         /* ldrh r3, [r0], #0x02 */
 635                 0x21, 0xf8, 0x02, 0x3b,         /* strh r3, [r1], #0x02 */
 636                                                                         /* busy: */
 637                 0xe3, 0x68,                                     /* ldr  r3, [r4, #STM32_FLASH_SR_OFFSET] */
 638                 0x13, 0xf0, 0x01, 0x0f,         /* tst  r3, #0x01 */
 639                 0xfb, 0xd0,                                     /* beq  busy */
 640                 0x13, 0xf0, 0x14, 0x0f,         /* tst  r3, #0x14 */
 641                 0x01, 0xd1,                                     /* bne  exit */
 642                 0x01, 0x3a,                                     /* subs r2, r2, #0x01 */
 643                 0xf0, 0xd1,                                     /* bne  write_half_word */
 644                                                                         /* exit: */
 645                 0x00, 0xbe,                                     /* bkpt #0x00 */
 646                 0x00, 0x20, 0x02, 0x40,         /* STM32_FLASH_BASE: .word 0x40022000 */
 647         };
 648
 649         /* flash write code */
 650         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
 651                         &stm32x_info->write_algorithm) != ERROR_OK)
 652         {
 653                 LOG_WARNING("no working area available, can't do block memory writes");
 654                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 655         };
 656
 657         if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
 658                         sizeof(stm32x_flash_write_code),
 659                         (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
 660                 return retval;
 661
 662         /* memory buffer */
 663         while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
 664         {
 665                 buffer_size /= 2;
 666                 if (buffer_size <= 256)
 667                 {
 668                         /* if we already allocated the writing code, but failed to get a
 669                          * buffer, free the algorithm */
 670                         if (stm32x_info->write_algorithm)
 671                                 target_free_working_area(target, stm32x_info->write_algorithm);
 672
 673                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 674                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 675                 }
 676         };
 677
 678         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 679         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 680
 681         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 682         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 683         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 684         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);
 685
 686         while (count > 0)
 687         {
 688                 uint32_t thisrun_count = (count > (buffer_size / 2)) ?
 689                                 (buffer_size / 2) : count;
 690
 691                 if ((retval = target_write_buffer(target, source->address,
 692                                 thisrun_count * 2, buffer)) != ERROR_OK)
 693                         break;
 694
 695                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 696                 buf_set_u32(reg_params[1].value, 0, 32, address);
 697                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 698                 buf_set_u32(reg_params[3].value, 0, 32, stm32x_info->register_offset);
 699
 700                 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
 701                                 stm32x_info->write_algorithm->address,
 702                                 0,
 703                                 10000, &armv7m_info)) != ERROR_OK)
 704                 {
 705                         LOG_ERROR("error executing stm32x flash write algorithm");
 706                         break;
 707                 }
 708
 709                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
 710                 {
 711                         LOG_ERROR("flash memory not erased before writing");
 712                         /* Clear but report errors */
 713                         target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
 714                         retval = ERROR_FAIL;
 715                         break;
 716                 }
 717
 718                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
 719                 {
 720                         LOG_ERROR("flash memory write protected");
 721                         /* Clear but report errors */
 722                         target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
 723                         retval = ERROR_FAIL;
 724                         break;
 725                 }
 726
 727                 buffer += thisrun_count * 2;
 728                 address += thisrun_count * 2;
 729                 count -= thisrun_count;
 730         }
 731
 732         target_free_working_area(target, source);
 733         target_free_working_area(target, stm32x_info->write_algorithm);
 734
 735         destroy_reg_param(&reg_params[0]);
 736         destroy_reg_param(&reg_params[1]);
 737         destroy_reg_param(&reg_params[2]);
 738         destroy_reg_param(&reg_params[3]);
 739
 740         return retval;
 741 }
 742
 743 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 744                 uint32_t offset, uint32_t count)
 745 {
 746         struct target *target = bank->target;
 747         uint32_t words_remaining = (count / 2);
 748         uint32_t bytes_remaining = (count & 0x00000001);
 749         uint32_t address = bank->base + offset;
 750         uint32_t bytes_written = 0;
 751         int retval;
 752
 753         if (bank->target->state != TARGET_HALTED)
 754         {
 755                 LOG_ERROR("Target not halted");
 756                 return ERROR_TARGET_NOT_HALTED;
 757         }
 758
 759         if (offset & 0x1)
 760         {
 761                 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
 762                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 763         }
 764
 765         /* unlock flash registers */
 766         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
 767         if (retval != ERROR_OK)
 768                 return retval;
 769         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
 770         if (retval != ERROR_OK)
 771                 return retval;
 772
 773         /* multiple half words (2-byte) to be programmed? */
 774         if (words_remaining > 0)
 775         {
 776                 /* try using a block write */
 777                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 778                 {
 779                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 780                         {
 781                                 /* if block write failed (no sufficient working area),
 782                                  * we use normal (slow) single dword accesses */
 783                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 784                         }
 785                 }
 786                 else
 787                 {
 788                         buffer += words_remaining * 2;
 789                         address += words_remaining * 2;
 790                         words_remaining = 0;
 791                 }
 792         }
 793
 794         if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
 795                 return retval;
 796
 797         while (words_remaining > 0)
 798         {
 799                 uint16_t value;
 800                 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
 801
 802                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 803                 if (retval != ERROR_OK)
 804                         return retval;
 805                 retval = target_write_u16(target, address, value);
 806                 if (retval != ERROR_OK)
 807                         return retval;
 808
 809                 retval = stm32x_wait_status_busy(bank, 5);
 810                 if (retval != ERROR_OK)
 811                         return retval;
 812
 813                 bytes_written += 2;
 814                 words_remaining--;
 815                 address += 2;
 816         }
 817
 818         if (bytes_remaining)
 819         {
 820                 uint16_t value = 0xffff;
 821                 memcpy(&value, buffer + bytes_written, bytes_remaining);
 822
 823                 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
 824                 if (retval != ERROR_OK)
 825                         return retval;
 826                 retval = target_write_u16(target, address, value);
 827                 if (retval != ERROR_OK)
 828                         return retval;
 829
 830                 retval = stm32x_wait_status_busy(bank, 5);
 831                 if (retval != ERROR_OK)
 832                         return retval;
 833         }
 834
 835         return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 836 }
 837
 838 static int stm32x_probe(struct flash_bank *bank)
 839 {
 840         struct target *target = bank->target;
 841         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 842         int i;
 843         uint16_t num_pages;
 844         uint32_t device_id;
 845         int page_size;
 846         uint32_t base_address = 0x08000000;
 847
 848         stm32x_info->probed = 0;
 849         stm32x_info->register_offset = FLASH_OFFSET_B0;
 850
 851         /* read stm32 device id register */
 852         int retval = target_read_u32(target, 0xE0042000, &device_id);
 853         if (retval != ERROR_OK)
 854                 return retval;
 855         LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 856
 857         /* get flash size from target. */
 858         retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
 859         if (retval != ERROR_OK)
 860         {
 861                 LOG_WARNING("failed reading flash size, default to max target family");
 862                 /* failed reading flash size, default to max target family */
 863                 num_pages = 0xffff;
 864         }
 865
 866         if ((device_id & 0x7ff) == 0x410)
 867         {
 868                 /* medium density - we have 1k pages
 869                  * 4 pages for a protection area */
 870                 page_size = 1024;
 871                 stm32x_info->ppage_size = 4;
 872
 873                 /* check for early silicon */
 874                 if (num_pages == 0xffff)
 875                 {
 876                         /* number of sectors incorrect on revA */
 877                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 878                         num_pages = 128;
 879                 }
 880         }
 881         else if ((device_id & 0x7ff) == 0x412)
 882         {
 883                 /* low density - we have 1k pages
 884                  * 4 pages for a protection area */
 885                 page_size = 1024;
 886                 stm32x_info->ppage_size = 4;
 887
 888                 /* check for early silicon */
 889                 if (num_pages == 0xffff)
 890                 {
 891                         /* number of sectors incorrect on revA */
 892                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
 893                         num_pages = 32;
 894                 }
 895         }
 896         else if ((device_id & 0x7ff) == 0x414)
 897         {
 898                 /* high density - we have 2k pages
 899                  * 2 pages for a protection area */
 900                 page_size = 2048;
 901                 stm32x_info->ppage_size = 2;
 902
 903                 /* check for early silicon */
 904                 if (num_pages == 0xffff)
 905                 {
 906                         /* number of sectors incorrect on revZ */
 907                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
 908                         num_pages = 512;
 909                 }
 910         }
 911         else if ((device_id & 0x7ff) == 0x418)
 912         {
 913                 /* connectivity line density - we have 2k pages
 914                  * 2 pages for a protection area */
 915                 page_size = 2048;
 916                 stm32x_info->ppage_size = 2;
 917
 918                 /* check for early silicon */
 919                 if (num_pages == 0xffff)
 920                 {
 921                         /* number of sectors incorrect on revZ */
 922                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
 923                         num_pages = 256;
 924                 }
 925         }
 926         else if ((device_id & 0x7ff) == 0x420)
 927         {
 928                 /* value line density - we have 1k pages
 929                  * 4 pages for a protection area */
 930                 page_size = 1024;
 931                 stm32x_info->ppage_size = 4;
 932
 933                 /* check for early silicon */
 934                 if (num_pages == 0xffff)
 935                 {
 936                         /* number of sectors may be incorrrect on early silicon */
 937                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
 938                         num_pages = 128;
 939                 }
 940         }
 941         else if ((device_id & 0x7ff) == 0x430)
 942         {
 943                 /* xl line density - we have 2k pages
 944                  * 2 pages for a protection area */
 945                 page_size = 2048;
 946                 stm32x_info->ppage_size = 2;
 947                 stm32x_info->has_dual_banks = true;
 948
 949                 /* check for early silicon */
 950                 if (num_pages == 0xffff)
 951                 {
 952                         /* number of sectors may be incorrrect on early silicon */
 953                         LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
 954                         num_pages = 1024;
 955                 }
 956
 957                 /* split reported size into matching bank */
 958                 if (bank->base != 0x08080000)
 959                 {
 960                         /* bank 0 will be fixed 512k */
 961                         num_pages = 512;
 962                 }
 963                 else
 964                 {
 965                         num_pages -= 512;
 966                         /* bank1 also uses a register offset */
 967                         stm32x_info->register_offset = FLASH_OFFSET_B1;
 968                         base_address = 0x08080000;
 969                 }
 970         }
 971         else
 972         {
 973                 LOG_WARNING("Cannot identify target as a STM32 family.");
 974                 return ERROR_FAIL;
 975         }
 976
 977         LOG_INFO("flash size = %dkbytes", num_pages);
 978
 979         /* calculate numbers of pages */
 980         num_pages /= (page_size / 1024);
 981
 982         if (bank->sectors)
 983         {
 984                 free(bank->sectors);
 985                 bank->sectors = NULL;
 986         }
 987
 988         bank->base = base_address;
 989         bank->size = (num_pages * page_size);
 990         bank->num_sectors = num_pages;
 991         bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 992
 993         for (i = 0; i < num_pages; i++)
 994         {
 995                 bank->sectors[i].offset = i * page_size;
 996                 bank->sectors[i].size = page_size;
 997                 bank->sectors[i].is_erased = -1;
 998                 bank->sectors[i].is_protected = 1;
 999         }
1000
1001         stm32x_info->probed = 1;
1002
1003         return ERROR_OK;
1004 }
1005
1006 static int stm32x_auto_probe(struct flash_bank *bank)
1007 {
1008         struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1009         if (stm32x_info->probed)
1010                 return ERROR_OK;
1011         return stm32x_probe(bank);
1012 }
1013
1014 #if 0
1015 COMMAND_HANDLER(stm32x_handle_part_id_command)
1016 {
1017         return ERROR_OK;
1018 }
1019 #endif
1020
1021 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1022 {
1023         struct target *target = bank->target;
1024         uint32_t device_id;
1025         int printed;
1026
1027         /* read stm32 device id register */
1028         int retval = target_read_u32(target, 0xE0042000, &device_id);
1029         if (retval != ERROR_OK)
1030                 return retval;
1031
1032         if ((device_id & 0x7ff) == 0x410)
1033         {
1034                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1035                 buf += printed;
1036                 buf_size -= printed;
1037
1038                 switch (device_id >> 16)
1039                 {
1040                         case 0x0000:
1041                                 snprintf(buf, buf_size, "A");
1042                                 break;
1043
1044                         case 0x2000:
1045                                 snprintf(buf, buf_size, "B");
1046                                 break;
1047
1048                         case 0x2001:
1049                                 snprintf(buf, buf_size, "Z");
1050                                 break;
1051
1052                         case 0x2003:
1053                                 snprintf(buf, buf_size, "Y");
1054                                 break;
1055
1056                         default:
1057                                 snprintf(buf, buf_size, "unknown");
1058                                 break;
1059                 }
1060         }
1061         else if ((device_id & 0x7ff) == 0x412)
1062         {
1063                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1064                 buf += printed;
1065                 buf_size -= printed;
1066
1067                 switch (device_id >> 16)
1068                 {
1069                         case 0x1000:
1070                                 snprintf(buf, buf_size, "A");
1071                                 break;
1072
1073                         default:
1074                                 snprintf(buf, buf_size, "unknown");
1075                                 break;
1076                 }
1077         }
1078         else if ((device_id & 0x7ff) == 0x414)
1079         {
1080                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1081                 buf += printed;
1082                 buf_size -= printed;
1083
1084                 switch (device_id >> 16)
1085                 {
1086                         case 0x1000:
1087                                 snprintf(buf, buf_size, "A");
1088                                 break;
1089
1090                         case 0x1001:
1091                                 snprintf(buf, buf_size, "Z");
1092                                 break;
1093
1094                         default:
1095                                 snprintf(buf, buf_size, "unknown");
1096                                 break;
1097                 }
1098         }
1099         else if ((device_id & 0x7ff) == 0x418)
1100         {
1101                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1102                 buf += printed;
1103                 buf_size -= printed;
1104
1105                 switch (device_id >> 16)
1106                 {
1107                         case 0x1000:
1108                                 snprintf(buf, buf_size, "A");
1109                                 break;
1110
1111                         case 0x1001:
1112                                 snprintf(buf, buf_size, "Z");
1113                                 break;
1114
1115                         default:
1116                                 snprintf(buf, buf_size, "unknown");
1117                                 break;
1118                 }
1119         }
1120         else if ((device_id & 0x7ff) == 0x420)
1121         {
1122                 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1123                 buf += printed;
1124                 buf_size -= printed;
1125
1126                 switch (device_id >> 16)
1127                 {
1128                         case 0x1000:
1129                                 snprintf(buf, buf_size, "A");
1130                                 break;
1131
1132                         case 0x1001:
1133                                 snprintf(buf, buf_size, "Z");
1134                                 break;
1135
1136                         default:
1137                                 snprintf(buf, buf_size, "unknown");
1138                                 break;
1139                 }
1140         }
1141         else if ((device_id & 0x7ff) == 0x430)
1142         {
1143                 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1144                 buf += printed;
1145                 buf_size -= printed;
1146
1147                 switch (device_id >> 16)
1148                 {
1149                         case 0x1000:
1150                                 snprintf(buf, buf_size, "A");
1151                                 break;
1152
1153                         default:
1154                                 snprintf(buf, buf_size, "unknown");
1155                                 break;
1156                 }
1157         }
1158         else
1159         {
1160                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1161                 return ERROR_FAIL;
1162         }
1163
1164         return ERROR_OK;
1165 }
1166
1167 COMMAND_HANDLER(stm32x_handle_lock_command)
1168 {
1169         struct target *target = NULL;
1170         struct stm32x_flash_bank *stm32x_info = NULL;
1171
1172         if (CMD_ARGC < 1)
1173         {
1174                 command_print(CMD_CTX, "stm32x lock <bank>");
1175                 return ERROR_OK;
1176         }
1177
1178         struct flash_bank *bank;
1179         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1180         if (ERROR_OK != retval)
1181                 return retval;
1182
1183         stm32x_info = bank->driver_priv;
1184
1185         target = bank->target;
1186
1187         if (target->state != TARGET_HALTED)
1188         {
1189                 LOG_ERROR("Target not halted");
1190                 return ERROR_TARGET_NOT_HALTED;
1191         }
1192
1193         retval = stm32x_check_operation_supported(bank);
1194         if (ERROR_OK != retval)
1195                 return retval;
1196
1197         if (stm32x_erase_options(bank) != ERROR_OK)
1198         {
1199                 command_print(CMD_CTX, "stm32x failed to erase options");
1200                 return ERROR_OK;
1201         }
1202
1203         /* set readout protection */
1204         stm32x_info->option_bytes.RDP = 0;
1205
1206         if (stm32x_write_options(bank) != ERROR_OK)
1207         {
1208                 command_print(CMD_CTX, "stm32x failed to lock device");
1209                 return ERROR_OK;
1210         }
1211
1212         command_print(CMD_CTX, "stm32x locked");
1213
1214         return ERROR_OK;
1215 }
1216
1217 COMMAND_HANDLER(stm32x_handle_unlock_command)
1218 {
1219         struct target *target = NULL;
1220
1221         if (CMD_ARGC < 1)
1222         {
1223                 command_print(CMD_CTX, "stm32x unlock <bank>");
1224                 return ERROR_OK;
1225         }
1226
1227         struct flash_bank *bank;
1228         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1229         if (ERROR_OK != retval)
1230                 return retval;
1231
1232         target = bank->target;
1233
1234         if (target->state != TARGET_HALTED)
1235         {
1236                 LOG_ERROR("Target not halted");
1237                 return ERROR_TARGET_NOT_HALTED;
1238         }
1239
1240         retval = stm32x_check_operation_supported(bank);
1241         if (ERROR_OK != retval)
1242                 return retval;
1243
1244         if (stm32x_erase_options(bank) != ERROR_OK)
1245         {
1246                 command_print(CMD_CTX, "stm32x failed to unlock device");
1247                 return ERROR_OK;
1248         }
1249
1250         if (stm32x_write_options(bank) != ERROR_OK)
1251         {
1252                 command_print(CMD_CTX, "stm32x failed to lock device");
1253                 return ERROR_OK;
1254         }
1255
1256         command_print(CMD_CTX, "stm32x unlocked.\n"
1257                         "INFO: a reset or power cycle is required "
1258                         "for the new settings to take effect.");
1259
1260         return ERROR_OK;
1261 }
1262
1263 COMMAND_HANDLER(stm32x_handle_options_read_command)
1264 {
1265         uint32_t optionbyte;
1266         struct target *target = NULL;
1267         struct stm32x_flash_bank *stm32x_info = NULL;
1268
1269         if (CMD_ARGC < 1)
1270         {
1271                 command_print(CMD_CTX, "stm32x options_read <bank>");
1272                 return ERROR_OK;
1273         }
1274
1275         struct flash_bank *bank;
1276         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1277         if (ERROR_OK != retval)
1278                 return retval;
1279
1280         stm32x_info = bank->driver_priv;
1281
1282         target = bank->target;
1283
1284         if (target->state != TARGET_HALTED)
1285         {
1286                 LOG_ERROR("Target not halted");
1287                 return ERROR_TARGET_NOT_HALTED;
1288         }
1289
1290         retval = stm32x_check_operation_supported(bank);
1291         if (ERROR_OK != retval)
1292                 return retval;
1293
1294         retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1295         if (retval != ERROR_OK)
1296                 return retval;
1297         command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1298
1299         if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1300                 command_print(CMD_CTX, "Option Byte Complement Error");
1301
1302         if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1303                 command_print(CMD_CTX, "Readout Protection On");
1304         else
1305                 command_print(CMD_CTX, "Readout Protection Off");
1306
1307         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1308                 command_print(CMD_CTX, "Software Watchdog");
1309         else
1310                 command_print(CMD_CTX, "Hardware Watchdog");
1311
1312         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1313                 command_print(CMD_CTX, "Stop: No reset generated");
1314         else
1315                 command_print(CMD_CTX, "Stop: Reset generated");
1316
1317         if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1318                 command_print(CMD_CTX, "Standby: No reset generated");
1319         else
1320                 command_print(CMD_CTX, "Standby: Reset generated");
1321
1322         if (stm32x_info->has_dual_banks)
1323         {
1324                 if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
1325                         command_print(CMD_CTX, "Boot: Bank 0");
1326                 else
1327                         command_print(CMD_CTX, "Boot: Bank 1");
1328         }
1329
1330         return ERROR_OK;
1331 }
1332
1333 COMMAND_HANDLER(stm32x_handle_options_write_command)
1334 {
1335         struct target *target = NULL;
1336         struct stm32x_flash_bank *stm32x_info = NULL;
1337         uint16_t optionbyte = 0xF8;
1338
1339         if (CMD_ARGC < 4)
1340         {
1341                 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> "
1342                                 "<RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP> <BOOT0 | BOOT1>");
1343                 return ERROR_OK;
1344         }
1345
1346         struct flash_bank *bank;
1347         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1348         if (ERROR_OK != retval)
1349                 return retval;
1350
1351         stm32x_info = bank->driver_priv;
1352
1353         target = bank->target;
1354
1355         if (target->state != TARGET_HALTED)
1356         {
1357                 LOG_ERROR("Target not halted");
1358                 return ERROR_TARGET_NOT_HALTED;
1359         }
1360
1361         retval = stm32x_check_operation_supported(bank);
1362         if (ERROR_OK != retval)
1363                 return retval;
1364
1365         /* REVISIT: ignores some options which we will display...
1366          * and doesn't insist on the specified syntax.
1367          */
1368
1369         /* OPT_RDWDGSW */
1370         if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1371         {
1372                 optionbyte |= (1 << 0);
1373         }
1374         else    /* REVISIT must be "HWWDG" then ... */
1375         {
1376                 optionbyte &= ~(1 << 0);
1377         }
1378
1379         /* OPT_RDRSTSTOP */
1380         if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
1381         {
1382                 optionbyte |= (1 << 1);
1383         }
1384         else    /* REVISIT must be "RSTSTNDBY" then ... */
1385         {
1386                 optionbyte &= ~(1 << 1);
1387         }
1388
1389         /* OPT_RDRSTSTDBY */
1390         if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
1391         {
1392                 optionbyte |= (1 << 2);
1393         }
1394         else    /* REVISIT must be "RSTSTOP" then ... */
1395         {
1396                 optionbyte &= ~(1 << 2);
1397         }
1398
1399         if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
1400         {
1401                 /* OPT_BFB2 */
1402                 if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
1403                 {
1404                         optionbyte |= (1 << 3);
1405                 }
1406                 else
1407                 {
1408                         optionbyte &= ~(1 << 3);
1409                 }
1410         }
1411
1412         if (stm32x_erase_options(bank) != ERROR_OK)
1413         {
1414                 command_print(CMD_CTX, "stm32x failed to erase options");
1415                 return ERROR_OK;
1416         }
1417
1418         stm32x_info->option_bytes.user_options = optionbyte;
1419
1420         if (stm32x_write_options(bank) != ERROR_OK)
1421         {
1422                 command_print(CMD_CTX, "stm32x failed to write options");
1423                 return ERROR_OK;
1424         }
1425
1426         command_print(CMD_CTX, "stm32x write options complete.\n"
1427                                 "INFO: a reset or power cycle is required "
1428                                 "for the new settings to take effect.");
1429
1430         return ERROR_OK;
1431 }
1432
1433 static int stm32x_mass_erase(struct flash_bank *bank)
1434 {
1435         struct target *target = bank->target;
1436
1437         if (target->state != TARGET_HALTED)
1438         {
1439                 LOG_ERROR("Target not halted");
1440                 return ERROR_TARGET_NOT_HALTED;
1441         }
1442
1443         /* unlock option flash registers */
1444         int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1445         if (retval != ERROR_OK)
1446                 return retval;
1447         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1448         if (retval != ERROR_OK)
1449                 return retval;
1450
1451         /* mass erase flash memory */
1452         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1453         if (retval != ERROR_OK)
1454                 return retval;
1455         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
1456         if (retval != ERROR_OK)
1457                 return retval;
1458
1459         retval = stm32x_wait_status_busy(bank, 100);
1460         if (retval != ERROR_OK)
1461                 return retval;
1462
1463         retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1464         if (retval != ERROR_OK)
1465                 return retval;
1466
1467         return ERROR_OK;
1468 }
1469
1470 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1471 {
1472         int i;
1473
1474         if (CMD_ARGC < 1)
1475         {
1476                 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1477                 return ERROR_OK;
1478         }
1479
1480         struct flash_bank *bank;
1481         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1482         if (ERROR_OK != retval)
1483                 return retval;
1484
1485         retval = stm32x_mass_erase(bank);
1486         if (retval == ERROR_OK)
1487         {
1488                 /* set all sectors as erased */
1489                 for (i = 0; i < bank->num_sectors; i++)
1490                 {
1491                         bank->sectors[i].is_erased = 1;
1492                 }
1493
1494                 command_print(CMD_CTX, "stm32x mass erase complete");
1495         }
1496         else
1497         {
1498                 command_print(CMD_CTX, "stm32x mass erase failed");
1499         }
1500
1501         return retval;
1502 }
1503
1504 static const struct command_registration stm32x_exec_command_handlers[] = {
1505         {
1506                 .name = "lock",
1507                 .handler = stm32x_handle_lock_command,
1508                 .mode = COMMAND_EXEC,
1509                 .usage = "bank_id",
1510                 .help = "Lock entire flash device.",
1511         },
1512         {
1513                 .name = "unlock",
1514                 .handler = stm32x_handle_unlock_command,
1515                 .mode = COMMAND_EXEC,
1516                 .usage = "bank_id",
1517                 .help = "Unlock entire protected flash device.",
1518         },
1519         {
1520                 .name = "mass_erase",
1521                 .handler = stm32x_handle_mass_erase_command,
1522                 .mode = COMMAND_EXEC,
1523                 .usage = "bank_id",
1524                 .help = "Erase entire flash device.",
1525         },
1526         {
1527                 .name = "options_read",
1528                 .handler = stm32x_handle_options_read_command,
1529                 .mode = COMMAND_EXEC,
1530                 .usage = "bank_id",
1531                 .help = "Read and display device option byte.",
1532         },
1533         {
1534                 .name = "options_write",
1535                 .handler = stm32x_handle_options_write_command,
1536                 .mode = COMMAND_EXEC,
1537                 .usage = "bank_id ('SWWDG'|'HWWDG') "
1538                         "('RSTSTNDBY'|'NORSTSTNDBY') "
1539                         "('RSTSTOP'|'NORSTSTOP')",
1540                 .help = "Replace bits in device option byte.",
1541         },
1542         COMMAND_REGISTRATION_DONE
1543 };
1544
1545 static const struct command_registration stm32x_command_handlers[] = {
1546         {
1547                 .name = "stm32x",
1548                 .mode = COMMAND_ANY,
1549                 .help = "stm32x flash command group",
1550                 .chain = stm32x_exec_command_handlers,
1551         },
1552         COMMAND_REGISTRATION_DONE
1553 };
1554
1555 struct flash_driver stm32x_flash = {
1556         .name = "stm32x",
1557         .commands = stm32x_command_handlers,
1558         .flash_bank_command = stm32x_flash_bank_command,
1559         .erase = stm32x_erase,
1560         .protect = stm32x_protect,
1561         .write = stm32x_write,
1562         .read = default_flash_read,
1563         .probe = stm32x_probe,
1564         .auto_probe = stm32x_auto_probe,
1565         .erase_check = default_flash_mem_blank_check,
1566         .protect_check = stm32x_protect_check,
1567         .info = get_stm32x_info,
1568 };