git.sur5r.net Git - openocd/blob - src/flash/nor/xmc4xxx.c

   1 /**************************************************************************
   2 *   Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com>         *
   3 *                                                                         *
   4 *   This program is free software; you can redistribute it and/or modify  *
   5 *   it under the terms of the GNU General Public License as published by  *
   6 *   the Free Software Foundation; either version 2 of the License, or     *
   7 *   (at your option) any later version.                                   *
   8 *                                                                         *
   9 *   This program is distributed in the hope that it will be useful,       *
  10 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12 *   GNU General Public License for more details.                          *
  13 *                                                                         *
  14 ***************************************************************************/
  15
  16 #ifdef HAVE_CONFIG_H
  17 #include "config.h"
  18 #endif
  19
  20 #include "imp.h"
  21 #include <helper/binarybuffer.h>
  22 #include <target/algorithm.h>
  23 #include <target/armv7m.h>
  24
  25 /* Maximum number of sectors */
  26 #define MAX_XMC_SECTORS 12
  27
  28 /* System control unit registers */
  29 #define SCU_REG_BASE 0x50004000
  30
  31 #define SCU_ID_CHIP 0x04
  32
  33 /* Base of the non-cached flash memory */
  34 #define PFLASH_BASE     0x0C000000
  35
  36 /* User configuration block offsets */
  37 #define UCB0_BASE       0x00000000
  38 #define UCB1_BASE       0x00000400
  39 #define UCB2_BASE       0x00000800
  40
  41 /* Flash register base */
  42 #define FLASH_REG_BASE 0x58000000
  43
  44 /* PMU ID Registers */
  45 #define FLASH_REG_PMU_ID        (FLASH_REG_BASE | 0x0508)
  46
  47 /* PMU Fields */
  48 #define PMU_MOD_REV_MASK        0xFF
  49 #define PMU_MOD_TYPE_MASK       0xFF00
  50 #define PMU_MOD_NO_MASK         0xFFFF0000
  51
  52 /* Prefetch Config */
  53 #define FLASH_REG_PREF_PCON     (FLASH_REG_BASE | 0x4000)
  54
  55 /* Prefetch Fields */
  56 #define PCON_IBYP       (1 << 0)
  57 #define PCON_IINV       (1 << 1)
  58
  59 /* Flash ID Register */
  60 #define FLASH_REG_FLASH0_ID     (FLASH_REG_BASE | 0x2008)
  61
  62 /* Flash Status Register */
  63 #define FLASH_REG_FLASH0_FSR    (FLASH_REG_BASE | 0x2010)
  64
  65 #define FSR_PBUSY       (0)
  66 #define FSR_FABUSY      (1)
  67 #define FSR_PROG        (4)
  68 #define FSR_ERASE       (5)
  69 #define FSR_PFPAGE      (6)
  70 #define FSR_PFOPER      (8)
  71 #define FSR_SQER        (10)
  72 #define FSR_PROER       (11)
  73 #define FSR_PFSBER      (12)
  74 #define FSR_PFDBER      (14)
  75 #define FSR_PROIN       (16)
  76 #define FSR_RPROIN      (18)
  77 #define FSR_RPRODIS     (19)
  78 #define FSR_WPROIN0     (21)
  79 #define FSR_WPROIN1     (22)
  80 #define FSR_WPROIN2     (23)
  81 #define FSR_WPRODIS0    (25)
  82 #define FSR_WPRODIS1    (26)
  83 #define FSR_SLM         (28)
  84 #define FSR_VER         (31)
  85
  86 #define FSR_PBUSY_MASK          (0x01 << FSR_PBUSY)
  87 #define FSR_FABUSY_MASK         (0x01 << FSR_FABUSY)
  88 #define FSR_PROG_MASK           (0x01 << FSR_PROG)
  89 #define FSR_ERASE_MASK          (0x01 << FSR_ERASE)
  90 #define FSR_PFPAGE_MASK         (0x01 << FSR_PFPAGE)
  91 #define FSR_PFOPER_MASK         (0x01 << FSR_PFOPER)
  92 #define FSR_SQER_MASK           (0x01 << FSR_SQER)
  93 #define FSR_PROER_MASK          (0x01 << FSR_PROER)
  94 #define FSR_PFSBER_MASK         (0x01 << FSR_PFSBER)
  95 #define FSR_PFDBER_MASK         (0x01 << FSR_PFDBER)
  96 #define FSR_PROIN_MASK          (0x01 << FSR_PROIN)
  97 #define FSR_RPROIN_MASK         (0x01 << FSR_RPROIN)
  98 #define FSR_RPRODIS_MASK        (0x01 << FSR_RPRODIS)
  99 #define FSR_WPROIN0_MASK        (0x01 << FSR_WPROIN0)
 100 #define FSR_WPROIN1_MASK        (0x01 << FSR_WPROIN1)
 101 #define FSR_WPROIN2_MASK        (0x01 << FSR_WPROIN2)
 102 #define FSR_WPRODIS0_MASK       (0x01 << FSR_WPRODIS0)
 103 #define FSR_WPRODIS1_MASK       (0x01 << FSR_WPRODIS1)
 104 #define FSR_SLM_MASK            (0x01 << FSR_SLM)
 105 #define FSR_VER_MASK            (0x01 << FSR_VER)
 106
 107 /* Flash Config Register */
 108 #define FLASH_REG_FLASH0_FCON   (FLASH_REG_BASE | 0x2014)
 109
 110 #define FCON_WSPFLASH           (0)
 111 #define FCON_WSECPF             (4)
 112 #define FCON_IDLE               (13)
 113 #define FCON_ESLDIS             (14)
 114 #define FCON_SLEEP              (15)
 115 #define FCON_RPA                (16)
 116 #define FCON_DCF                (17)
 117 #define FCON_DDF                (18)
 118 #define FCON_VOPERM             (24)
 119 #define FCON_SQERM              (25)
 120 #define FCON_PROERM             (26)
 121 #define FCON_PFSBERM            (27)
 122 #define FCON_PFDBERM            (29)
 123 #define FCON_EOBM               (31)
 124
 125 #define FCON_WSPFLASH_MASK      (0x0f << FCON_WSPFLASH)
 126 #define FCON_WSECPF_MASK        (0x01 << FCON_WSECPF)
 127 #define FCON_IDLE_MASK          (0x01 << FCON_IDLE)
 128 #define FCON_ESLDIS_MASK        (0x01 << FCON_ESLDIS)
 129 #define FCON_SLEEP_MASK         (0x01 << FCON_SLEEP)
 130 #define FCON_RPA_MASK           (0x01 << FCON_RPA)
 131 #define FCON_DCF_MASK           (0x01 << FCON_DCF)
 132 #define FCON_DDF_MASK           (0x01 << FCON_DDF)
 133 #define FCON_VOPERM_MASK        (0x01 << FCON_VOPERM)
 134 #define FCON_SQERM_MASK         (0x01 << FCON_SQERM)
 135 #define FCON_PROERM_MASK        (0x01 << FCON_PROERM)
 136 #define FCON_PFSBERM_MASK       (0x01 << FCON_PFSBERM)
 137 #define FCON_PFDBERM_MASK       (0x01 << FCON_PFDBERM)
 138 #define FCON_EOBM_MASK          (0x01 << FCON_EOBM)
 139
 140 /* Flash Margin Control Register */
 141 #define FLASH_REG_FLASH0_MARP   (FLASH_REG_BASE | 0x2018)
 142
 143 #define MARP_MARGIN             (0)
 144 #define MARP_TRAPDIS            (15)
 145
 146 #define MARP_MARGIN_MASK        (0x0f << MARP_MARGIN)
 147 #define MARP_TRAPDIS_MASK       (0x01 << MARP_TRAPDIS)
 148
 149 /* Flash Protection Registers */
 150 #define FLASH_REG_FLASH0_PROCON0        (FLASH_REG_BASE | 0x2020)
 151 #define FLASH_REG_FLASH0_PROCON1        (FLASH_REG_BASE | 0x2024)
 152 #define FLASH_REG_FLASH0_PROCON2        (FLASH_REG_BASE | 0x2028)
 153
 154 #define PROCON_S0L             (0)
 155 #define PROCON_S1L             (1)
 156 #define PROCON_S2L             (2)
 157 #define PROCON_S3L             (3)
 158 #define PROCON_S4L             (4)
 159 #define PROCON_S5L             (5)
 160 #define PROCON_S6L             (6)
 161 #define PROCON_S7L             (7)
 162 #define PROCON_S8L             (8)
 163 #define PROCON_S9L             (9)
 164 #define PROCON_S10_S11L        (10)
 165 #define PROCON_RPRO            (15)
 166
 167 #define PROCON_S0L_MASK        (0x01 << PROCON_S0L)
 168 #define PROCON_S1L_MASK        (0x01 << PROCON_S1L)
 169 #define PROCON_S2L_MASK        (0x01 << PROCON_S2L)
 170 #define PROCON_S3L_MASK        (0x01 << PROCON_S3L)
 171 #define PROCON_S4L_MASK        (0x01 << PROCON_S4L)
 172 #define PROCON_S5L_MASK        (0x01 << PROCON_S5L)
 173 #define PROCON_S6L_MASK        (0x01 << PROCON_S6L)
 174 #define PROCON_S7L_MASK        (0x01 << PROCON_S7L)
 175 #define PROCON_S8L_MASK        (0x01 << PROCON_S8L)
 176 #define PROCON_S9L_MASK        (0x01 << PROCON_S9L)
 177 #define PROCON_S10_S11L_MASK   (0x01 << PROCON_S10_S11L)
 178 #define PROCON_RPRO_MASK       (0x01 << PROCON_RPRO)
 179
 180 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
 181
 182 /* Flash controller configuration values */
 183 #define FLASH_ID_XMC4500        0xA2
 184 #define FLASH_ID_XMC4100_4200   0x9C
 185 #define FLASH_ID_XMC4400        0x9F
 186
 187 /* Timeouts */
 188 #define FLASH_OP_TIMEOUT 5000
 189
 190 /* Flash commands (write/erase/protect) are performed using special
 191  * command sequences that are written to magic addresses in the flash controller */
 192 /* Command sequence addresses.  See reference manual, section 8: Flash Command Sequences */
 193 #define FLASH_CMD_ERASE_1 0x0C005554
 194 #define FLASH_CMD_ERASE_2 0x0C00AAA8
 195 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
 196 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
 197 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
 198 /* ERASE_6 is the sector base address */
 199
 200 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
 201
 202 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
 203
 204 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
 205 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
 206
 207 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
 208 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
 209 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
 210 /* WRITE_PAGE_4 is the page base address */
 211
 212 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
 213 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
 214 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
 215 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
 216 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
 217 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
 218
 219 struct xmc4xxx_flash_bank {
 220         bool probed;
 221
 222         /* We need the flash controller ID to choose the sector layout */
 223         uint32_t fcon_id;
 224
 225         /* Passwords used for protection operations */
 226         uint32_t pw1;
 227         uint32_t pw2;
 228         bool pw_set;
 229
 230         /* Protection flags */
 231         bool read_protected;
 232
 233         bool write_prot_otp[MAX_XMC_SECTORS];
 234 };
 235
 236 struct xmc4xxx_command_seq {
 237         uint32_t address;
 238         uint32_t magic;
 239 };
 240
 241 /* Sector capacities.  See section 8 of xmc4x00_rm */
 242 static unsigned int sector_capacity_8[] = {
 243         16, 16, 16, 16, 16, 16, 16, 128
 244 };
 245
 246 static unsigned int sector_capacity_9[] = {
 247         16, 16, 16, 16, 16, 16, 16, 128, 256
 248 };
 249
 250 static unsigned int sector_capacity_12[] = {
 251         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
 252 };
 253
 254 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
 255                                          struct xmc4xxx_command_seq *seq,
 256                                          int seq_len)
 257 {
 258         int res = ERROR_OK;
 259
 260         for (int i = 0; i < seq_len; i++) {
 261                 res = target_write_u32(bank->target, seq[i].address,
 262                                        seq[i].magic);
 263                 if (res != ERROR_OK)
 264                         return res;
 265         }
 266
 267         return ERROR_OK;
 268 }
 269
 270 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
 271 {
 272         unsigned int *capacity = NULL;
 273
 274         /* At this point, we know which flash controller ID we're
 275          * talking to and simply need to fill out the bank structure accordingly */
 276         LOG_DEBUG("%d sectors", bank->num_sectors);
 277
 278         switch (bank->num_sectors) {
 279         case 8:
 280                 capacity = sector_capacity_8;
 281                 break;
 282         case 9:
 283                 capacity = sector_capacity_9;
 284                 break;
 285         case 12:
 286                 capacity = sector_capacity_12;
 287                 break;
 288         default:
 289                 LOG_ERROR("Unexpected number of sectors, %d\n",
 290                           bank->num_sectors);
 291                 return ERROR_FAIL;
 292         }
 293
 294         /* This looks like a bank that we understand, now we know the
 295          * corresponding sector capacities and we can add those up into the
 296          * bank size. */
 297         uint32_t total_offset = 0;
 298         bank->sectors = calloc(bank->num_sectors,
 299                                sizeof(struct flash_sector));
 300         for (int i = 0; i < bank->num_sectors; i++) {
 301                 bank->sectors[i].size = capacity[i] * 1024;
 302                 bank->sectors[i].offset = total_offset;
 303                 bank->sectors[i].is_erased = -1;
 304                 bank->sectors[i].is_protected = -1;
 305
 306                 bank->size += bank->sectors[i].size;
 307                 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
 308                 total_offset += bank->sectors[i].size;
 309         }
 310
 311         /* This part doesn't follow the typical standard of 0xff
 312          * being the default padding value.*/
 313         bank->default_padded_value = 0x00;
 314
 315         return ERROR_OK;
 316 }
 317
 318 static int xmc4xxx_probe(struct flash_bank *bank)
 319 {
 320         int res;
 321         uint32_t devid, config;
 322         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 323         uint8_t flash_id;
 324
 325         if (fb->probed)
 326                 return ERROR_OK;
 327
 328         /* It's not possible for the DAP to access the OTP locations needed for
 329          * probing the part info and Flash geometry so we require that the target
 330          * be halted before proceeding. */
 331         if (bank->target->state != TARGET_HALTED) {
 332                 LOG_WARNING("Cannot communicate... target not halted.");
 333                 return ERROR_TARGET_NOT_HALTED;
 334         }
 335
 336         /* The SCU registers contain the ID of the chip */
 337         res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
 338         if (res != ERROR_OK) {
 339                 LOG_ERROR("Cannot read device identification register.");
 340                 return res;
 341         }
 342
 343         /* Make sure this is a XMC4000 family device */
 344         if ((devid & 0xF0000) != 0x40000) {
 345                 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
 346                 return ERROR_FAIL;
 347         }
 348
 349         LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
 350
 351         /* Now sanity-check the Flash controller itself. */
 352         res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
 353                         &config);
 354         if (res != ERROR_OK) {
 355                 LOG_ERROR("Cannot read Flash bank configuration.");
 356                 return res;
 357         }
 358         flash_id = (config & 0xff0000) >> 16;
 359
 360         /* The Flash configuration register is our only means of
 361          * determining the sector layout. We need to make sure that
 362          * we understand the type of controller we're dealing with */
 363         switch (flash_id) {
 364         case FLASH_ID_XMC4100_4200:
 365                 bank->num_sectors = 8;
 366                 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
 367                 break;
 368         case FLASH_ID_XMC4400:
 369                 bank->num_sectors = 9;
 370                 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
 371                 break;
 372         case FLASH_ID_XMC4500:
 373                 bank->num_sectors = 12;
 374                 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
 375                 break;
 376         default:
 377                 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
 378                           flash_id);
 379                 return ERROR_FAIL;
 380         }
 381
 382         /* Retrieve information about the particular bank we're probing and fill in
 383          * the bank structure accordingly. */
 384         res = xmc4xxx_load_bank_layout(bank);
 385         if (res == ERROR_OK) {
 386                 /* We're done */
 387                 fb->probed = true;
 388         } else {
 389                 LOG_ERROR("Unable to load bank information.");
 390                 return ERROR_FAIL;
 391         }
 392
 393         return ERROR_OK;
 394 }
 395
 396 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
 397                                          int sector, uint32_t *ret_addr)
 398 {
 399         /* Make sure we understand this sector */
 400         if (sector > bank->num_sectors)
 401                 return ERROR_FAIL;
 402
 403         *ret_addr = bank->base + bank->sectors[sector].offset;
 404
 405         return ERROR_OK;
 406
 407 }
 408
 409 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
 410 {
 411         int res;
 412         /* TODO: Do we need to check for sequence error? */
 413         LOG_INFO("Clearing flash status");
 414         res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
 415                                0xF5);
 416         if (res != ERROR_OK) {
 417                 LOG_ERROR("Unable to write erase command sequence");
 418                 return res;
 419         }
 420
 421         return ERROR_OK;
 422 }
 423
 424 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
 425 {
 426         int res;
 427
 428         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
 429
 430         if (res != ERROR_OK)
 431                 LOG_ERROR("Cannot read flash status register.");
 432
 433         return res;
 434 }
 435
 436 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
 437 {
 438         int res;
 439         uint32_t status;
 440
 441         res = xmc4xxx_get_flash_status(bank, &status);
 442         if (res != ERROR_OK)
 443                 return res;
 444
 445         /* While the flash controller is busy, wait */
 446         while (status & FSR_PBUSY_MASK) {
 447                 res = xmc4xxx_get_flash_status(bank, &status);
 448                 if (res != ERROR_OK)
 449                         return res;
 450
 451                 if (timeout-- <= 0) {
 452                         LOG_ERROR("Timed out waiting for flash");
 453                         return ERROR_FAIL;
 454                 }
 455                 alive_sleep(1);
 456                 keep_alive();
 457         }
 458
 459         if (status & FSR_PROER_MASK) {
 460                 LOG_ERROR("XMC4xxx flash protected");
 461                 res = ERROR_FAIL;
 462         }
 463
 464         return res;
 465 }
 466
 467 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
 468                                 bool user_config)
 469 {
 470         int res;
 471         uint32_t status;
 472
 473         /* See reference manual table 8.4: Command Sequences for Flash Control */
 474         struct xmc4xxx_command_seq erase_cmd_seq[6] = {
 475                 {FLASH_CMD_ERASE_1, 0xAA},
 476                 {FLASH_CMD_ERASE_2, 0x55},
 477                 {FLASH_CMD_ERASE_3, 0x80},
 478                 {FLASH_CMD_ERASE_4, 0xAA},
 479                 {FLASH_CMD_ERASE_5, 0x55},
 480                 {0xFF,              0xFF} /* Needs filled in */
 481         };
 482
 483         /* We need to fill in the base address of the sector we'll be
 484          * erasing, as well as the magic code that determines whether
 485          * this is a standard flash sector or a user configuration block */
 486
 487         erase_cmd_seq[5].address = address;
 488         if (user_config) {
 489                 /* Removing flash protection requires the addition of
 490                  * the base address */
 491                 erase_cmd_seq[5].address += bank->base;
 492                 erase_cmd_seq[5].magic = 0xC0;
 493         } else {
 494                 erase_cmd_seq[5].magic = 0x30;
 495         }
 496
 497         res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
 498                                              ARRAY_SIZE(erase_cmd_seq));
 499         if (res != ERROR_OK)
 500                 return res;
 501
 502         /* Read the flash status register */
 503         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
 504         if (res != ERROR_OK) {
 505                 LOG_ERROR("Cannot read flash status register.");
 506                 return res;
 507         }
 508
 509         /* Check for a sequence error */
 510         if (status & FSR_SQER_MASK) {
 511                 LOG_ERROR("Error with flash erase sequence");
 512                 return ERROR_FAIL;
 513         }
 514
 515         /* Make sure a flash erase was triggered */
 516         if (!(status & FSR_ERASE_MASK)) {
 517                 LOG_ERROR("Flash failed to erase");
 518                 return ERROR_FAIL;
 519         }
 520
 521         /* Now we must wait for the erase operation to end */
 522         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 523
 524         return res;
 525 }
 526
 527 static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
 528 {
 529         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 530         int res;
 531
 532         if (bank->target->state != TARGET_HALTED) {
 533                 LOG_ERROR("Unable to erase, target is not halted");
 534                 return ERROR_TARGET_NOT_HALTED;
 535         }
 536
 537         if (!fb->probed) {
 538                 res = xmc4xxx_probe(bank);
 539                 if (res != ERROR_OK)
 540                         return res;
 541         }
 542
 543         uint32_t tmp_addr;
 544         /* Loop through the sectors and erase each one */
 545         for (int i = first; i <= last; i++) {
 546                 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
 547                 if (res != ERROR_OK) {
 548                         LOG_ERROR("Invalid sector %d", i);
 549                         return res;
 550                 }
 551
 552                 LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
 553
 554                 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
 555                 if (res != ERROR_OK) {
 556                         LOG_ERROR("Unable to write erase command sequence");
 557                         goto clear_status_and_exit;
 558                 }
 559
 560                 /* Now we must wait for the erase operation to end */
 561                 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 562
 563                 if (res != ERROR_OK)
 564                         goto clear_status_and_exit;
 565
 566                 bank->sectors[i].is_erased = 1;
 567         }
 568
 569 clear_status_and_exit:
 570         res = xmc4xxx_clear_flash_status(bank);
 571         return res;
 572
 573 }
 574
 575 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
 576 {
 577         int res;
 578         uint32_t status;
 579
 580         res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
 581         if (res != ERROR_OK) {
 582                 LOG_ERROR("Unable to write enter page mode command");
 583                 return ERROR_FAIL;
 584         }
 585
 586         res = xmc4xxx_get_flash_status(bank, &status);
 587
 588         if (res != ERROR_OK)
 589                 return res;
 590
 591         /* Make sure we're in page mode */
 592         if (!(status & FSR_PFPAGE_MASK)) {
 593                 LOG_ERROR("Unable to enter page mode");
 594                 return ERROR_FAIL;
 595         }
 596
 597         /* Make sure we didn't encounter a sequence error */
 598         if (status & FSR_SQER_MASK) {
 599                 LOG_ERROR("Sequence error while entering page mode");
 600                 return ERROR_FAIL;
 601         }
 602
 603         return res;
 604 }
 605
 606 /* The logical erase value of an xmc4xxx memory cell is 0x00,
 607  * therefore, we cannot use the built in flash blank check and must
 608  * implement our own */
 609
 610 /** Checks whether a memory region is zeroed. */
 611 int xmc4xxx_blank_check_memory(struct target *target,
 612         uint32_t address, uint32_t count, uint32_t *blank)
 613 {
 614         struct working_area *erase_check_algorithm;
 615         struct reg_param reg_params[3];
 616         struct armv7m_algorithm armv7m_info;
 617         int retval;
 618
 619         /* see contrib/loaders/erase_check/armv7m_0_erase_check.s for src */
 620
 621         static const uint8_t erase_check_code[] = {
 622                 /* loop: */
 623                 0x03, 0x78,             /* ldrb r3, [r0] */
 624                 0x01, 0x30,             /* adds r0, #1 */
 625                 0x1A, 0x43,             /* orrs r2, r2, r3 */
 626                 0x01, 0x39,             /* subs r1, r1, #1 */
 627                 0xFA, 0xD1,             /* bne  loop */
 628                 0x00, 0xBE              /* bkpt #0 */
 629         };
 630
 631         /* make sure we have a working area */
 632         if (target_alloc_working_area(target, sizeof(erase_check_code),
 633                 &erase_check_algorithm) != ERROR_OK)
 634                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 635
 636         retval = target_write_buffer(target, erase_check_algorithm->address,
 637                         sizeof(erase_check_code), (uint8_t *)erase_check_code);
 638         if (retval != ERROR_OK)
 639                 return retval;
 640
 641         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 642         armv7m_info.core_mode = ARM_MODE_THREAD;
 643
 644         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 645         buf_set_u32(reg_params[0].value, 0, 32, address);
 646
 647         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 648         buf_set_u32(reg_params[1].value, 0, 32, count);
 649
 650         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 651         buf_set_u32(reg_params[2].value, 0, 32, 0x00);
 652
 653         retval = target_run_algorithm(target,
 654                                       0,
 655                                       NULL,
 656                                       3,
 657                                       reg_params,
 658                                       erase_check_algorithm->address,
 659                                       erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
 660                                       10000,
 661                                       &armv7m_info);
 662
 663         if (retval == ERROR_OK)
 664                 *blank = buf_get_u32(reg_params[2].value, 0, 32);
 665
 666         destroy_reg_param(&reg_params[0]);
 667         destroy_reg_param(&reg_params[1]);
 668         destroy_reg_param(&reg_params[2]);
 669
 670         target_free_working_area(target, erase_check_algorithm);
 671
 672         return retval;
 673 }
 674
 675 static int xmc4xxx_flash_blank_check(struct flash_bank *bank)
 676 {
 677         struct target *target = bank->target;
 678         int i;
 679         int retval;
 680         uint32_t blank;
 681
 682         if (bank->target->state != TARGET_HALTED) {
 683                 LOG_ERROR("Target not halted");
 684                 return ERROR_TARGET_NOT_HALTED;
 685         }
 686
 687         for (i = 0; i < bank->num_sectors; i++) {
 688                 uint32_t address = bank->base + bank->sectors[i].offset;
 689                 uint32_t size = bank->sectors[i].size;
 690
 691                 LOG_DEBUG("Erase checking 0x%08"PRIx32, address);
 692                 retval = xmc4xxx_blank_check_memory(target, address, size, &blank);
 693
 694                 if (retval != ERROR_OK)
 695                         break;
 696
 697                 if (blank == 0x00)
 698                         bank->sectors[i].is_erased = 1;
 699                 else
 700                         bank->sectors[i].is_erased = 0;
 701         }
 702
 703         return ERROR_OK;
 704 }
 705
 706 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
 707                               uint32_t offset, bool user_config)
 708 {
 709         int res;
 710         uint32_t status;
 711
 712         /* Base of the flash write command */
 713         struct xmc4xxx_command_seq write_cmd_seq[4] = {
 714                 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
 715                 {FLASH_CMD_WRITE_PAGE_2, 0x55},
 716                 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
 717                 {0xFF,                   0xFF}  /* Needs filled in */
 718         };
 719
 720         /* The command sequence differs depending on whether this is
 721          * being written to standard flash or the user configuration
 722          * area */
 723         if (user_config)
 724                 write_cmd_seq[2].magic = 0xC0;
 725         else
 726                 write_cmd_seq[2].magic = 0xA0;
 727
 728         /* Finally, we need to add the address that this page will be
 729          * written to */
 730         write_cmd_seq[3].address = bank->base + offset;
 731         write_cmd_seq[3].magic = 0xAA;
 732
 733
 734         /* Flash pages are written 256 bytes at a time.  For each 256
 735          * byte chunk, we need to:
 736          * 1. Enter page mode. This activates the flash write buffer
 737          * 2. Load the page buffer with data (2x 32 bit words at a time)
 738          * 3. Burn the page buffer into its intended location
 739          * If the starting offset is not on a 256 byte boundary, we
 740          * will need to pad the beginning of the write buffer
 741          * accordingly. Likewise, if the last page does not fill the
 742          * buffer, we should pad it to avoid leftover data from being
 743          * written to flash
 744          */
 745         res = xmc4xxx_enter_page_mode(bank);
 746         if (res != ERROR_OK)
 747                 return res;
 748
 749         /* Copy the data into the page buffer*/
 750         for (int i = 0; i < 256; i += 8) {
 751                 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
 752                 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
 753                 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
 754                 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
 755
 756                 /* Data is loaded 2x 32 bit words at a time */
 757                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
 758                 if (res != ERROR_OK)
 759                         return res;
 760
 761                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
 762                 if (res != ERROR_OK)
 763                         return res;
 764
 765                 /* Check for an error */
 766                 res = xmc4xxx_get_flash_status(bank, &status);
 767                 if (res != ERROR_OK)
 768                         return res;
 769
 770                 if (status & FSR_SQER_MASK) {
 771                         LOG_ERROR("Error loading page buffer");
 772                         return ERROR_FAIL;
 773                 }
 774         }
 775
 776         /* The page buffer is now full, time to commit it to flash */
 777
 778         res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
 779         if (res != ERROR_OK) {
 780                 LOG_ERROR("Unable to enter write command sequence");
 781                 return res;
 782         }
 783
 784         /* Read the flash status register */
 785         res = xmc4xxx_get_flash_status(bank, &status);
 786         if (res != ERROR_OK)
 787                 return res;
 788
 789         /* Check for a sequence error */
 790         if (status & FSR_SQER_MASK) {
 791                 LOG_ERROR("Error with flash write sequence");
 792                 return ERROR_FAIL;
 793         }
 794
 795         /* Make sure a flash write was triggered */
 796         if (!(status & FSR_PROG_MASK)) {
 797                 LOG_ERROR("Failed to write flash page");
 798                 return ERROR_FAIL;
 799         }
 800
 801         /* Wait for the write operation to end */
 802         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 803         if (res != ERROR_OK)
 804                 return res;
 805
 806         /* TODO: Verify that page was written without error */
 807         return res;
 808 }
 809
 810 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
 811                          uint32_t offset, uint32_t count)
 812 {
 813         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 814         int res = ERROR_OK;
 815
 816         if (bank->target->state != TARGET_HALTED) {
 817                 LOG_ERROR("Unable to erase, target is not halted");
 818                 return ERROR_TARGET_NOT_HALTED;
 819         }
 820
 821         if (!fb->probed) {
 822                 res = xmc4xxx_probe(bank);
 823                 if (res != ERROR_OK)
 824                         return res;
 825         }
 826
 827         /* Make sure we won't run off the end of the flash bank */
 828         if ((offset + count) > (bank->size)) {
 829                 LOG_ERROR("Attempting to write past the end of flash");
 830                 return ERROR_FAIL;
 831         }
 832
 833
 834         /* Attempt to write the passed in buffer to flash */
 835         /* Pages are written 256 bytes at a time, we need to handle
 836          * scenarios where padding is required at the beginning and
 837          * end of a page */
 838         while (count) {
 839                 /* page working area */
 840                 uint8_t tmp_buf[256] = {0};
 841
 842                 /* Amount of data we'll be writing to this page */
 843                 int remaining;
 844                 int end_pad;
 845
 846                 remaining = MIN(count, sizeof(tmp_buf));
 847                 end_pad   = sizeof(tmp_buf) - remaining;
 848
 849                 /* Make sure we're starting on a page boundary */
 850                 int start_pad = offset % 256;
 851                 if (start_pad) {
 852                         LOG_INFO("Write does not start on a 256 byte boundary. "
 853                                  "Padding by %d bytes", start_pad);
 854                         memset(tmp_buf, 0xff, start_pad);
 855                         /* Subtract the amount of start offset from
 856                          * the amount of data we'll need to write */
 857                         remaining -= start_pad;
 858                 }
 859
 860                 /* Remove the amount we'll be writing from the total count */
 861                 count -= remaining;
 862
 863                 /* Now copy in the remaining data */
 864                 memcpy(&tmp_buf[start_pad], buffer, remaining);
 865
 866                 if (end_pad) {
 867                         LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
 868                                  bank->base + offset, end_pad);
 869                         memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
 870                 }
 871
 872                 /* Now commit this page to flash, if there was start
 873                  * padding, we should subtract that from the target offset */
 874                 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
 875                 if (res != ERROR_OK) {
 876                         LOG_ERROR("Unable to write flash page");
 877                         goto abort_write_and_exit;
 878                 }
 879
 880                 /* Advance the buffer pointer */
 881                 buffer += remaining;
 882
 883                 /* Advance the offset */
 884                 offset += remaining;
 885         }
 886
 887 abort_write_and_exit:
 888         xmc4xxx_clear_flash_status(bank);
 889         return res;
 890
 891 }
 892
 893 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
 894 {
 895         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 896         uint32_t scu_idcode;
 897
 898         if (bank->target->state != TARGET_HALTED) {
 899                 LOG_WARNING("Cannot communicate... target not halted.");
 900                 return ERROR_TARGET_NOT_HALTED;
 901         }
 902
 903         /* The SCU registers contain the ID of the chip */
 904         int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
 905         if (res != ERROR_OK) {
 906                 LOG_ERROR("Cannot read device identification register.");
 907                 return res;
 908         }
 909
 910         uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
 911         uint16_t rev_id = scu_idcode & 0xf;
 912         const char *dev_str;
 913         const char *rev_str = NULL;
 914
 915         switch (dev_id) {
 916         case 0x100:
 917                 dev_str = "XMC4100";
 918
 919                 switch (rev_id) {
 920                 case 0x1:
 921                         rev_str = "AA";
 922                         break;
 923                 case 0x2:
 924                         rev_str = "AB";
 925                         break;
 926                 }
 927                 break;
 928         case 0x200:
 929                 dev_str = "XMC4200";
 930
 931                 switch (rev_id) {
 932                 case 0x1:
 933                         rev_str = "AA";
 934                         break;
 935                 case 0x2:
 936                         rev_str = "AB";
 937                         break;
 938                 }
 939                 break;
 940         case 0x400:
 941                 dev_str = "XMC4400";
 942
 943                 switch (rev_id) {
 944                 case 0x1:
 945                         rev_str = "AA";
 946                         break;
 947                 case 0x2:
 948                         rev_str = "AB";
 949                         break;
 950                 }
 951                 break;
 952         case 0x500:
 953                 dev_str = "XMC4500";
 954
 955                 switch (rev_id) {
 956                 case 0x2:
 957                         rev_str = "AA";
 958                         break;
 959                 case 0x3:
 960                         rev_str = "AB";
 961                         break;
 962                 case 0x4:
 963                         rev_str = "AC";
 964                         break;
 965                 }
 966                 break;
 967
 968         default:
 969                 snprintf(buf, buf_size,
 970                          "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
 971                          scu_idcode);
 972                 return ERROR_OK;
 973         }
 974
 975         /* String to declare protection data held in the private driver */
 976         char prot_str[512] = {0};
 977         if (fb->read_protected)
 978                 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
 979
 980         bool otp_enabled = false;
 981         for (int i = 0; i < bank->num_sectors; i++)
 982                 if (fb->write_prot_otp[i])
 983                         otp_enabled = true;
 984
 985         /* If OTP Write protection is enabled (User 2), list each
 986          * sector that has it enabled */
 987         char otp_str[8];
 988         if (otp_enabled) {
 989                 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
 990                 for (int i = 0; i < bank->num_sectors; i++) {
 991                         if (fb->write_prot_otp[i]) {
 992                                 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
 993                                 strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
 994                         }
 995                 }
 996         }
 997
 998         if (rev_str != NULL)
 999                 snprintf(buf, buf_size, "%s - Rev: %s%s",
1000                          dev_str, rev_str, prot_str);
1001         else
1002                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
1003                          dev_str, rev_id, prot_str);
1004
1005         return ERROR_OK;
1006 }
1007
1008 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
1009 {
1010         struct xmc4xxx_flash_bank *fb;
1011         int res = ERROR_OK;
1012         uint32_t status = 0;
1013
1014         struct xmc4xxx_command_seq temp_unprot_seq[6] = {
1015                 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
1016                 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
1017                 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
1018                 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
1019                 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
1020                 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
1021         };
1022
1023         if (user_level < 0 || user_level > 2) {
1024                 LOG_ERROR("Invalid user level, must be 0-2");
1025                 return ERROR_FAIL;
1026         }
1027
1028         fb = bank->driver_priv;
1029
1030         /* Fill in the user level and passwords */
1031         temp_unprot_seq[2].magic = user_level;
1032         temp_unprot_seq[3].magic = fb->pw1;
1033         temp_unprot_seq[4].magic = fb->pw2;
1034
1035         res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
1036                                              ARRAY_SIZE(temp_unprot_seq));
1037         if (res != ERROR_OK) {
1038                 LOG_ERROR("Unable to write temp unprotect sequence");
1039                 return res;
1040         }
1041
1042         res = xmc4xxx_get_flash_status(bank, &status);
1043         if (res != ERROR_OK)
1044                 return res;
1045
1046         if (status & FSR_WPRODIS0) {
1047                 LOG_INFO("Flash is temporarily unprotected");
1048         } else {
1049                 LOG_INFO("Unable to disable flash protection");
1050                 res = ERROR_FAIL;
1051         }
1052
1053
1054         return res;
1055 }
1056
1057 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
1058 {
1059         uint32_t addr;
1060         int res;
1061
1062         if ((level < 0) || (level > 1)) {
1063                 LOG_ERROR("Invalid user level. Must be 0-1");
1064                 return ERROR_FAIL;
1065         }
1066
1067         switch (level) {
1068         case 0:
1069                 addr = UCB0_BASE;
1070                 break;
1071         case 1:
1072                 addr = UCB1_BASE;
1073                 break;
1074         }
1075
1076         res = xmc4xxx_erase_sector(bank, addr, true);
1077
1078         if (res != ERROR_OK)
1079                 LOG_ERROR("Error erasing user configuration block");
1080
1081         return res;
1082 }
1083
1084 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1085 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1086                                  int first, int last)
1087 {
1088         /* User configuration block buffers */
1089         uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1090         uint32_t ucb_base = 0;
1091         uint32_t procon = 0;
1092         int res = ERROR_OK;
1093         uint32_t status = 0;
1094         bool proin = false;
1095
1096         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1097
1098         /* Read protect only works for user 0, make sure we don't try
1099          * to do something silly */
1100         if (level != 0 && read_protect) {
1101                 LOG_ERROR("Read protection is for user level 0 only!");
1102                 return ERROR_FAIL;
1103         }
1104
1105         /* Check to see if protection is already installed for the
1106          * specified user level.  If it is, the user configuration
1107          * block will need to be erased before we can continue */
1108
1109         /* Grab the flash status register*/
1110         res = xmc4xxx_get_flash_status(bank, &status);
1111         if (res != ERROR_OK)
1112                 return res;
1113
1114         switch (level) {
1115         case 0:
1116                 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1117                         proin = true;
1118                 break;
1119         case 1:
1120                 if (status & FSR_WPROIN1_MASK)
1121                         proin = true;
1122                 break;
1123         case 2:
1124                 if (status & FSR_WPROIN2_MASK)
1125                         proin = true;
1126                 break;
1127         }
1128
1129         if (proin) {
1130                 LOG_ERROR("Flash protection is installed for user %d"
1131                           " and must be removed before continuing", level);
1132                 return ERROR_FAIL;
1133         }
1134
1135         /* If this device has 12 flash sectors, protection for
1136          * sectors 10 & 11 are handled jointly. If we are trying to
1137          * write all sectors, we should decrement
1138          * last to ensure we don't write to a register bit that
1139          * doesn't exist*/
1140         if ((bank->num_sectors == 12) && (last == 12))
1141                 last--;
1142
1143         /*  We need to fill out the procon register representation
1144          *   that we will be writing to the device */
1145         for (int i = first; i <= last; i++)
1146                 procon |= 1 << i;
1147
1148         /* If read protection is requested, set the appropriate bit
1149          * (we checked that this is allowed above) */
1150         if (read_protect)
1151                 procon |= PROCON_RPRO_MASK;
1152
1153         LOG_DEBUG("Setting flash protection with procon:");
1154         LOG_DEBUG("PROCON: %"PRIx32, procon);
1155
1156         /* First we need to copy in the procon register to the buffer
1157          * we're going to attempt to write.  This is written twice */
1158         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1159         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1160
1161         /* Now we must copy in both flash passwords.  As with the
1162          * procon data, this must be written twice (4 total words
1163          * worth of data) */
1164         target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1165         target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1166         target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1167         target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1168
1169         /* Finally, (if requested) we copy in the confirmation
1170          * code so that the protection is permanent and will
1171          * require a password to undo. */
1172         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1173         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1174
1175         /* Now that the data is copied into place, we must write
1176          * these pages into flash */
1177
1178         /* The user configuration block base depends on what level of
1179          * protection we're trying to install, select the proper one */
1180         switch (level) {
1181         case 0:
1182                 ucb_base = UCB0_BASE;
1183                 break;
1184         case 1:
1185                 ucb_base = UCB1_BASE;
1186                 break;
1187         case 2:
1188                 ucb_base = UCB2_BASE;
1189                 break;
1190         }
1191
1192         /* Write the user config pages */
1193         res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1194         if (res != ERROR_OK) {
1195                 LOG_ERROR("Error writing user configuration block 0");
1196                 return res;
1197         }
1198
1199         return ERROR_OK;
1200 }
1201
1202 static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
1203 {
1204         int ret;
1205         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1206
1207         /* Check for flash passwords */
1208         if (!fb->pw_set) {
1209                 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1210                 return ERROR_FAIL;
1211         }
1212
1213         /* We want to clear flash protection temporarily*/
1214         if (set == 0) {
1215                 LOG_WARNING("Flash protection will be temporarily disabled"
1216                             " for all pages (User 0 only)!");
1217                 ret = xmc4xxx_temp_unprotect(bank, 0);
1218                 return ret;
1219         }
1220
1221         /* Install write protection for user 0 on the specified pages */
1222         ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1223
1224         return ret;
1225 }
1226
1227 static int xmc4xxx_protect_check(struct flash_bank *bank)
1228 {
1229         int ret;
1230         uint32_t protection[3] = {0};
1231         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1232
1233         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1234         if (ret != ERROR_OK) {
1235                 LOG_ERROR("Unable to read flash User0 protection register");
1236                 return ret;
1237         }
1238
1239         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1240         if (ret != ERROR_OK) {
1241                 LOG_ERROR("Unable to read flash User1 protection register");
1242                 return ret;
1243         }
1244
1245         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1246         if (ret != ERROR_OK) {
1247                 LOG_ERROR("Unable to read flash User2 protection register");
1248                 return ret;
1249         }
1250
1251         int sectors = bank->num_sectors;
1252
1253         /* On devices with 12 sectors, sectors 10 & 11 are ptected
1254          * together instead of individually */
1255         if (sectors == 12)
1256                 sectors--;
1257
1258         /* Clear the protection status */
1259         for (int i = 0; i < bank->num_sectors; i++) {
1260                 bank->sectors[i].is_protected = 0;
1261                 fb->write_prot_otp[i] = false;
1262         }
1263         fb->read_protected = false;
1264
1265         /* The xmc4xxx series supports 3 levels of user protection
1266          * (User0, User1 (low priority), and User 2(OTP), we need to
1267          * check all 3 */
1268         for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1269
1270                 /* Check for write protection on every available
1271                 *  sector */
1272                 for (int j = 0; j < sectors; j++) {
1273                         int set = (protection[i] & (1 << j)) ? 1 : 0;
1274                         bank->sectors[j].is_protected |= set;
1275
1276                         /* Handle sector 11 */
1277                         if (j == 10)
1278                                 bank->sectors[j + 1].is_protected |= set;
1279
1280                         /* User 2 indicates this protection is
1281                          * permanent, make note in the private driver structure */
1282                         if (i == 2 && set) {
1283                                 fb->write_prot_otp[j] = true;
1284
1285                                 /* Handle sector 11 */
1286                                 if (j == 10)
1287                                         fb->write_prot_otp[j + 1] = true;
1288                         }
1289
1290                 }
1291         }
1292
1293         /* XMC4xxx also supports read proptection, make a note
1294          * in the private driver structure */
1295         if (protection[0] & PROCON_RPRO_MASK)
1296                 fb->read_protected = true;
1297
1298         return ERROR_OK;
1299 }
1300
1301 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1302 {
1303         bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1304
1305         if (!bank->driver_priv)
1306                 return ERROR_FLASH_OPERATION_FAILED;
1307
1308         (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1309
1310         return ERROR_OK;
1311 }
1312
1313 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1314 {
1315         int res;
1316         struct flash_bank *bank;
1317
1318         if (CMD_ARGC < 3)
1319                 return ERROR_COMMAND_SYNTAX_ERROR;
1320
1321         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1322         if (res != ERROR_OK)
1323                 return res;
1324
1325         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1326
1327         errno = 0;
1328
1329         /* We skip over the flash bank */
1330         fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1331
1332         if (errno)
1333                 return ERROR_COMMAND_SYNTAX_ERROR;
1334
1335         fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1336
1337         if (errno)
1338                 return ERROR_COMMAND_SYNTAX_ERROR;
1339
1340         fb->pw_set = true;
1341
1342         command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
1343         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
1344         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
1345         return ERROR_OK;
1346 }
1347
1348 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1349 {
1350         struct flash_bank *bank;
1351         int res;
1352         int32_t level;
1353
1354         if (CMD_ARGC < 2)
1355                 return ERROR_COMMAND_SYNTAX_ERROR;
1356
1357         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1358         if (res != ERROR_OK)
1359                 return res;
1360
1361         COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1362
1363         res = xmc4xxx_flash_unprotect(bank, level);
1364
1365         return res;
1366 }
1367
1368 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1369         {
1370                 .name = "flash_password",
1371                 .handler = xmc4xxx_handle_flash_password_command,
1372                 .mode = COMMAND_EXEC,
1373                 .usage = "bank_id password1 password2",
1374                 .help = "Set the flash passwords used for protect operations. "
1375                 "Passwords should be in standard hex form (0x00000000). "
1376                 "(You must call this before any other protect commands) "
1377                 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1378                 "Please use protection carefully!",
1379         },
1380         {
1381                 .name = "flash_unprotect",
1382                 .handler = xmc4xxx_handle_flash_unprotect_command,
1383                 .mode = COMMAND_EXEC,
1384                 .usage = "bank_id user_level[0-1]",
1385                 .help = "Permanently Removes flash protection (read and write) "
1386                 "for the specified user level",
1387         },      COMMAND_REGISTRATION_DONE
1388 };
1389
1390 static const struct command_registration xmc4xxx_command_handlers[] = {
1391         {
1392                 .name = "xmc4xxx",
1393                 .mode = COMMAND_ANY,
1394                 .help = "xmc4xxx flash command group",
1395                 .usage = "",
1396                 .chain = xmc4xxx_exec_command_handlers,
1397         },
1398         COMMAND_REGISTRATION_DONE
1399 };
1400
1401 struct flash_driver xmc4xxx_flash = {
1402         .name = "xmc4xxx",
1403         .commands = xmc4xxx_command_handlers,
1404         .flash_bank_command = xmc4xxx_flash_bank_command,
1405         .erase = xmc4xxx_erase,
1406         .write = xmc4xxx_write,
1407         .read = default_flash_read,
1408         .probe = xmc4xxx_probe,
1409         .auto_probe = xmc4xxx_probe,
1410         .erase_check = xmc4xxx_flash_blank_check,
1411         .info = xmc4xxx_get_info_command,
1412         .protect_check = xmc4xxx_protect_check,
1413         .protect = xmc4xxx_protect,
1414 };