git.sur5r.net Git - openocd/blob - src/flash/nor/xmc4xxx.c

   1 /**************************************************************************
   2 *   Copyright (C) 2015 Jeff Ciesielski <jeffciesielski@gmail.com>         *
   3 *                                                                         *
   4 *   This program is free software; you can redistribute it and/or modify  *
   5 *   it under the terms of the GNU General Public License as published by  *
   6 *   the Free Software Foundation; either version 2 of the License, or     *
   7 *   (at your option) any later version.                                   *
   8 *                                                                         *
   9 *   This program is distributed in the hope that it will be useful,       *
  10 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12 *   GNU General Public License for more details.                          *
  13 *                                                                         *
  14 ***************************************************************************/
  15
  16 #ifdef HAVE_CONFIG_H
  17 #include "config.h"
  18 #endif
  19
  20 #include "imp.h"
  21 #include <helper/binarybuffer.h>
  22 #include <target/algorithm.h>
  23 #include <target/armv7m.h>
  24
  25 /* Maximum number of sectors */
  26 #define MAX_XMC_SECTORS 12
  27
  28 /* System control unit registers */
  29 #define SCU_REG_BASE 0x50004000
  30
  31 #define SCU_ID_CHIP 0x04
  32
  33 /* Base of the non-cached flash memory */
  34 #define PFLASH_BASE     0x0C000000
  35
  36 /* User configuration block offsets */
  37 #define UCB0_BASE       0x00000000
  38 #define UCB1_BASE       0x00000400
  39 #define UCB2_BASE       0x00000800
  40
  41 /* Flash register base */
  42 #define FLASH_REG_BASE 0x58000000
  43
  44 /* PMU ID Registers */
  45 #define FLASH_REG_PMU_ID        (FLASH_REG_BASE | 0x0508)
  46
  47 /* PMU Fields */
  48 #define PMU_MOD_REV_MASK        0xFF
  49 #define PMU_MOD_TYPE_MASK       0xFF00
  50 #define PMU_MOD_NO_MASK         0xFFFF0000
  51
  52 /* Prefetch Config */
  53 #define FLASH_REG_PREF_PCON     (FLASH_REG_BASE | 0x4000)
  54
  55 /* Prefetch Fields */
  56 #define PCON_IBYP       (1 << 0)
  57 #define PCON_IINV       (1 << 1)
  58
  59 /* Flash ID Register */
  60 #define FLASH_REG_FLASH0_ID     (FLASH_REG_BASE | 0x2008)
  61
  62 /* Flash Status Register */
  63 #define FLASH_REG_FLASH0_FSR    (FLASH_REG_BASE | 0x2010)
  64
  65 #define FSR_PBUSY       (0)
  66 #define FSR_FABUSY      (1)
  67 #define FSR_PROG        (4)
  68 #define FSR_ERASE       (5)
  69 #define FSR_PFPAGE      (6)
  70 #define FSR_PFOPER      (8)
  71 #define FSR_SQER        (10)
  72 #define FSR_PROER       (11)
  73 #define FSR_PFSBER      (12)
  74 #define FSR_PFDBER      (14)
  75 #define FSR_PROIN       (16)
  76 #define FSR_RPROIN      (18)
  77 #define FSR_RPRODIS     (19)
  78 #define FSR_WPROIN0     (21)
  79 #define FSR_WPROIN1     (22)
  80 #define FSR_WPROIN2     (23)
  81 #define FSR_WPRODIS0    (25)
  82 #define FSR_WPRODIS1    (26)
  83 #define FSR_SLM         (28)
  84 #define FSR_VER         (31)
  85
  86 #define FSR_PBUSY_MASK          (0x01 << FSR_PBUSY)
  87 #define FSR_FABUSY_MASK         (0x01 << FSR_FABUSY)
  88 #define FSR_PROG_MASK           (0x01 << FSR_PROG)
  89 #define FSR_ERASE_MASK          (0x01 << FSR_ERASE)
  90 #define FSR_PFPAGE_MASK         (0x01 << FSR_PFPAGE)
  91 #define FSR_PFOPER_MASK         (0x01 << FSR_PFOPER)
  92 #define FSR_SQER_MASK           (0x01 << FSR_SQER)
  93 #define FSR_PROER_MASK          (0x01 << FSR_PROER)
  94 #define FSR_PFSBER_MASK         (0x01 << FSR_PFSBER)
  95 #define FSR_PFDBER_MASK         (0x01 << FSR_PFDBER)
  96 #define FSR_PROIN_MASK          (0x01 << FSR_PROIN)
  97 #define FSR_RPROIN_MASK         (0x01 << FSR_RPROIN)
  98 #define FSR_RPRODIS_MASK        (0x01 << FSR_RPRODIS)
  99 #define FSR_WPROIN0_MASK        (0x01 << FSR_WPROIN0)
 100 #define FSR_WPROIN1_MASK        (0x01 << FSR_WPROIN1)
 101 #define FSR_WPROIN2_MASK        (0x01 << FSR_WPROIN2)
 102 #define FSR_WPRODIS0_MASK       (0x01 << FSR_WPRODIS0)
 103 #define FSR_WPRODIS1_MASK       (0x01 << FSR_WPRODIS1)
 104 #define FSR_SLM_MASK            (0x01 << FSR_SLM)
 105 #define FSR_VER_MASK            (0x01 << FSR_VER)
 106
 107 /* Flash Config Register */
 108 #define FLASH_REG_FLASH0_FCON   (FLASH_REG_BASE | 0x2014)
 109
 110 #define FCON_WSPFLASH           (0)
 111 #define FCON_WSECPF             (4)
 112 #define FCON_IDLE               (13)
 113 #define FCON_ESLDIS             (14)
 114 #define FCON_SLEEP              (15)
 115 #define FCON_RPA                (16)
 116 #define FCON_DCF                (17)
 117 #define FCON_DDF                (18)
 118 #define FCON_VOPERM             (24)
 119 #define FCON_SQERM              (25)
 120 #define FCON_PROERM             (26)
 121 #define FCON_PFSBERM            (27)
 122 #define FCON_PFDBERM            (29)
 123 #define FCON_EOBM               (31)
 124
 125 #define FCON_WSPFLASH_MASK      (0x0f << FCON_WSPFLASH)
 126 #define FCON_WSECPF_MASK        (0x01 << FCON_WSECPF)
 127 #define FCON_IDLE_MASK          (0x01 << FCON_IDLE)
 128 #define FCON_ESLDIS_MASK        (0x01 << FCON_ESLDIS)
 129 #define FCON_SLEEP_MASK         (0x01 << FCON_SLEEP)
 130 #define FCON_RPA_MASK           (0x01 << FCON_RPA)
 131 #define FCON_DCF_MASK           (0x01 << FCON_DCF)
 132 #define FCON_DDF_MASK           (0x01 << FCON_DDF)
 133 #define FCON_VOPERM_MASK        (0x01 << FCON_VOPERM)
 134 #define FCON_SQERM_MASK         (0x01 << FCON_SQERM)
 135 #define FCON_PROERM_MASK        (0x01 << FCON_PROERM)
 136 #define FCON_PFSBERM_MASK       (0x01 << FCON_PFSBERM)
 137 #define FCON_PFDBERM_MASK       (0x01 << FCON_PFDBERM)
 138 #define FCON_EOBM_MASK          (0x01 << FCON_EOBM)
 139
 140 /* Flash Margin Control Register */
 141 #define FLASH_REG_FLASH0_MARP   (FLASH_REG_BASE | 0x2018)
 142
 143 #define MARP_MARGIN             (0)
 144 #define MARP_TRAPDIS            (15)
 145
 146 #define MARP_MARGIN_MASK        (0x0f << MARP_MARGIN)
 147 #define MARP_TRAPDIS_MASK       (0x01 << MARP_TRAPDIS)
 148
 149 /* Flash Protection Registers */
 150 #define FLASH_REG_FLASH0_PROCON0        (FLASH_REG_BASE | 0x2020)
 151 #define FLASH_REG_FLASH0_PROCON1        (FLASH_REG_BASE | 0x2024)
 152 #define FLASH_REG_FLASH0_PROCON2        (FLASH_REG_BASE | 0x2028)
 153
 154 #define PROCON_S0L             (0)
 155 #define PROCON_S1L             (1)
 156 #define PROCON_S2L             (2)
 157 #define PROCON_S3L             (3)
 158 #define PROCON_S4L             (4)
 159 #define PROCON_S5L             (5)
 160 #define PROCON_S6L             (6)
 161 #define PROCON_S7L             (7)
 162 #define PROCON_S8L             (8)
 163 #define PROCON_S9L             (9)
 164 #define PROCON_S10_S11L        (10)
 165 #define PROCON_RPRO            (15)
 166
 167 #define PROCON_S0L_MASK        (0x01 << PROCON_S0L)
 168 #define PROCON_S1L_MASK        (0x01 << PROCON_S1L)
 169 #define PROCON_S2L_MASK        (0x01 << PROCON_S2L)
 170 #define PROCON_S3L_MASK        (0x01 << PROCON_S3L)
 171 #define PROCON_S4L_MASK        (0x01 << PROCON_S4L)
 172 #define PROCON_S5L_MASK        (0x01 << PROCON_S5L)
 173 #define PROCON_S6L_MASK        (0x01 << PROCON_S6L)
 174 #define PROCON_S7L_MASK        (0x01 << PROCON_S7L)
 175 #define PROCON_S8L_MASK        (0x01 << PROCON_S8L)
 176 #define PROCON_S9L_MASK        (0x01 << PROCON_S9L)
 177 #define PROCON_S10_S11L_MASK   (0x01 << PROCON_S10_S11L)
 178 #define PROCON_RPRO_MASK       (0x01 << PROCON_RPRO)
 179
 180 #define FLASH_PROTECT_CONFIRMATION_CODE 0x8AFE15C3
 181
 182 /* Flash controller configuration values */
 183 #define FLASH_ID_XMC4500        0xA2
 184 #define FLASH_ID_XMC4700_4800   0x92
 185 #define FLASH_ID_XMC4100_4200   0x9C
 186 #define FLASH_ID_XMC4400        0x9F
 187
 188 /* Timeouts */
 189 #define FLASH_OP_TIMEOUT 5000
 190
 191 /* Flash commands (write/erase/protect) are performed using special
 192  * command sequences that are written to magic addresses in the flash controller */
 193 /* Command sequence addresses.  See reference manual, section 8: Flash Command Sequences */
 194 #define FLASH_CMD_ERASE_1 0x0C005554
 195 #define FLASH_CMD_ERASE_2 0x0C00AAA8
 196 #define FLASH_CMD_ERASE_3 FLASH_CMD_ERASE_1
 197 #define FLASH_CMD_ERASE_4 FLASH_CMD_ERASE_1
 198 #define FLASH_CMD_ERASE_5 FLASH_CMD_ERASE_2
 199 /* ERASE_6 is the sector base address */
 200
 201 #define FLASH_CMD_CLEAR_STATUS FLASH_CMD_ERASE_1
 202
 203 #define FLASH_CMD_ENTER_PAGEMODE FLASH_CMD_ERASE_1
 204
 205 #define FLASH_CMD_LOAD_PAGE_1 0x0C0055F0
 206 #define FLASH_CMD_LOAD_PAGE_2 0x0C0055F4
 207
 208 #define FLASH_CMD_WRITE_PAGE_1 FLASH_CMD_ERASE_1
 209 #define FLASH_CMD_WRITE_PAGE_2 FLASH_CMD_ERASE_2
 210 #define FLASH_CMD_WRITE_PAGE_3 FLASH_CMD_ERASE_1
 211 /* WRITE_PAGE_4 is the page base address */
 212
 213 #define FLASH_CMD_TEMP_UNPROT_1 FLASH_CMD_ERASE_1
 214 #define FLASH_CMD_TEMP_UNPROT_2 FLASH_CMD_ERASE_2
 215 #define FLASH_CMD_TEMP_UNPROT_3 0x0C00553C
 216 #define FLASH_CMD_TEMP_UNPROT_4 FLASH_CMD_ERASE_2
 217 #define FLASH_CMD_TEMP_UNPROT_5 FLASH_CMD_ERASE_2
 218 #define FLASH_CMD_TEMP_UNPROT_6 0x0C005558
 219
 220 struct xmc4xxx_flash_bank {
 221         bool probed;
 222
 223         /* We need the flash controller ID to choose the sector layout */
 224         uint32_t fcon_id;
 225
 226         /* Passwords used for protection operations */
 227         uint32_t pw1;
 228         uint32_t pw2;
 229         bool pw_set;
 230
 231         /* Protection flags */
 232         bool read_protected;
 233
 234         bool write_prot_otp[MAX_XMC_SECTORS];
 235 };
 236
 237 struct xmc4xxx_command_seq {
 238         uint32_t address;
 239         uint32_t magic;
 240 };
 241
 242 /* Sector capacities.  See section 8 of xmc4x00_rm */
 243 static const unsigned int sector_capacity_8[8] = {
 244         16, 16, 16, 16, 16, 16, 16, 128
 245 };
 246
 247 static const unsigned int sector_capacity_9[9] = {
 248         16, 16, 16, 16, 16, 16, 16, 128, 256
 249 };
 250
 251 static const unsigned int sector_capacity_12[12] = {
 252         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256
 253 };
 254
 255 static const unsigned int sector_capacity_16[16] = {
 256         16, 16, 16, 16, 16, 16, 16, 16, 128, 256, 256, 256, 256, 256, 256, 256
 257 };
 258
 259 static int xmc4xxx_write_command_sequence(struct flash_bank *bank,
 260                                          struct xmc4xxx_command_seq *seq,
 261                                          int seq_len)
 262 {
 263         int res = ERROR_OK;
 264
 265         for (int i = 0; i < seq_len; i++) {
 266                 res = target_write_u32(bank->target, seq[i].address,
 267                                        seq[i].magic);
 268                 if (res != ERROR_OK)
 269                         return res;
 270         }
 271
 272         return ERROR_OK;
 273 }
 274
 275 static int xmc4xxx_load_bank_layout(struct flash_bank *bank)
 276 {
 277         const unsigned int *capacity = NULL;
 278
 279         /* At this point, we know which flash controller ID we're
 280          * talking to and simply need to fill out the bank structure accordingly */
 281         LOG_DEBUG("%d sectors", bank->num_sectors);
 282
 283         switch (bank->num_sectors) {
 284         case 8:
 285                 capacity = sector_capacity_8;
 286                 break;
 287         case 9:
 288                 capacity = sector_capacity_9;
 289                 break;
 290         case 12:
 291                 capacity = sector_capacity_12;
 292                 break;
 293         case 16:
 294                 capacity = sector_capacity_16;
 295                 break;
 296         default:
 297                 LOG_ERROR("Unexpected number of sectors, %d\n",
 298                           bank->num_sectors);
 299                 return ERROR_FAIL;
 300         }
 301
 302         /* This looks like a bank that we understand, now we know the
 303          * corresponding sector capacities and we can add those up into the
 304          * bank size. */
 305         uint32_t total_offset = 0;
 306         bank->sectors = calloc(bank->num_sectors,
 307                                sizeof(struct flash_sector));
 308         for (int i = 0; i < bank->num_sectors; i++) {
 309                 bank->sectors[i].size = capacity[i] * 1024;
 310                 bank->sectors[i].offset = total_offset;
 311                 bank->sectors[i].is_erased = -1;
 312                 bank->sectors[i].is_protected = -1;
 313
 314                 bank->size += bank->sectors[i].size;
 315                 LOG_DEBUG("\t%d: %uk", i, capacity[i]);
 316                 total_offset += bank->sectors[i].size;
 317         }
 318
 319         /* This part doesn't follow the typical standard of 0xff
 320          * being the default padding value.*/
 321         bank->default_padded_value = 0x00;
 322
 323         return ERROR_OK;
 324 }
 325
 326 static int xmc4xxx_probe(struct flash_bank *bank)
 327 {
 328         int res;
 329         uint32_t devid, config;
 330         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 331         uint8_t flash_id;
 332
 333         if (fb->probed)
 334                 return ERROR_OK;
 335
 336         /* It's not possible for the DAP to access the OTP locations needed for
 337          * probing the part info and Flash geometry so we require that the target
 338          * be halted before proceeding. */
 339         if (bank->target->state != TARGET_HALTED) {
 340                 LOG_WARNING("Cannot communicate... target not halted.");
 341                 return ERROR_TARGET_NOT_HALTED;
 342         }
 343
 344         /* The SCU registers contain the ID of the chip */
 345         res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &devid);
 346         if (res != ERROR_OK) {
 347                 LOG_ERROR("Cannot read device identification register.");
 348                 return res;
 349         }
 350
 351         /* Make sure this is a XMC4000 family device */
 352         if ((devid & 0xF0000) != 0x40000 && devid != 0) {
 353                 LOG_ERROR("Platform ID doesn't match XMC4xxx: 0x%08" PRIx32, devid);
 354                 return ERROR_FAIL;
 355         }
 356
 357         LOG_DEBUG("Found XMC4xxx with devid: 0x%08" PRIx32, devid);
 358
 359         /* Now sanity-check the Flash controller itself. */
 360         res = target_read_u32(bank->target, FLASH_REG_FLASH0_ID,
 361                         &config);
 362         if (res != ERROR_OK) {
 363                 LOG_ERROR("Cannot read Flash bank configuration.");
 364                 return res;
 365         }
 366         flash_id = (config & 0xff0000) >> 16;
 367
 368         /* The Flash configuration register is our only means of
 369          * determining the sector layout. We need to make sure that
 370          * we understand the type of controller we're dealing with */
 371         switch (flash_id) {
 372         case FLASH_ID_XMC4100_4200:
 373                 bank->num_sectors = 8;
 374                 LOG_DEBUG("XMC4xxx: XMC4100/4200 detected.");
 375                 break;
 376         case FLASH_ID_XMC4400:
 377                 bank->num_sectors = 9;
 378                 LOG_DEBUG("XMC4xxx: XMC4400 detected.");
 379                 break;
 380         case FLASH_ID_XMC4500:
 381                 bank->num_sectors = 12;
 382                 LOG_DEBUG("XMC4xxx: XMC4500 detected.");
 383                 break;
 384         case FLASH_ID_XMC4700_4800:
 385                 bank->num_sectors = 16;
 386                 LOG_DEBUG("XMC4xxx: XMC4700/4800 detected.");
 387                 break;
 388         default:
 389                 LOG_ERROR("XMC4xxx: Unexpected flash ID. got %02" PRIx8,
 390                           flash_id);
 391                 return ERROR_FAIL;
 392         }
 393
 394         /* Retrieve information about the particular bank we're probing and fill in
 395          * the bank structure accordingly. */
 396         res = xmc4xxx_load_bank_layout(bank);
 397         if (res == ERROR_OK) {
 398                 /* We're done */
 399                 fb->probed = true;
 400         } else {
 401                 LOG_ERROR("Unable to load bank information.");
 402                 return ERROR_FAIL;
 403         }
 404
 405         return ERROR_OK;
 406 }
 407
 408 static int xmc4xxx_get_sector_start_addr(struct flash_bank *bank,
 409                                          int sector, uint32_t *ret_addr)
 410 {
 411         /* Make sure we understand this sector */
 412         if (sector > bank->num_sectors)
 413                 return ERROR_FAIL;
 414
 415         *ret_addr = bank->base + bank->sectors[sector].offset;
 416
 417         return ERROR_OK;
 418
 419 }
 420
 421 static int xmc4xxx_clear_flash_status(struct flash_bank *bank)
 422 {
 423         int res;
 424         /* TODO: Do we need to check for sequence error? */
 425         LOG_INFO("Clearing flash status");
 426         res = target_write_u32(bank->target, FLASH_CMD_CLEAR_STATUS,
 427                                0xF5);
 428         if (res != ERROR_OK) {
 429                 LOG_ERROR("Unable to write erase command sequence");
 430                 return res;
 431         }
 432
 433         return ERROR_OK;
 434 }
 435
 436 static int xmc4xxx_get_flash_status(struct flash_bank *bank, uint32_t *status)
 437 {
 438         int res;
 439
 440         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, status);
 441
 442         if (res != ERROR_OK)
 443                 LOG_ERROR("Cannot read flash status register.");
 444
 445         return res;
 446 }
 447
 448 static int xmc4xxx_wait_status_busy(struct flash_bank *bank, int timeout)
 449 {
 450         int res;
 451         uint32_t status;
 452
 453         res = xmc4xxx_get_flash_status(bank, &status);
 454         if (res != ERROR_OK)
 455                 return res;
 456
 457         /* While the flash controller is busy, wait */
 458         while (status & FSR_PBUSY_MASK) {
 459                 res = xmc4xxx_get_flash_status(bank, &status);
 460                 if (res != ERROR_OK)
 461                         return res;
 462
 463                 if (timeout-- <= 0) {
 464                         LOG_ERROR("Timed out waiting for flash");
 465                         return ERROR_FAIL;
 466                 }
 467                 alive_sleep(1);
 468                 keep_alive();
 469         }
 470
 471         if (status & FSR_PROER_MASK) {
 472                 LOG_ERROR("XMC4xxx flash protected");
 473                 res = ERROR_FAIL;
 474         }
 475
 476         return res;
 477 }
 478
 479 static int xmc4xxx_erase_sector(struct flash_bank *bank, uint32_t address,
 480                                 bool user_config)
 481 {
 482         int res;
 483         uint32_t status;
 484
 485         /* See reference manual table 8.4: Command Sequences for Flash Control */
 486         struct xmc4xxx_command_seq erase_cmd_seq[6] = {
 487                 {FLASH_CMD_ERASE_1, 0xAA},
 488                 {FLASH_CMD_ERASE_2, 0x55},
 489                 {FLASH_CMD_ERASE_3, 0x80},
 490                 {FLASH_CMD_ERASE_4, 0xAA},
 491                 {FLASH_CMD_ERASE_5, 0x55},
 492                 {0xFF,              0xFF} /* Needs filled in */
 493         };
 494
 495         /* We need to fill in the base address of the sector we'll be
 496          * erasing, as well as the magic code that determines whether
 497          * this is a standard flash sector or a user configuration block */
 498
 499         erase_cmd_seq[5].address = address;
 500         if (user_config) {
 501                 /* Removing flash protection requires the addition of
 502                  * the base address */
 503                 erase_cmd_seq[5].address += bank->base;
 504                 erase_cmd_seq[5].magic = 0xC0;
 505         } else {
 506                 erase_cmd_seq[5].magic = 0x30;
 507         }
 508
 509         res = xmc4xxx_write_command_sequence(bank, erase_cmd_seq,
 510                                              ARRAY_SIZE(erase_cmd_seq));
 511         if (res != ERROR_OK)
 512                 return res;
 513
 514         /* Read the flash status register */
 515         res = target_read_u32(bank->target, FLASH_REG_FLASH0_FSR, &status);
 516         if (res != ERROR_OK) {
 517                 LOG_ERROR("Cannot read flash status register.");
 518                 return res;
 519         }
 520
 521         /* Check for a sequence error */
 522         if (status & FSR_SQER_MASK) {
 523                 LOG_ERROR("Error with flash erase sequence");
 524                 return ERROR_FAIL;
 525         }
 526
 527         /* Make sure a flash erase was triggered */
 528         if (!(status & FSR_ERASE_MASK)) {
 529                 LOG_ERROR("Flash failed to erase");
 530                 return ERROR_FAIL;
 531         }
 532
 533         /* Now we must wait for the erase operation to end */
 534         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 535
 536         return res;
 537 }
 538
 539 static int xmc4xxx_erase(struct flash_bank *bank, int first, int last)
 540 {
 541         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 542         int res;
 543
 544         if (bank->target->state != TARGET_HALTED) {
 545                 LOG_ERROR("Unable to erase, target is not halted");
 546                 return ERROR_TARGET_NOT_HALTED;
 547         }
 548
 549         if (!fb->probed) {
 550                 res = xmc4xxx_probe(bank);
 551                 if (res != ERROR_OK)
 552                         return res;
 553         }
 554
 555         uint32_t tmp_addr;
 556         /* Loop through the sectors and erase each one */
 557         for (int i = first; i <= last; i++) {
 558                 res = xmc4xxx_get_sector_start_addr(bank, i, &tmp_addr);
 559                 if (res != ERROR_OK) {
 560                         LOG_ERROR("Invalid sector %d", i);
 561                         return res;
 562                 }
 563
 564                 LOG_DEBUG("Erasing sector %d @ 0x%08"PRIx32, i, tmp_addr);
 565
 566                 res = xmc4xxx_erase_sector(bank, tmp_addr, false);
 567                 if (res != ERROR_OK) {
 568                         LOG_ERROR("Unable to write erase command sequence");
 569                         goto clear_status_and_exit;
 570                 }
 571
 572                 /* Now we must wait for the erase operation to end */
 573                 res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 574
 575                 if (res != ERROR_OK)
 576                         goto clear_status_and_exit;
 577
 578                 bank->sectors[i].is_erased = 1;
 579         }
 580
 581 clear_status_and_exit:
 582         res = xmc4xxx_clear_flash_status(bank);
 583         return res;
 584
 585 }
 586
 587 static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
 588 {
 589         int res;
 590         uint32_t status;
 591
 592         res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
 593         if (res != ERROR_OK) {
 594                 LOG_ERROR("Unable to write enter page mode command");
 595                 return ERROR_FAIL;
 596         }
 597
 598         res = xmc4xxx_get_flash_status(bank, &status);
 599
 600         if (res != ERROR_OK)
 601                 return res;
 602
 603         /* Make sure we're in page mode */
 604         if (!(status & FSR_PFPAGE_MASK)) {
 605                 LOG_ERROR("Unable to enter page mode");
 606                 return ERROR_FAIL;
 607         }
 608
 609         /* Make sure we didn't encounter a sequence error */
 610         if (status & FSR_SQER_MASK) {
 611                 LOG_ERROR("Sequence error while entering page mode");
 612                 return ERROR_FAIL;
 613         }
 614
 615         return res;
 616 }
 617
 618 /* The logical erase value of an xmc4xxx memory cell is 0x00,
 619  * therefore, we cannot use the built in flash blank check and must
 620  * implement our own */
 621
 622 /** Checks whether a memory region is zeroed. */
 623 int xmc4xxx_blank_check_memory(struct target *target,
 624         uint32_t address, uint32_t count, uint32_t *blank)
 625 {
 626         struct working_area *erase_check_algorithm;
 627         struct reg_param reg_params[3];
 628         struct armv7m_algorithm armv7m_info;
 629         int retval;
 630
 631         static const uint8_t erase_check_code[] = {
 632 #include "../../../contrib/loaders/erase_check/armv7m_0_erase_check.inc"
 633         };
 634
 635         /* make sure we have a working area */
 636         if (target_alloc_working_area(target, sizeof(erase_check_code),
 637                 &erase_check_algorithm) != ERROR_OK)
 638                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 639
 640         retval = target_write_buffer(target, erase_check_algorithm->address,
 641                         sizeof(erase_check_code), (uint8_t *)erase_check_code);
 642         if (retval != ERROR_OK)
 643                 return retval;
 644
 645         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 646         armv7m_info.core_mode = ARM_MODE_THREAD;
 647
 648         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 649         buf_set_u32(reg_params[0].value, 0, 32, address);
 650
 651         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 652         buf_set_u32(reg_params[1].value, 0, 32, count);
 653
 654         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
 655         buf_set_u32(reg_params[2].value, 0, 32, 0x00);
 656
 657         retval = target_run_algorithm(target,
 658                                       0,
 659                                       NULL,
 660                                       3,
 661                                       reg_params,
 662                                       erase_check_algorithm->address,
 663                                       erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
 664                                       10000,
 665                                       &armv7m_info);
 666
 667         if (retval == ERROR_OK)
 668                 *blank = buf_get_u32(reg_params[2].value, 0, 32);
 669
 670         destroy_reg_param(&reg_params[0]);
 671         destroy_reg_param(&reg_params[1]);
 672         destroy_reg_param(&reg_params[2]);
 673
 674         target_free_working_area(target, erase_check_algorithm);
 675
 676         return retval;
 677 }
 678
 679 static int xmc4xxx_flash_blank_check(struct flash_bank *bank)
 680 {
 681         struct target *target = bank->target;
 682         int i;
 683         int retval;
 684         uint32_t blank;
 685
 686         if (bank->target->state != TARGET_HALTED) {
 687                 LOG_ERROR("Target not halted");
 688                 return ERROR_TARGET_NOT_HALTED;
 689         }
 690
 691         for (i = 0; i < bank->num_sectors; i++) {
 692                 uint32_t address = bank->base + bank->sectors[i].offset;
 693                 uint32_t size = bank->sectors[i].size;
 694
 695                 LOG_DEBUG("Erase checking 0x%08"PRIx32, address);
 696                 retval = xmc4xxx_blank_check_memory(target, address, size, &blank);
 697
 698                 if (retval != ERROR_OK)
 699                         break;
 700
 701                 if (blank == 0x00)
 702                         bank->sectors[i].is_erased = 1;
 703                 else
 704                         bank->sectors[i].is_erased = 0;
 705         }
 706
 707         return ERROR_OK;
 708 }
 709
 710 static int xmc4xxx_write_page(struct flash_bank *bank, const uint8_t *pg_buf,
 711                               uint32_t offset, bool user_config)
 712 {
 713         int res;
 714         uint32_t status;
 715
 716         /* Base of the flash write command */
 717         struct xmc4xxx_command_seq write_cmd_seq[4] = {
 718                 {FLASH_CMD_WRITE_PAGE_1, 0xAA},
 719                 {FLASH_CMD_WRITE_PAGE_2, 0x55},
 720                 {FLASH_CMD_WRITE_PAGE_3, 0xFF}, /* Needs filled in */
 721                 {0xFF,                   0xFF}  /* Needs filled in */
 722         };
 723
 724         /* The command sequence differs depending on whether this is
 725          * being written to standard flash or the user configuration
 726          * area */
 727         if (user_config)
 728                 write_cmd_seq[2].magic = 0xC0;
 729         else
 730                 write_cmd_seq[2].magic = 0xA0;
 731
 732         /* Finally, we need to add the address that this page will be
 733          * written to */
 734         write_cmd_seq[3].address = bank->base + offset;
 735         write_cmd_seq[3].magic = 0xAA;
 736
 737
 738         /* Flash pages are written 256 bytes at a time.  For each 256
 739          * byte chunk, we need to:
 740          * 1. Enter page mode. This activates the flash write buffer
 741          * 2. Load the page buffer with data (2x 32 bit words at a time)
 742          * 3. Burn the page buffer into its intended location
 743          * If the starting offset is not on a 256 byte boundary, we
 744          * will need to pad the beginning of the write buffer
 745          * accordingly. Likewise, if the last page does not fill the
 746          * buffer, we should pad it to avoid leftover data from being
 747          * written to flash
 748          */
 749         res = xmc4xxx_enter_page_mode(bank);
 750         if (res != ERROR_OK)
 751                 return res;
 752
 753         /* Copy the data into the page buffer*/
 754         for (int i = 0; i < 256; i += 8) {
 755                 uint32_t w_lo = target_buffer_get_u32(bank->target, &pg_buf[i]);
 756                 uint32_t w_hi = target_buffer_get_u32(bank->target, &pg_buf[i + 4]);
 757                 LOG_DEBUG("WLO: %08"PRIx32, w_lo);
 758                 LOG_DEBUG("WHI: %08"PRIx32, w_hi);
 759
 760                 /* Data is loaded 2x 32 bit words at a time */
 761                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_1, w_lo);
 762                 if (res != ERROR_OK)
 763                         return res;
 764
 765                 res = target_write_u32(bank->target, FLASH_CMD_LOAD_PAGE_2, w_hi);
 766                 if (res != ERROR_OK)
 767                         return res;
 768
 769                 /* Check for an error */
 770                 res = xmc4xxx_get_flash_status(bank, &status);
 771                 if (res != ERROR_OK)
 772                         return res;
 773
 774                 if (status & FSR_SQER_MASK) {
 775                         LOG_ERROR("Error loading page buffer");
 776                         return ERROR_FAIL;
 777                 }
 778         }
 779
 780         /* The page buffer is now full, time to commit it to flash */
 781
 782         res = xmc4xxx_write_command_sequence(bank, write_cmd_seq, ARRAY_SIZE(write_cmd_seq));
 783         if (res != ERROR_OK) {
 784                 LOG_ERROR("Unable to enter write command sequence");
 785                 return res;
 786         }
 787
 788         /* Read the flash status register */
 789         res = xmc4xxx_get_flash_status(bank, &status);
 790         if (res != ERROR_OK)
 791                 return res;
 792
 793         /* Check for a sequence error */
 794         if (status & FSR_SQER_MASK) {
 795                 LOG_ERROR("Error with flash write sequence");
 796                 return ERROR_FAIL;
 797         }
 798
 799         /* Make sure a flash write was triggered */
 800         if (!(status & FSR_PROG_MASK)) {
 801                 LOG_ERROR("Failed to write flash page");
 802                 return ERROR_FAIL;
 803         }
 804
 805         /* Wait for the write operation to end */
 806         res = xmc4xxx_wait_status_busy(bank, FLASH_OP_TIMEOUT);
 807         if (res != ERROR_OK)
 808                 return res;
 809
 810         /* TODO: Verify that page was written without error */
 811         return res;
 812 }
 813
 814 static int xmc4xxx_write(struct flash_bank *bank, const uint8_t *buffer,
 815                          uint32_t offset, uint32_t count)
 816 {
 817         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 818         int res = ERROR_OK;
 819
 820         if (bank->target->state != TARGET_HALTED) {
 821                 LOG_ERROR("Unable to erase, target is not halted");
 822                 return ERROR_TARGET_NOT_HALTED;
 823         }
 824
 825         if (!fb->probed) {
 826                 res = xmc4xxx_probe(bank);
 827                 if (res != ERROR_OK)
 828                         return res;
 829         }
 830
 831         /* Make sure we won't run off the end of the flash bank */
 832         if ((offset + count) > (bank->size)) {
 833                 LOG_ERROR("Attempting to write past the end of flash");
 834                 return ERROR_FAIL;
 835         }
 836
 837
 838         /* Attempt to write the passed in buffer to flash */
 839         /* Pages are written 256 bytes at a time, we need to handle
 840          * scenarios where padding is required at the beginning and
 841          * end of a page */
 842         while (count) {
 843                 /* page working area */
 844                 uint8_t tmp_buf[256] = {0};
 845
 846                 /* Amount of data we'll be writing to this page */
 847                 int remaining;
 848                 int end_pad;
 849
 850                 remaining = MIN(count, sizeof(tmp_buf));
 851                 end_pad   = sizeof(tmp_buf) - remaining;
 852
 853                 /* Make sure we're starting on a page boundary */
 854                 int start_pad = offset % 256;
 855                 if (start_pad) {
 856                         LOG_INFO("Write does not start on a 256 byte boundary. "
 857                                  "Padding by %d bytes", start_pad);
 858                         memset(tmp_buf, 0xff, start_pad);
 859                         /* Subtract the amount of start offset from
 860                          * the amount of data we'll need to write */
 861                         remaining -= start_pad;
 862                 }
 863
 864                 /* Remove the amount we'll be writing from the total count */
 865                 count -= remaining;
 866
 867                 /* Now copy in the remaining data */
 868                 memcpy(&tmp_buf[start_pad], buffer, remaining);
 869
 870                 if (end_pad) {
 871                         LOG_INFO("Padding end of page @%08"PRIx32" by %d bytes",
 872                                  bank->base + offset, end_pad);
 873                         memset(&tmp_buf[256 - end_pad], 0xff, end_pad);
 874                 }
 875
 876                 /* Now commit this page to flash, if there was start
 877                  * padding, we should subtract that from the target offset */
 878                 res = xmc4xxx_write_page(bank, tmp_buf, (offset - start_pad), false);
 879                 if (res != ERROR_OK) {
 880                         LOG_ERROR("Unable to write flash page");
 881                         goto abort_write_and_exit;
 882                 }
 883
 884                 /* Advance the buffer pointer */
 885                 buffer += remaining;
 886
 887                 /* Advance the offset */
 888                 offset += remaining;
 889         }
 890
 891 abort_write_and_exit:
 892         xmc4xxx_clear_flash_status(bank);
 893         return res;
 894
 895 }
 896
 897 static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
 898 {
 899         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
 900         uint32_t scu_idcode;
 901
 902         if (bank->target->state != TARGET_HALTED) {
 903                 LOG_WARNING("Cannot communicate... target not halted.");
 904                 return ERROR_TARGET_NOT_HALTED;
 905         }
 906
 907         /* The SCU registers contain the ID of the chip */
 908         int res = target_read_u32(bank->target, SCU_REG_BASE + SCU_ID_CHIP, &scu_idcode);
 909         if (res != ERROR_OK) {
 910                 LOG_ERROR("Cannot read device identification register.");
 911                 return res;
 912         }
 913
 914         uint16_t dev_id = (scu_idcode & 0xfff0) >> 4;
 915         uint16_t rev_id = scu_idcode & 0xf;
 916         const char *dev_str;
 917         const char *rev_str = NULL;
 918
 919         switch (dev_id) {
 920         case 0x100:
 921                 dev_str = "XMC4100";
 922
 923                 switch (rev_id) {
 924                 case 0x1:
 925                         rev_str = "AA";
 926                         break;
 927                 case 0x2:
 928                         rev_str = "AB";
 929                         break;
 930                 }
 931                 break;
 932         case 0x200:
 933                 dev_str = "XMC4200";
 934
 935                 switch (rev_id) {
 936                 case 0x1:
 937                         rev_str = "AA";
 938                         break;
 939                 case 0x2:
 940                         rev_str = "AB";
 941                         break;
 942                 }
 943                 break;
 944         case 0x400:
 945                 dev_str = "XMC4400";
 946
 947                 switch (rev_id) {
 948                 case 0x1:
 949                         rev_str = "AA";
 950                         break;
 951                 case 0x2:
 952                         rev_str = "AB";
 953                         break;
 954                 }
 955                 break;
 956         case 0:
 957                 /* XMC4500 EES AA13 with date codes before GE212
 958                  * had zero SCU_IDCHIP
 959                  */
 960                 dev_str = "XMC4500 EES";
 961                 rev_str = "AA13";
 962                 break;
 963         case 0x500:
 964                 dev_str = "XMC4500";
 965
 966                 switch (rev_id) {
 967                 case 0x2:
 968                         rev_str = "AA";
 969                         break;
 970                 case 0x3:
 971                         rev_str = "AB";
 972                         break;
 973                 case 0x4:
 974                         rev_str = "AC";
 975                         break;
 976                 }
 977                 break;
 978         case 0x700:
 979                 dev_str = "XMC4700";
 980
 981                 switch (rev_id) {
 982                 case 0x1:
 983                         rev_str = "EES-AA";
 984                         break;
 985                 }
 986                 break;
 987         case 0x800:
 988                 dev_str = "XMC4800";
 989
 990                 switch (rev_id) {
 991                 case 0x1:
 992                         rev_str = "EES-AA";
 993                         break;
 994                 }
 995                 break;
 996
 997         default:
 998                 snprintf(buf, buf_size,
 999                          "Cannot identify target as an XMC4xxx. SCU_ID: %"PRIx32"\n",
1000                          scu_idcode);
1001                 return ERROR_OK;
1002         }
1003
1004         /* String to declare protection data held in the private driver */
1005         char prot_str[512] = {0};
1006         if (fb->read_protected)
1007                 snprintf(prot_str, sizeof(prot_str), "\nFlash is read protected");
1008
1009         bool otp_enabled = false;
1010         for (int i = 0; i < bank->num_sectors; i++)
1011                 if (fb->write_prot_otp[i])
1012                         otp_enabled = true;
1013
1014         /* If OTP Write protection is enabled (User 2), list each
1015          * sector that has it enabled */
1016         char otp_str[8];
1017         if (otp_enabled) {
1018                 strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
1019                 for (int i = 0; i < bank->num_sectors; i++) {
1020                         if (fb->write_prot_otp[i]) {
1021                                 snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
1022                                 strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
1023                         }
1024                 }
1025         }
1026
1027         if (rev_str != NULL)
1028                 snprintf(buf, buf_size, "%s - Rev: %s%s",
1029                          dev_str, rev_str, prot_str);
1030         else
1031                 snprintf(buf, buf_size, "%s - Rev: unknown (0x%01x)%s",
1032                          dev_str, rev_id, prot_str);
1033
1034         return ERROR_OK;
1035 }
1036
1037 static int xmc4xxx_temp_unprotect(struct flash_bank *bank, int user_level)
1038 {
1039         struct xmc4xxx_flash_bank *fb;
1040         int res = ERROR_OK;
1041         uint32_t status = 0;
1042
1043         struct xmc4xxx_command_seq temp_unprot_seq[6] = {
1044                 {FLASH_CMD_TEMP_UNPROT_1, 0xAA},
1045                 {FLASH_CMD_TEMP_UNPROT_2, 0x55},
1046                 {FLASH_CMD_TEMP_UNPROT_3, 0xFF}, /* Needs filled in */
1047                 {FLASH_CMD_TEMP_UNPROT_4, 0xFF}, /* Needs filled in */
1048                 {FLASH_CMD_TEMP_UNPROT_5, 0xFF}, /* Needs filled in */
1049                 {FLASH_CMD_TEMP_UNPROT_6, 0x05}
1050         };
1051
1052         if (user_level < 0 || user_level > 2) {
1053                 LOG_ERROR("Invalid user level, must be 0-2");
1054                 return ERROR_FAIL;
1055         }
1056
1057         fb = bank->driver_priv;
1058
1059         /* Fill in the user level and passwords */
1060         temp_unprot_seq[2].magic = user_level;
1061         temp_unprot_seq[3].magic = fb->pw1;
1062         temp_unprot_seq[4].magic = fb->pw2;
1063
1064         res = xmc4xxx_write_command_sequence(bank, temp_unprot_seq,
1065                                              ARRAY_SIZE(temp_unprot_seq));
1066         if (res != ERROR_OK) {
1067                 LOG_ERROR("Unable to write temp unprotect sequence");
1068                 return res;
1069         }
1070
1071         res = xmc4xxx_get_flash_status(bank, &status);
1072         if (res != ERROR_OK)
1073                 return res;
1074
1075         if (status & FSR_WPRODIS0) {
1076                 LOG_INFO("Flash is temporarily unprotected");
1077         } else {
1078                 LOG_INFO("Unable to disable flash protection");
1079                 res = ERROR_FAIL;
1080         }
1081
1082
1083         return res;
1084 }
1085
1086 static int xmc4xxx_flash_unprotect(struct flash_bank *bank, int32_t level)
1087 {
1088         uint32_t addr;
1089         int res;
1090
1091         if ((level < 0) || (level > 1)) {
1092                 LOG_ERROR("Invalid user level. Must be 0-1");
1093                 return ERROR_FAIL;
1094         }
1095
1096         switch (level) {
1097         case 0:
1098                 addr = UCB0_BASE;
1099                 break;
1100         case 1:
1101                 addr = UCB1_BASE;
1102                 break;
1103         }
1104
1105         res = xmc4xxx_erase_sector(bank, addr, true);
1106
1107         if (res != ERROR_OK)
1108                 LOG_ERROR("Error erasing user configuration block");
1109
1110         return res;
1111 }
1112
1113 /* Reference: "XMC4500 Flash Protection.pptx" app note */
1114 static int xmc4xxx_flash_protect(struct flash_bank *bank, int level, bool read_protect,
1115                                  int first, int last)
1116 {
1117         /* User configuration block buffers */
1118         uint8_t ucp0_buf[8 * sizeof(uint32_t)] = {0};
1119         uint32_t ucb_base = 0;
1120         uint32_t procon = 0;
1121         int res = ERROR_OK;
1122         uint32_t status = 0;
1123         bool proin = false;
1124
1125         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1126
1127         /* Read protect only works for user 0, make sure we don't try
1128          * to do something silly */
1129         if (level != 0 && read_protect) {
1130                 LOG_ERROR("Read protection is for user level 0 only!");
1131                 return ERROR_FAIL;
1132         }
1133
1134         /* Check to see if protection is already installed for the
1135          * specified user level.  If it is, the user configuration
1136          * block will need to be erased before we can continue */
1137
1138         /* Grab the flash status register*/
1139         res = xmc4xxx_get_flash_status(bank, &status);
1140         if (res != ERROR_OK)
1141                 return res;
1142
1143         switch (level) {
1144         case 0:
1145                 if ((status & FSR_RPROIN_MASK) || (status & FSR_WPROIN0_MASK))
1146                         proin = true;
1147                 break;
1148         case 1:
1149                 if (status & FSR_WPROIN1_MASK)
1150                         proin = true;
1151                 break;
1152         case 2:
1153                 if (status & FSR_WPROIN2_MASK)
1154                         proin = true;
1155                 break;
1156         }
1157
1158         if (proin) {
1159                 LOG_ERROR("Flash protection is installed for user %d"
1160                           " and must be removed before continuing", level);
1161                 return ERROR_FAIL;
1162         }
1163
1164         /* If this device has 12 flash sectors, protection for
1165          * sectors 10 & 11 are handled jointly. If we are trying to
1166          * write all sectors, we should decrement
1167          * last to ensure we don't write to a register bit that
1168          * doesn't exist*/
1169         if ((bank->num_sectors == 12) && (last == 12))
1170                 last--;
1171
1172         /*  We need to fill out the procon register representation
1173          *   that we will be writing to the device */
1174         for (int i = first; i <= last; i++)
1175                 procon |= 1 << i;
1176
1177         /* If read protection is requested, set the appropriate bit
1178          * (we checked that this is allowed above) */
1179         if (read_protect)
1180                 procon |= PROCON_RPRO_MASK;
1181
1182         LOG_DEBUG("Setting flash protection with procon:");
1183         LOG_DEBUG("PROCON: %"PRIx32, procon);
1184
1185         /* First we need to copy in the procon register to the buffer
1186          * we're going to attempt to write.  This is written twice */
1187         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], procon);
1188         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], procon);
1189
1190         /* Now we must copy in both flash passwords.  As with the
1191          * procon data, this must be written twice (4 total words
1192          * worth of data) */
1193         target_buffer_set_u32(bank->target, &ucp0_buf[4 * 4], fb->pw1);
1194         target_buffer_set_u32(bank->target, &ucp0_buf[5 * 4], fb->pw2);
1195         target_buffer_set_u32(bank->target, &ucp0_buf[6 * 4], fb->pw1);
1196         target_buffer_set_u32(bank->target, &ucp0_buf[7 * 4], fb->pw2);
1197
1198         /* Finally, (if requested) we copy in the confirmation
1199          * code so that the protection is permanent and will
1200          * require a password to undo. */
1201         target_buffer_set_u32(bank->target, &ucp0_buf[0 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1202         target_buffer_set_u32(bank->target, &ucp0_buf[2 * 4], FLASH_PROTECT_CONFIRMATION_CODE);
1203
1204         /* Now that the data is copied into place, we must write
1205          * these pages into flash */
1206
1207         /* The user configuration block base depends on what level of
1208          * protection we're trying to install, select the proper one */
1209         switch (level) {
1210         case 0:
1211                 ucb_base = UCB0_BASE;
1212                 break;
1213         case 1:
1214                 ucb_base = UCB1_BASE;
1215                 break;
1216         case 2:
1217                 ucb_base = UCB2_BASE;
1218                 break;
1219         }
1220
1221         /* Write the user config pages */
1222         res = xmc4xxx_write_page(bank, ucp0_buf, ucb_base, true);
1223         if (res != ERROR_OK) {
1224                 LOG_ERROR("Error writing user configuration block 0");
1225                 return res;
1226         }
1227
1228         return ERROR_OK;
1229 }
1230
1231 static int xmc4xxx_protect(struct flash_bank *bank, int set, int first, int last)
1232 {
1233         int ret;
1234         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1235
1236         /* Check for flash passwords */
1237         if (!fb->pw_set) {
1238                 LOG_ERROR("Flash passwords not set, use xmc4xxx flash_password to set them");
1239                 return ERROR_FAIL;
1240         }
1241
1242         /* We want to clear flash protection temporarily*/
1243         if (set == 0) {
1244                 LOG_WARNING("Flash protection will be temporarily disabled"
1245                             " for all pages (User 0 only)!");
1246                 ret = xmc4xxx_temp_unprotect(bank, 0);
1247                 return ret;
1248         }
1249
1250         /* Install write protection for user 0 on the specified pages */
1251         ret = xmc4xxx_flash_protect(bank, 0, false, first, last);
1252
1253         return ret;
1254 }
1255
1256 static int xmc4xxx_protect_check(struct flash_bank *bank)
1257 {
1258         int ret;
1259         uint32_t protection[3] = {0};
1260         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1261
1262         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON0, &protection[0]);
1263         if (ret != ERROR_OK) {
1264                 LOG_ERROR("Unable to read flash User0 protection register");
1265                 return ret;
1266         }
1267
1268         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON1, &protection[1]);
1269         if (ret != ERROR_OK) {
1270                 LOG_ERROR("Unable to read flash User1 protection register");
1271                 return ret;
1272         }
1273
1274         ret = target_read_u32(bank->target, FLASH_REG_FLASH0_PROCON2, &protection[2]);
1275         if (ret != ERROR_OK) {
1276                 LOG_ERROR("Unable to read flash User2 protection register");
1277                 return ret;
1278         }
1279
1280         int sectors = bank->num_sectors;
1281
1282         /* On devices with 12 sectors, sectors 10 & 11 are ptected
1283          * together instead of individually */
1284         if (sectors == 12)
1285                 sectors--;
1286
1287         /* Clear the protection status */
1288         for (int i = 0; i < bank->num_sectors; i++) {
1289                 bank->sectors[i].is_protected = 0;
1290                 fb->write_prot_otp[i] = false;
1291         }
1292         fb->read_protected = false;
1293
1294         /* The xmc4xxx series supports 3 levels of user protection
1295          * (User0, User1 (low priority), and User 2(OTP), we need to
1296          * check all 3 */
1297         for (unsigned int i = 0; i < ARRAY_SIZE(protection); i++) {
1298
1299                 /* Check for write protection on every available
1300                 *  sector */
1301                 for (int j = 0; j < sectors; j++) {
1302                         int set = (protection[i] & (1 << j)) ? 1 : 0;
1303                         bank->sectors[j].is_protected |= set;
1304
1305                         /* Handle sector 11 */
1306                         if (j == 10)
1307                                 bank->sectors[j + 1].is_protected |= set;
1308
1309                         /* User 2 indicates this protection is
1310                          * permanent, make note in the private driver structure */
1311                         if (i == 2 && set) {
1312                                 fb->write_prot_otp[j] = true;
1313
1314                                 /* Handle sector 11 */
1315                                 if (j == 10)
1316                                         fb->write_prot_otp[j + 1] = true;
1317                         }
1318
1319                 }
1320         }
1321
1322         /* XMC4xxx also supports read proptection, make a note
1323          * in the private driver structure */
1324         if (protection[0] & PROCON_RPRO_MASK)
1325                 fb->read_protected = true;
1326
1327         return ERROR_OK;
1328 }
1329
1330 FLASH_BANK_COMMAND_HANDLER(xmc4xxx_flash_bank_command)
1331 {
1332         bank->driver_priv = malloc(sizeof(struct xmc4xxx_flash_bank));
1333
1334         if (!bank->driver_priv)
1335                 return ERROR_FLASH_OPERATION_FAILED;
1336
1337         (void)memset(bank->driver_priv, 0, sizeof(struct xmc4xxx_flash_bank));
1338
1339         return ERROR_OK;
1340 }
1341
1342 COMMAND_HANDLER(xmc4xxx_handle_flash_password_command)
1343 {
1344         int res;
1345         struct flash_bank *bank;
1346
1347         if (CMD_ARGC < 3)
1348                 return ERROR_COMMAND_SYNTAX_ERROR;
1349
1350         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1351         if (res != ERROR_OK)
1352                 return res;
1353
1354         struct xmc4xxx_flash_bank *fb = bank->driver_priv;
1355
1356         errno = 0;
1357
1358         /* We skip over the flash bank */
1359         fb->pw1 = strtol(CMD_ARGV[1], NULL, 16);
1360
1361         if (errno)
1362                 return ERROR_COMMAND_SYNTAX_ERROR;
1363
1364         fb->pw2 = strtol(CMD_ARGV[2], NULL, 16);
1365
1366         if (errno)
1367                 return ERROR_COMMAND_SYNTAX_ERROR;
1368
1369         fb->pw_set = true;
1370
1371         command_print(CMD_CTX, "XMC4xxx flash passwords set to:\n");
1372         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw1);
1373         command_print(CMD_CTX, "-0x%08"PRIx32"\n", fb->pw2);
1374         return ERROR_OK;
1375 }
1376
1377 COMMAND_HANDLER(xmc4xxx_handle_flash_unprotect_command)
1378 {
1379         struct flash_bank *bank;
1380         int res;
1381         int32_t level;
1382
1383         if (CMD_ARGC < 2)
1384                 return ERROR_COMMAND_SYNTAX_ERROR;
1385
1386         res = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1387         if (res != ERROR_OK)
1388                 return res;
1389
1390         COMMAND_PARSE_NUMBER(s32, CMD_ARGV[1], level);
1391
1392         res = xmc4xxx_flash_unprotect(bank, level);
1393
1394         return res;
1395 }
1396
1397 static const struct command_registration xmc4xxx_exec_command_handlers[] = {
1398         {
1399                 .name = "flash_password",
1400                 .handler = xmc4xxx_handle_flash_password_command,
1401                 .mode = COMMAND_EXEC,
1402                 .usage = "bank_id password1 password2",
1403                 .help = "Set the flash passwords used for protect operations. "
1404                 "Passwords should be in standard hex form (0x00000000). "
1405                 "(You must call this before any other protect commands) "
1406                 "NOTE: The xmc4xxx's UCB area only allows for FOUR cycles. "
1407                 "Please use protection carefully!",
1408         },
1409         {
1410                 .name = "flash_unprotect",
1411                 .handler = xmc4xxx_handle_flash_unprotect_command,
1412                 .mode = COMMAND_EXEC,
1413                 .usage = "bank_id user_level[0-1]",
1414                 .help = "Permanently Removes flash protection (read and write) "
1415                 "for the specified user level",
1416         },      COMMAND_REGISTRATION_DONE
1417 };
1418
1419 static const struct command_registration xmc4xxx_command_handlers[] = {
1420         {
1421                 .name = "xmc4xxx",
1422                 .mode = COMMAND_ANY,
1423                 .help = "xmc4xxx flash command group",
1424                 .usage = "",
1425                 .chain = xmc4xxx_exec_command_handlers,
1426         },
1427         COMMAND_REGISTRATION_DONE
1428 };
1429
1430 struct flash_driver xmc4xxx_flash = {
1431         .name = "xmc4xxx",
1432         .commands = xmc4xxx_command_handlers,
1433         .flash_bank_command = xmc4xxx_flash_bank_command,
1434         .erase = xmc4xxx_erase,
1435         .write = xmc4xxx_write,
1436         .read = default_flash_read,
1437         .probe = xmc4xxx_probe,
1438         .auto_probe = xmc4xxx_probe,
1439         .erase_check = xmc4xxx_flash_blank_check,
1440         .info = xmc4xxx_get_info_command,
1441         .protect_check = xmc4xxx_protect_check,
1442         .protect = xmc4xxx_protect,
1443 };