]> git.sur5r.net Git - openocd/blob - src/target/Makefile.am
Rework/update ARM semihosting
[openocd] / src / target / Makefile.am
1 if OOCD_TRACE
2 OOCD_TRACE_FILES = %D%/oocd_trace.c
3 else
4 OOCD_TRACE_FILES =
5 endif
6
7 %C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
8
9 STARTUP_TCL_SRCS += %D%/startup.tcl
10
11 noinst_LTLIBRARIES += %D%/libtarget.la
12 %C%_libtarget_la_SOURCES = \
13         $(TARGET_CORE_SRC) \
14         $(ARM_DEBUG_SRC) \
15         $(ARMV4_5_SRC) \
16         $(ARMV6_SRC) \
17         $(ARMV7_SRC) \
18         $(ARM_MISC_SRC) \
19         $(AVR32_SRC) \
20         $(MIPS32_SRC) \
21         $(NDS32_SRC) \
22         $(STM8_SRC) \
23         $(INTEL_IA32_SRC) \
24         %D%/avrt.c \
25         %D%/dsp563xx.c \
26         %D%/dsp563xx_once.c \
27         %D%/dsp5680xx.c \
28         %D%/hla_target.c
29
30 if TARGET64
31 %C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
32 endif
33
34 TARGET_CORE_SRC = \
35         %D%/algorithm.c \
36         %D%/register.c \
37         %D%/image.c \
38         %D%/breakpoints.c \
39         %D%/target.c \
40         %D%/target_request.c \
41         %D%/testee.c \
42         %D%/semihosting_common.c \
43         %D%/smp.c
44
45 ARMV4_5_SRC = \
46         %D%/armv4_5.c \
47         %D%/armv4_5_mmu.c \
48         %D%/armv4_5_cache.c \
49         $(ARM7_9_SRC)
50
51 ARM7_9_SRC = \
52         %D%/arm7_9_common.c \
53         %D%/arm7tdmi.c \
54         %D%/arm720t.c \
55         %D%/arm9tdmi.c \
56         %D%/arm920t.c \
57         %D%/arm966e.c \
58         %D%/arm946e.c \
59         %D%/arm926ejs.c \
60         %D%/feroceon.c
61
62 ARM_MISC_SRC = \
63         %D%/fa526.c \
64         %D%/xscale.c
65
66 ARMV6_SRC = \
67         %D%/arm11.c \
68         %D%/arm11_dbgtap.c
69
70 ARMV7_SRC = \
71         %D%/armv7m.c \
72         %D%/armv7m_trace.c \
73         %D%/cortex_m.c \
74         %D%/armv7a.c \
75         %D%/cortex_a.c \
76         %D%/ls1_sap.c
77
78 ARMV8_SRC = \
79         %D%/armv8_dpm.c \
80         %D%/armv8_opcodes.c \
81         %D%/aarch64.c \
82         %D%/armv8.c \
83         %D%/armv8_cache.c
84
85 ARM_DEBUG_SRC = \
86         %D%/arm_dpm.c \
87         %D%/arm_jtag.c \
88         %D%/arm_disassembler.c \
89         %D%/arm_simulator.c \
90         %D%/arm_semihosting.c \
91         %D%/arm_adi_v5.c \
92         %D%/arm_dap.c \
93         %D%/armv7a_cache.c \
94         %D%/armv7a_cache_l2x.c \
95         %D%/adi_v5_jtag.c \
96         %D%/adi_v5_swd.c \
97         %D%/embeddedice.c \
98         %D%/trace.c \
99         %D%/etb.c \
100         %D%/etm.c \
101         $(OOCD_TRACE_FILES) \
102         %D%/etm_dummy.c \
103         %D%/arm_cti.c
104
105 AVR32_SRC = \
106         %D%/avr32_ap7k.c \
107         %D%/avr32_jtag.c \
108         %D%/avr32_mem.c \
109         %D%/avr32_regs.c
110
111 MIPS32_SRC = \
112         %D%/mips32.c \
113         %D%/mips_m4k.c \
114         %D%/mips32_pracc.c \
115         %D%/mips32_dmaacc.c \
116         %D%/mips_ejtag.c
117
118 NDS32_SRC = \
119         %D%/nds32.c \
120         %D%/nds32_reg.c \
121         %D%/nds32_cmd.c \
122         %D%/nds32_disassembler.c \
123         %D%/nds32_tlb.c \
124         %D%/nds32_v2.c \
125         %D%/nds32_v3_common.c \
126         %D%/nds32_v3.c \
127         %D%/nds32_v3m.c \
128         %D%/nds32_aice.c
129
130 STM8_SRC = \
131         %D%/stm8.c
132
133 INTEL_IA32_SRC = \
134         %D%/quark_x10xx.c \
135         %D%/quark_d20xx.c \
136         %D%/lakemont.c \
137         %D%/x86_32_common.c
138
139 %C%_libtarget_la_SOURCES += \
140         %D%/algorithm.h \
141         %D%/arm.h \
142         %D%/arm_dpm.h \
143         %D%/arm_jtag.h \
144         %D%/arm_adi_v5.h \
145         %D%/armv7a_cache.h \
146         %D%/armv7a_cache_l2x.h \
147         %D%/arm_disassembler.h \
148         %D%/arm_opcodes.h \
149         %D%/arm_simulator.h \
150         %D%/arm_semihosting.h \
151         %D%/arm7_9_common.h \
152         %D%/arm7tdmi.h \
153         %D%/arm720t.h \
154         %D%/arm9tdmi.h \
155         %D%/arm920t.h \
156         %D%/arm926ejs.h \
157         %D%/arm966e.h \
158         %D%/arm946e.h \
159         %D%/arm11.h \
160         %D%/arm11_dbgtap.h \
161         %D%/armv4_5.h \
162         %D%/armv4_5_mmu.h \
163         %D%/armv4_5_cache.h \
164         %D%/armv7a.h \
165         %D%/armv7m.h \
166         %D%/armv7m_trace.h \
167         %D%/armv8.h \
168         %D%/armv8_dpm.h \
169         %D%/armv8_opcodes.h \
170         %D%/armv8_cache.h \
171         %D%/avrt.h \
172         %D%/dsp563xx.h \
173         %D%/dsp563xx_once.h \
174         %D%/dsp5680xx.h \
175         %D%/breakpoints.h \
176         %D%/cortex_m.h \
177         %D%/cortex_a.h \
178         %D%/aarch64.h \
179         %D%/embeddedice.h \
180         %D%/etb.h \
181         %D%/etm.h \
182         %D%/etm_dummy.h \
183         %D%/image.h \
184         %D%/mips32.h \
185         %D%/mips_m4k.h \
186         %D%/mips_ejtag.h \
187         %D%/mips32_pracc.h \
188         %D%/mips32_dmaacc.h \
189         %D%/oocd_trace.h \
190         %D%/register.h \
191         %D%/target.h \
192         %D%/target_type.h \
193         %D%/trace.h \
194         %D%/target_request.h \
195         %D%/trace.h \
196         %D%/xscale.h \
197         %D%/smp.h \
198         %D%/avr32_ap7k.h \
199         %D%/avr32_jtag.h \
200         %D%/avr32_mem.h \
201         %D%/avr32_regs.h \
202         %D%/nds32.h \
203         %D%/nds32_cmd.h \
204         %D%/nds32_disassembler.h \
205         %D%/nds32_edm.h \
206         %D%/nds32_insn.h \
207         %D%/nds32_reg.h \
208         %D%/nds32_tlb.h \
209         %D%/nds32_v2.h \
210         %D%/nds32_v3_common.h \
211         %D%/nds32_v3.h \
212         %D%/nds32_v3m.h \
213         %D%/nds32_aice.h \
214         %D%/semihosting_common.h \
215         %D%/stm8.h \
216         %D%/lakemont.h \
217         %D%/x86_32_common.h \
218         %D%/arm_cti.h
219
220 include %D%/openrisc/Makefile.am