1 /***************************************************************************
3 * Copyright (C) 2010 by David Brownell
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
29 * Single-DAP support only.
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
61 static int swd_finish_read(struct adiv5_dap *dap)
63 const struct swd_driver *swd = jtag_interface->swd;
64 int retval = ERROR_OK;
65 if (dap->last_read != NULL) {
66 retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
67 dap->last_read = NULL;
72 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
75 static int swd_clear_sticky_errors(struct adiv5_dap *dap)
77 const struct swd_driver *swd = jtag_interface->swd;
80 return swd->write_reg(swd_cmd(false, false, DP_ABORT),
81 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
84 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
86 const struct swd_driver *swd = jtag_interface->swd;
89 return swd->write_reg(swd_cmd(false, false, DP_ABORT),
90 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
93 /** Select the DP register bank matching bits 7:4 of reg. */
94 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
96 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
101 if (select_dp_bank == dap->dp_bank_value)
104 dap->dp_bank_value = select_dp_bank;
105 select_dp_bank |= dap->ap_current | dap->ap_bank_value;
107 return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
110 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
114 /* REVISIT status return vs ack ... */
115 const struct swd_driver *swd = jtag_interface->swd;
118 retval = swd_queue_dp_bankselect(dap, reg);
119 if (retval != ERROR_OK)
122 retval = swd->read_reg(swd_cmd(true, false, reg), data);
124 if (retval != ERROR_OK) {
126 swd_clear_sticky_errors(dap);
133 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
137 /* REVISIT status return vs ack ... */
138 const struct swd_driver *swd = jtag_interface->swd;
141 retval = swd_finish_read(dap);
142 if (retval != ERROR_OK)
145 retval = swd_queue_dp_bankselect(dap, reg);
146 if (retval != ERROR_OK)
149 retval = swd->write_reg(swd_cmd(false, false, reg), data);
151 if (retval != ERROR_OK) {
153 swd_clear_sticky_errors(dap);
159 /** Select the AP register bank matching bits 7:4 of reg. */
160 static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
162 uint32_t select_ap_bank = reg & 0x000000F0;
164 if (select_ap_bank == dap->ap_bank_value)
167 dap->ap_bank_value = select_ap_bank;
168 select_ap_bank |= dap->ap_current | dap->dp_bank_value;
170 return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
173 static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
176 /* REVISIT status return ... */
177 const struct swd_driver *swd = jtag_interface->swd;
180 int retval = swd_queue_ap_bankselect(dap, reg);
181 if (retval != ERROR_OK)
184 retval = swd->read_reg(swd_cmd(true, true, reg), dap->last_read);
185 dap->last_read = data;
187 if (retval != ERROR_OK) {
189 swd_clear_sticky_errors(dap);
196 static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
199 /* REVISIT status return ... */
200 const struct swd_driver *swd = jtag_interface->swd;
204 retval = swd_finish_read(dap);
205 if (retval != ERROR_OK)
208 retval = swd_queue_ap_bankselect(dap, reg);
209 if (retval != ERROR_OK)
212 retval = swd->write_reg(swd_cmd(false, true, reg), data);
214 if (retval != ERROR_OK) {
216 swd_clear_sticky_errors(dap);
222 /** Executes all queued DAP operations. */
223 static int swd_run(struct adiv5_dap *dap)
225 /* for now the SWD interface hard-wires a zero-size queue. */
227 int retval = swd_finish_read(dap);
229 /* FIXME but we still need to check and scrub
230 * any hardware errors ...
235 const struct dap_ops swd_dap_ops = {
238 .queue_dp_read = swd_queue_dp_read,
239 .queue_dp_write = swd_queue_dp_write,
240 .queue_ap_read = swd_queue_ap_read,
241 .queue_ap_write = swd_queue_ap_write,
242 .queue_ap_abort = swd_queue_ap_abort,
247 * This represents the bits which must be sent out on TMS/SWDIO to
248 * switch a DAP implemented using an SWJ-DP module into SWD mode.
249 * These bits are stored (and transmitted) LSB-first.
251 * See the DAP-Lite specification, section 2.2.5 for information
252 * about making the debug link select SWD or JTAG. (Similar info
253 * is in a few other ARM documents.)
255 static const uint8_t jtag2swd_bitseq[] = {
256 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
257 * putting both JTAG and SWD logic into reset state.
259 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
260 /* Switching sequence enables SWD and disables JTAG
261 * NOTE: bits in the DP's IDCODE may expose the need for
262 * an old/obsolete/deprecated sequence (0xb6 0xed).
265 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
266 * putting both JTAG and SWD logic into reset state.
268 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
272 * Put the debug link into SWD mode, if the target supports it.
273 * The link's initial mode may be either JTAG (for example,
274 * with SWJ-DP after reset) or SWD.
276 * @param target Enters SWD mode (if possible).
278 * Note that targets using the JTAG-DP do not support SWD, and that
279 * some targets which could otherwise support it may have have been
280 * configured to disable SWD signaling
282 * @return ERROR_OK or else a fault code.
284 int dap_to_swd(struct target *target)
286 struct arm *arm = target_to_arm(target);
289 LOG_DEBUG("Enter SWD mode");
291 /* REVISIT it's ugly to need to make calls to a "jtag"
292 * subsystem if the link may not be in JTAG mode...
295 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
296 jtag2swd_bitseq, TAP_INVALID);
297 if (retval == ERROR_OK)
298 retval = jtag_execute_queue();
300 /* set up the DAP's ops vector for SWD mode. */
301 arm->dap->ops = &swd_dap_ops;
306 COMMAND_HANDLER(handle_swd_wcr)
309 struct target *target = get_current_target(CMD_CTX);
310 struct arm *arm = target_to_arm(target);
311 struct adiv5_dap *dap = arm->dap;
313 unsigned trn, scale = 0;
316 /* no-args: just dump state */
318 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
319 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
320 if (retval == ERROR_OK)
322 if (retval != ERROR_OK) {
323 LOG_ERROR("can't read WCR?");
327 command_print(CMD_CTX,
328 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
330 WCR_TO_PRESCALE(wcr));
333 case 2: /* TRN and prescale */
334 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
336 LOG_ERROR("prescale %d is too big", scale);
341 case 1: /* TRN only */
342 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
343 if (trn < 1 || trn > 4) {
344 LOG_ERROR("turnaround %d is invalid", trn);
348 wcr = ((trn - 1) << 8) | scale;
351 * then, re-init adapter with new TRN
353 LOG_ERROR("can't yet modify WCR");
356 default: /* too many arguments */
357 return ERROR_COMMAND_SYNTAX_ERROR;
361 static const struct command_registration swd_commands[] = {
364 * Set up SWD and JTAG targets identically, unless/until
365 * infrastructure improves ... meanwhile, ignore all
366 * JTAG-specific stuff like IR length for SWD.
368 * REVISIT can we verify "just one SWD DAP" here/early?
371 .jim_handler = jim_jtag_newtap,
372 .mode = COMMAND_CONFIG,
373 .help = "declare a new SWD DAP"
377 .handler = handle_swd_wcr,
379 .help = "display or update DAP's WCR register",
380 .usage = "turnaround (1..4), prescale (0..7)",
383 /* REVISIT -- add a command for SWV trace on/off */
384 COMMAND_REGISTRATION_DONE
387 static const struct command_registration swd_handlers[] = {
391 .help = "SWD command group",
392 .chain = swd_commands,
394 COMMAND_REGISTRATION_DONE
397 static int swd_select(struct command_context *ctx)
401 retval = register_commands(ctx, NULL, swd_handlers);
403 if (retval != ERROR_OK)
406 const struct swd_driver *swd = jtag_interface->swd;
408 /* be sure driver is in SWD mode; start
409 * with hardware default TRN (1), it can be changed later
411 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
412 LOG_DEBUG("no SWD driver?");
416 retval = swd->init(1);
417 if (retval != ERROR_OK) {
418 LOG_DEBUG("can't init SWD driver");
422 /* force DAP into SWD mode (not JTAG) */
423 /*retval = dap_to_swd(target);*/
425 if (ctx->current_target) {
426 /* force DAP into SWD mode (not JTAG) */
427 struct target *target = get_current_target(ctx);
428 retval = dap_to_swd(target);
434 static int swd_init(struct command_context *ctx)
436 struct target *target = get_current_target(ctx);
437 struct arm *arm = target_to_arm(target);
438 struct adiv5_dap *dap = arm->dap;
442 /* Force the DAP's ops vector for SWD mode.
443 * messy - is there a better way? */
444 arm->dap->ops = &swd_dap_ops;
446 /* FIXME validate transport config ... is the
447 * configured DAP present (check IDCODE)?
448 * Is *only* one DAP configured?
453 /* Note, debugport_init() does setup too */
455 status = swd_queue_dp_read(dap, DP_IDCODE, &idcode);
457 if (status == ERROR_OK)
458 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
460 /* force clear all sticky faults */
461 swd_clear_sticky_errors(dap);
463 /* this is a workaround to get polling working */
464 jtag_add_reset(0, 0);
469 static struct transport swd_transport = {
471 .select = swd_select,
475 static void swd_constructor(void) __attribute__((constructor));
476 static void swd_constructor(void)
478 transport_register(&swd_transport);
481 /** Returns true if the current debug session
482 * is using SWD as its transport.
484 bool transport_is_swd(void)
486 return get_current_transport() == &swd_transport;