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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116         }
 117 }
 118
 119 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 120 {
 121         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 122                 dap->ap[dap_ap_get_select(dap)].csw_default;
 123
 124         if (csw != dap->ap[dap_ap_get_select(dap)].csw_value) {
 125                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 126                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
 127                 if (retval != ERROR_OK)
 128                         return retval;
 129                 dap->ap[dap_ap_get_select(dap)].csw_value = csw;
 130         }
 131         return ERROR_OK;
 132 }
 133
 134 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 135 {
 136         if (tar != dap->ap[dap_ap_get_select(dap)].tar_value ||
 137                         (dap->ap[dap_ap_get_select(dap)].csw_value & CSW_ADDRINC_MASK)) {
 138                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 139                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
 140                 if (retval != ERROR_OK)
 141                         return retval;
 142                 dap->ap[dap_ap_get_select(dap)].tar_value = tar;
 143         }
 144         return ERROR_OK;
 145 }
 146
 147 /**
 148  * Queue transactions setting up transfer parameters for the
 149  * currently selected MEM-AP.
 150  *
 151  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 152  * initiate data reads or writes using memory or peripheral addresses.
 153  * If the CSW is configured for it, the TAR may be automatically
 154  * incremented after each transfer.
 155  *
 156  * @todo Rename to reflect it being specifically a MEM-AP function.
 157  *
 158  * @param dap The DAP connected to the MEM-AP.
 159  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 160  *      matches the cached value, the register is not changed.
 161  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 162  *      matches the cached address, the register is not changed.
 163  *
 164  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 165  */
 166 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 167 {
 168         int retval;
 169         retval = dap_setup_accessport_csw(dap, csw);
 170         if (retval != ERROR_OK)
 171                 return retval;
 172         retval = dap_setup_accessport_tar(dap, tar);
 173         if (retval != ERROR_OK)
 174                 return retval;
 175         return ERROR_OK;
 176 }
 177
 178 /**
 179  * Asynchronous (queued) read of a word from memory or a system register.
 180  *
 181  * @param dap The DAP connected to the MEM-AP performing the read.
 182  * @param address Address of the 32-bit word to read; it must be
 183  *      readable by the currently selected MEM-AP.
 184  * @param value points to where the word will be stored when the
 185  *      transaction queue is flushed (assuming no errors).
 186  *
 187  * @return ERROR_OK for success.  Otherwise a fault code.
 188  */
 189 static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
 190                 uint32_t *value)
 191 {
 192         int retval;
 193
 194         /* Use banked addressing (REG_BDx) to avoid some link traffic
 195          * (updating TAR) when reading several consecutive addresses.
 196          */
 197         retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
 198                         address & 0xFFFFFFF0);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         return dap_queue_ap_read(ap->dap, MEM_AP_REG_BD0 | (address & 0xC), value);
 203 }
 204
 205 /**
 206  * Synchronous read of a word from memory or a system register.
 207  * As a side effect, this flushes any queued transactions.
 208  *
 209  * @param dap The DAP connected to the MEM-AP performing the read.
 210  * @param address Address of the 32-bit word to read; it must be
 211  *      readable by the currently selected MEM-AP.
 212  * @param value points to where the result will be stored.
 213  *
 214  * @return ERROR_OK for success; *value holds the result.
 215  * Otherwise a fault code.
 216  */
 217 static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 218                 uint32_t *value)
 219 {
 220         int retval;
 221
 222         retval = mem_ap_read_u32(ap, address, value);
 223         if (retval != ERROR_OK)
 224                 return retval;
 225
 226         return dap_run(ap->dap);
 227 }
 228
 229 /**
 230  * Asynchronous (queued) write of a word to memory or a system register.
 231  *
 232  * @param dap The DAP connected to the MEM-AP.
 233  * @param address Address to be written; it must be writable by
 234  *      the currently selected MEM-AP.
 235  * @param value Word that will be written to the address when transaction
 236  *      queue is flushed (assuming no errors).
 237  *
 238  * @return ERROR_OK for success.  Otherwise a fault code.
 239  */
 240 static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
 241                 uint32_t value)
 242 {
 243         int retval;
 244
 245         /* Use banked addressing (REG_BDx) to avoid some link traffic
 246          * (updating TAR) when writing several consecutive addresses.
 247          */
 248         retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
 249                         address & 0xFFFFFFF0);
 250         if (retval != ERROR_OK)
 251                 return retval;
 252
 253         return dap_queue_ap_write(ap->dap, MEM_AP_REG_BD0 | (address & 0xC),
 254                         value);
 255 }
 256
 257 /**
 258  * Synchronous write of a word to memory or a system register.
 259  * As a side effect, this flushes any queued transactions.
 260  *
 261  * @param dap The DAP connected to the MEM-AP.
 262  * @param address Address to be written; it must be writable by
 263  *      the currently selected MEM-AP.
 264  * @param value Word that will be written.
 265  *
 266  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 267  */
 268 static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 269                 uint32_t value)
 270 {
 271         int retval = mem_ap_write_u32(ap, address, value);
 272
 273         if (retval != ERROR_OK)
 274                 return retval;
 275
 276         return dap_run(ap->dap);
 277 }
 278
 279 /**
 280  * Synchronous write of a block of memory, using a specific access size.
 281  *
 282  * @param dap The DAP connected to the MEM-AP.
 283  * @param buffer The data buffer to write. No particular alignment is assumed.
 284  * @param size Which access size to use, in bytes. 1, 2 or 4.
 285  * @param count The number of writes to do (in size units, not bytes).
 286  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 287  * @param addrinc Whether the target address should be increased for each write or not. This
 288  *  should normally be true, except when writing to e.g. a FIFO.
 289  * @return ERROR_OK on success, otherwise an error code.
 290  */
 291 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
 292                 uint32_t address, bool addrinc)
 293 {
 294         struct adiv5_dap *dap = ap->dap;
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (ap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && ap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         struct adiv5_dap *dap = ap->dap;
 426         size_t nbytes = size * count;
 427         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 428         uint32_t csw_size;
 429         uint32_t address = adr;
 430         int retval;
 431
 432         /* TI BE-32 Quirks mode:
 433          * Reads on big-endian TMS570 behave strangely differently than writes.
 434          * They read from the physical address requested, but with DRW byte-reversed.
 435          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 436          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 437          * so avoid them. */
 438
 439         if (size == 4)
 440                 csw_size = CSW_32BIT;
 441         else if (size == 2)
 442                 csw_size = CSW_16BIT;
 443         else if (size == 1)
 444                 csw_size = CSW_8BIT;
 445         else
 446                 return ERROR_TARGET_UNALIGNED_ACCESS;
 447
 448         if (ap->unaligned_access_bad && (adr % size != 0))
 449                 return ERROR_TARGET_UNALIGNED_ACCESS;
 450
 451         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 452          * over-allocation if packed transfers are going to be used, but determining the real need at
 453          * this point would be messy. */
 454         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 455         uint32_t *read_ptr = read_buf;
 456         if (read_buf == NULL) {
 457                 LOG_ERROR("Failed to allocate read buffer");
 458                 return ERROR_FAIL;
 459         }
 460
 461         retval = dap_setup_accessport_tar(dap, address);
 462         if (retval != ERROR_OK) {
 463                 free(read_buf);
 464                 return retval;
 465         }
 466
 467         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 468          * useful bytes it contains, and their location in the word, depends on the type of transfer
 469          * and alignment. */
 470         while (nbytes > 0) {
 471                 uint32_t this_size = size;
 472
 473                 /* Select packed transfer if possible */
 474                 if (addrinc && ap->packed_transfers && nbytes >= 4
 475                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 476                         this_size = 4;
 477                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 478                 } else {
 479                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 480                 }
 481                 if (retval != ERROR_OK)
 482                         break;
 483
 484                 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
 485                 if (retval != ERROR_OK)
 486                         break;
 487
 488                 nbytes -= this_size;
 489                 address += this_size;
 490
 491                 /* Rewrite TAR if it wrapped */
 492                 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
 493                         retval = dap_setup_accessport_tar(dap, address);
 494                         if (retval != ERROR_OK)
 495                                 break;
 496                 }
 497         }
 498
 499         if (retval == ERROR_OK)
 500                 retval = dap_run(dap);
 501
 502         /* Restore state */
 503         address = adr;
 504         nbytes = size * count;
 505         read_ptr = read_buf;
 506
 507         /* If something failed, read TAR to find out how much data was successfully read, so we can
 508          * at least give the caller what we have. */
 509         if (retval != ERROR_OK) {
 510                 uint32_t tar;
 511                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 512                                 && dap_run(dap) == ERROR_OK) {
 513                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 514                         if (nbytes > tar - address)
 515                                 nbytes = tar - address;
 516                 } else {
 517                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 518                         nbytes = 0;
 519                 }
 520         }
 521
 522         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 523         while (nbytes > 0) {
 524                 uint32_t this_size = size;
 525
 526                 if (addrinc && ap->packed_transfers && nbytes >= 4
 527                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 528                         this_size = 4;
 529                 }
 530
 531                 if (dap->ti_be_32_quirks) {
 532                         switch (this_size) {
 533                         case 4:
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 536                         case 2:
 537                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 538                         case 1:
 539                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 540                         }
 541                 } else {
 542                         switch (this_size) {
 543                         case 4:
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 546                         case 2:
 547                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 548                         case 1:
 549                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 550                         }
 551                 }
 552
 553                 read_ptr++;
 554                 nbytes -= this_size;
 555         }
 556
 557         free(read_buf);
 558         return retval;
 559 }
 560
 561 /*--------------------------------------------------------------------*/
 562 /*          Wrapping function with selection of AP                    */
 563 /*--------------------------------------------------------------------*/
 564 int mem_ap_sel_read_u32(struct adiv5_ap *ap,
 565                 uint32_t address, uint32_t *value)
 566 {
 567         dap_ap_select(ap->dap, ap->ap_num);
 568         return mem_ap_read_u32(ap, address, value);
 569 }
 570
 571 int mem_ap_sel_write_u32(struct adiv5_ap *ap,
 572                 uint32_t address, uint32_t value)
 573 {
 574         dap_ap_select(ap->dap, ap->ap_num);
 575         return mem_ap_write_u32(ap, address, value);
 576 }
 577
 578 int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
 579                 uint32_t address, uint32_t *value)
 580 {
 581         dap_ap_select(ap->dap, ap->ap_num);
 582         return mem_ap_read_atomic_u32(ap, address, value);
 583 }
 584
 585 int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
 586                 uint32_t address, uint32_t value)
 587 {
 588         dap_ap_select(ap->dap, ap->ap_num);
 589         return mem_ap_write_atomic_u32(ap, address, value);
 590 }
 591
 592 int mem_ap_sel_read_buf(struct adiv5_ap *ap,
 593                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 594 {
 595         dap_ap_select(ap->dap, ap->ap_num);
 596         return mem_ap_read(ap, buffer, size, count, address, true);
 597 }
 598
 599 int mem_ap_sel_write_buf(struct adiv5_ap *ap,
 600                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 601 {
 602         dap_ap_select(ap->dap, ap->ap_num);
 603         return mem_ap_write(ap, buffer, size, count, address, true);
 604 }
 605
 606 int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
 607                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 608 {
 609         dap_ap_select(ap->dap, ap->ap_num);
 610         return mem_ap_read(ap, buffer, size, count, address, false);
 611 }
 612
 613 int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
 614                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 615 {
 616         dap_ap_select(ap->dap, ap->ap_num);
 617         return mem_ap_write(ap, buffer, size, count, address, false);
 618 }
 619
 620 /*--------------------------------------------------------------------------*/
 621
 622
 623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 624
 625 /* FIXME don't import ... just initialize as
 626  * part of DAP transport setup
 627 */
 628 extern const struct dap_ops jtag_dp_ops;
 629
 630 /*--------------------------------------------------------------------------*/
 631
 632 /**
 633  * Create a new DAP
 634  */
 635 struct adiv5_dap *dap_init(void)
 636 {
 637         struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
 638         int i;
 639         /* Set up with safe defaults */
 640         for (i = 0; i <= 255; i++) {
 641                 dap->ap[i].dap = dap;
 642                 dap->ap[i].ap_num = i;
 643                 /* memaccess_tck max is 255 */
 644                 dap->ap[i].memaccess_tck = 255;
 645                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
 646                 dap->ap[i].tar_autoincr_block = (1<<10);
 647         }
 648         dap->ap_current = -1;
 649         dap->ap_bank_value = -1;
 650         dap->dp_bank_value = -1;
 651         return dap;
 652 }
 653
 654 /**
 655  * Initialize a DAP.  This sets up the power domains, prepares the DP
 656  * for further use and activates overrun checking.
 657  *
 658  * @param dap The DAP being initialized.
 659  */
 660 int dap_dp_init(struct adiv5_dap *dap)
 661 {
 662         int retval;
 663
 664         LOG_DEBUG(" ");
 665         /* JTAG-DP or SWJ-DP, in JTAG mode
 666          * ... for SWD mode this is patched as part
 667          * of link switchover
 668          * FIXME: This should already be setup by the respective transport specific DAP creation.
 669          */
 670         if (!dap->ops)
 671                 dap->ops = &jtag_dp_ops;
 672
 673         dap->ap_current = -1;
 674         dap->ap_bank_value = -1;
 675         dap->last_read = NULL;
 676
 677         for (size_t i = 0; i < 10; i++) {
 678                 /* DP initialization */
 679
 680                 dap->dp_bank_value = 0;
 681
 682                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 683                 if (retval != ERROR_OK)
 684                         continue;
 685
 686                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 687                 if (retval != ERROR_OK)
 688                         continue;
 689
 690                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 691                 if (retval != ERROR_OK)
 692                         continue;
 693
 694                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 695                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 696                 if (retval != ERROR_OK)
 697                         continue;
 698
 699                 /* Check that we have debug power domains activated */
 700                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 701                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 702                                               CDBGPWRUPACK, CDBGPWRUPACK,
 703                                               DAP_POWER_DOMAIN_TIMEOUT);
 704                 if (retval != ERROR_OK)
 705                         continue;
 706
 707                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 708                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 709                                               CSYSPWRUPACK, CSYSPWRUPACK,
 710                                               DAP_POWER_DOMAIN_TIMEOUT);
 711                 if (retval != ERROR_OK)
 712                         continue;
 713
 714                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 715                 if (retval != ERROR_OK)
 716                         continue;
 717
 718                 /* With debug power on we can activate OVERRUN checking */
 719                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 720                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 721                 if (retval != ERROR_OK)
 722                         continue;
 723                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 724                 if (retval != ERROR_OK)
 725                         continue;
 726
 727                 retval = dap_run(dap);
 728                 if (retval != ERROR_OK)
 729                         continue;
 730
 731                 break;
 732         }
 733
 734         return retval;
 735 }
 736
 737 /**
 738  * Initialize a DAP.  This sets up the power domains, prepares the DP
 739  * for further use, and arranges to use AP #0 for all AP operations
 740  * until dap_ap-select() changes that policy.
 741  *
 742  * @param ap The MEM-AP being initialized.
 743  */
 744 int mem_ap_init(struct adiv5_ap *ap)
 745 {
 746         /* check that we support packed transfers */
 747         uint32_t csw, cfg;
 748         int retval;
 749         struct adiv5_dap *dap = ap->dap;
 750
 751         dap_ap_select(dap, ap->ap_num);
 752
 753         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 754         if (retval != ERROR_OK)
 755                 return retval;
 756
 757         retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
 758         if (retval != ERROR_OK)
 759                 return retval;
 760
 761         retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
 762         if (retval != ERROR_OK)
 763                 return retval;
 764
 765         retval = dap_run(dap);
 766         if (retval != ERROR_OK)
 767                 return retval;
 768
 769         if (csw & CSW_ADDRINC_PACKED)
 770                 ap->packed_transfers = true;
 771         else
 772                 ap->packed_transfers = false;
 773
 774         /* Packed transfers on TI BE-32 processors do not work correctly in
 775          * many cases. */
 776         if (dap->ti_be_32_quirks)
 777                 ap->packed_transfers = false;
 778
 779         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 780                         ap->packed_transfers ? "enabled" : "disabled");
 781
 782         /* The ARM ADI spec leaves implementation-defined whether unaligned
 783          * memory accesses work, only work partially, or cause a sticky error.
 784          * On TI BE-32 processors, reads seem to return garbage in some bytes
 785          * and unaligned writes seem to cause a sticky error.
 786          * TODO: it would be nice to have a way to detect whether unaligned
 787          * operations are supported on other processors. */
 788         ap->unaligned_access_bad = dap->ti_be_32_quirks;
 789
 790         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 791                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 792
 793         return ERROR_OK;
 794 }
 795
 796 /* CID interpretation -- see ARM IHI 0029B section 3
 797  * and ARM IHI 0031A table 13-3.
 798  */
 799 static const char *class_description[16] = {
 800         "Reserved", "ROM table", "Reserved", "Reserved",
 801         "Reserved", "Reserved", "Reserved", "Reserved",
 802         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 803         "Reserved", "OptimoDE DESS",
 804         "Generic IP component", "PrimeCell or System component"
 805 };
 806
 807 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 808 {
 809         return cid3 == 0xb1 && cid2 == 0x05
 810                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 811 }
 812
 813 /*
 814  * This function checks the ID for each access port to find the requested Access Port type
 815  */
 816 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 817 {
 818         int ap_num;
 819
 820         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 821         for (ap_num = 0; ap_num <= 255; ap_num++) {
 822
 823                 /* read the IDR register of the Access Port */
 824                 uint32_t id_val = 0;
 825                 dap_ap_select(dap, ap_num);
 826
 827                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 828                 if (retval != ERROR_OK)
 829                         return retval;
 830
 831                 retval = dap_run(dap);
 832
 833                 /* IDR bits:
 834                  * 31-28 : Revision
 835                  * 27-24 : JEDEC bank (0x4 for ARM)
 836                  * 23-17 : JEDEC code (0x3B for ARM)
 837                  * 16-13 : Class (0b1000=Mem-AP)
 838                  * 12-8  : Reserved
 839                  *  7-4  : AP Variant (non-zero for JTAG-AP)
 840                  *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 841                  */
 842
 843                 /* Reading register for a non-existant AP should not cause an error,
 844                  * but just to be sure, try to continue searching if an error does happen.
 845                  */
 846                 if ((retval == ERROR_OK) &&                  /* Register read success */
 847                         ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
 848                         ((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
 849
 850                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 851                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 852                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 853                                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 854                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 855                                                 ap_num, id_val);
 856
 857                         *ap_out = &dap->ap[ap_num];
 858                         return ERROR_OK;
 859                 }
 860         }
 861
 862         LOG_DEBUG("No %s found",
 863                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 864                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 865                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 866                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 867         return ERROR_FAIL;
 868 }
 869
 870 int dap_get_debugbase(struct adiv5_ap *ap,
 871                         uint32_t *dbgbase, uint32_t *apid)
 872 {
 873         struct adiv5_dap *dap = ap->dap;
 874         uint32_t ap_old;
 875         int retval;
 876
 877         ap_old = dap_ap_get_select(dap);
 878         dap_ap_select(dap, ap->ap_num);
 879
 880         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
 881         if (retval != ERROR_OK)
 882                 return retval;
 883         retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
 884         if (retval != ERROR_OK)
 885                 return retval;
 886         retval = dap_run(dap);
 887         if (retval != ERROR_OK)
 888                 return retval;
 889
 890         dap_ap_select(dap, ap_old);
 891
 892         return ERROR_OK;
 893 }
 894
 895 int dap_lookup_cs_component(struct adiv5_ap *ap,
 896                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 897 {
 898         struct adiv5_dap *dap = ap->dap;
 899         uint32_t ap_old;
 900         uint32_t romentry, entry_offset = 0, component_base, devtype;
 901         int retval;
 902
 903         *addr = 0;
 904         ap_old = dap_ap_get_select(dap);
 905
 906         do {
 907                 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
 908                                                 entry_offset, &romentry);
 909                 if (retval != ERROR_OK)
 910                         return retval;
 911
 912                 component_base = (dbgbase & 0xFFFFF000)
 913                         + (romentry & 0xFFFFF000);
 914
 915                 if (romentry & 0x1) {
 916                         uint32_t c_cid1;
 917                         retval = mem_ap_sel_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
 918                         if (retval != ERROR_OK) {
 919                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 920                                           ", the corresponding core might be turned off", component_base);
 921                                 return retval;
 922                         }
 923                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 924                                 retval = dap_lookup_cs_component(ap, component_base,
 925                                                         type, addr, idx);
 926                                 if (retval == ERROR_OK)
 927                                         break;
 928                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 929                                         return retval;
 930                         }
 931
 932                         retval = mem_ap_sel_read_atomic_u32(ap,
 933                                         (component_base & 0xfffff000) | 0xfcc,
 934                                         &devtype);
 935                         if (retval != ERROR_OK)
 936                                 return retval;
 937                         if ((devtype & 0xff) == type) {
 938                                 if (!*idx) {
 939                                         *addr = component_base;
 940                                         break;
 941                                 } else
 942                                         (*idx)--;
 943                         }
 944                 }
 945                 entry_offset += 4;
 946         } while (romentry > 0);
 947
 948         dap_ap_select(dap, ap_old);
 949
 950         if (!*addr)
 951                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 952
 953         return ERROR_OK;
 954 }
 955
 956 static int dap_rom_display(struct command_context *cmd_ctx,
 957                                 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 958 {
 959         struct adiv5_dap *dap = ap->dap;
 960         int retval;
 961         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 962         uint16_t entry_offset;
 963         char tabs[7] = "";
 964
 965         if (depth > 16) {
 966                 command_print(cmd_ctx, "\tTables too deep");
 967                 return ERROR_FAIL;
 968         }
 969
 970         if (depth)
 971                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 972
 973         /* bit 16 of apid indicates a memory access port */
 974         if (dbgbase & 0x02)
 975                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 976         else
 977                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 978
 979         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 980         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 981         if (retval != ERROR_OK)
 982                 return retval;
 983         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 984         if (retval != ERROR_OK)
 985                 return retval;
 986         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 987         if (retval != ERROR_OK)
 988                 return retval;
 989         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 990         if (retval != ERROR_OK)
 991                 return retval;
 992         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 993         if (retval != ERROR_OK)
 994                 return retval;
 995         retval = dap_run(dap);
 996         if (retval != ERROR_OK)
 997                 return retval;
 998
 999         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1000                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1001                                 ", CID2 0x%02x"
1002                                 ", CID1 0x%02x"
1003                                 ", CID0 0x%02x",
1004                                 tabs,
1005                                 (unsigned)cid3, (unsigned)cid2,
1006                                 (unsigned)cid1, (unsigned)cid0);
1007         if (memtype & 0x01)
1008                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1009         else
1010                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1011
1012         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1013         for (entry_offset = 0; ; entry_offset += 4) {
1014                 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1015                 if (retval != ERROR_OK)
1016                         return retval;
1017                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1018                                 tabs, entry_offset, romentry);
1019                 if (romentry & 0x01) {
1020                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1021                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1022                         uint32_t component_base;
1023                         uint32_t part_num;
1024                         const char *type, *full;
1025
1026                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1027
1028                         /* IDs are in last 4K section */
1029                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
1030                         if (retval != ERROR_OK) {
1031                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1032                                               ", the corresponding core might be turned off", tabs, component_base);
1033                                 continue;
1034                         }
1035                         c_pid0 &= 0xff;
1036                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
1037                         if (retval != ERROR_OK)
1038                                 return retval;
1039                         c_pid1 &= 0xff;
1040                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1041                         if (retval != ERROR_OK)
1042                                 return retval;
1043                         c_pid2 &= 0xff;
1044                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1045                         if (retval != ERROR_OK)
1046                                 return retval;
1047                         c_pid3 &= 0xff;
1048                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1049                         if (retval != ERROR_OK)
1050                                 return retval;
1051                         c_pid4 &= 0xff;
1052
1053                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1054                         if (retval != ERROR_OK)
1055                                 return retval;
1056                         c_cid0 &= 0xff;
1057                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1058                         if (retval != ERROR_OK)
1059                                 return retval;
1060                         c_cid1 &= 0xff;
1061                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1062                         if (retval != ERROR_OK)
1063                                 return retval;
1064                         c_cid2 &= 0xff;
1065                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1066                         if (retval != ERROR_OK)
1067                                 return retval;
1068                         c_cid3 &= 0xff;
1069
1070                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1071                                       "start address 0x%" PRIx32, component_base,
1072                                       /* component may take multiple 4K pages */
1073                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1074                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1075                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1076                                         /* See ARM IHI 0029B Table 3-3 */
1077                                         class_description[(c_cid1 >> 4) & 0xf]);
1078
1079                         /* CoreSight component? */
1080                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1081                                 uint32_t devtype;
1082                                 unsigned minor;
1083                                 const char *major = "Reserved", *subtype = "Reserved";
1084
1085                                 retval = mem_ap_sel_read_atomic_u32(ap,
1086                                                 (component_base & 0xfffff000) | 0xfcc,
1087                                                 &devtype);
1088                                 if (retval != ERROR_OK)
1089                                         return retval;
1090                                 minor = (devtype >> 4) & 0x0f;
1091                                 switch (devtype & 0x0f) {
1092                                 case 0:
1093                                         major = "Miscellaneous";
1094                                         switch (minor) {
1095                                         case 0:
1096                                                 subtype = "other";
1097                                                 break;
1098                                         case 4:
1099                                                 subtype = "Validation component";
1100                                                 break;
1101                                         }
1102                                         break;
1103                                 case 1:
1104                                         major = "Trace Sink";
1105                                         switch (minor) {
1106                                         case 0:
1107                                                 subtype = "other";
1108                                                 break;
1109                                         case 1:
1110                                                 subtype = "Port";
1111                                                 break;
1112                                         case 2:
1113                                                 subtype = "Buffer";
1114                                                 break;
1115                                         case 3:
1116                                                 subtype = "Router";
1117                                                 break;
1118                                         }
1119                                         break;
1120                                 case 2:
1121                                         major = "Trace Link";
1122                                         switch (minor) {
1123                                         case 0:
1124                                                 subtype = "other";
1125                                                 break;
1126                                         case 1:
1127                                                 subtype = "Funnel, router";
1128                                                 break;
1129                                         case 2:
1130                                                 subtype = "Filter";
1131                                                 break;
1132                                         case 3:
1133                                                 subtype = "FIFO, buffer";
1134                                                 break;
1135                                         }
1136                                         break;
1137                                 case 3:
1138                                         major = "Trace Source";
1139                                         switch (minor) {
1140                                         case 0:
1141                                                 subtype = "other";
1142                                                 break;
1143                                         case 1:
1144                                                 subtype = "Processor";
1145                                                 break;
1146                                         case 2:
1147                                                 subtype = "DSP";
1148                                                 break;
1149                                         case 3:
1150                                                 subtype = "Engine/Coprocessor";
1151                                                 break;
1152                                         case 4:
1153                                                 subtype = "Bus";
1154                                                 break;
1155                                         case 6:
1156                                                 subtype = "Software";
1157                                                 break;
1158                                         }
1159                                         break;
1160                                 case 4:
1161                                         major = "Debug Control";
1162                                         switch (minor) {
1163                                         case 0:
1164                                                 subtype = "other";
1165                                                 break;
1166                                         case 1:
1167                                                 subtype = "Trigger Matrix";
1168                                                 break;
1169                                         case 2:
1170                                                 subtype = "Debug Auth";
1171                                                 break;
1172                                         case 3:
1173                                                 subtype = "Power Requestor";
1174                                                 break;
1175                                         }
1176                                         break;
1177                                 case 5:
1178                                         major = "Debug Logic";
1179                                         switch (minor) {
1180                                         case 0:
1181                                                 subtype = "other";
1182                                                 break;
1183                                         case 1:
1184                                                 subtype = "Processor";
1185                                                 break;
1186                                         case 2:
1187                                                 subtype = "DSP";
1188                                                 break;
1189                                         case 3:
1190                                                 subtype = "Engine/Coprocessor";
1191                                                 break;
1192                                         case 4:
1193                                                 subtype = "Bus";
1194                                                 break;
1195                                         case 5:
1196                                                 subtype = "Memory";
1197                                                 break;
1198                                         }
1199                                         break;
1200                                 case 6:
1201                                         major = "Perfomance Monitor";
1202                                         switch (minor) {
1203                                         case 0:
1204                                                 subtype = "other";
1205                                                 break;
1206                                         case 1:
1207                                                 subtype = "Processor";
1208                                                 break;
1209                                         case 2:
1210                                                 subtype = "DSP";
1211                                                 break;
1212                                         case 3:
1213                                                 subtype = "Engine/Coprocessor";
1214                                                 break;
1215                                         case 4:
1216                                                 subtype = "Bus";
1217                                                 break;
1218                                         case 5:
1219                                                 subtype = "Memory";
1220                                                 break;
1221                                         }
1222                                         break;
1223                                 }
1224                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1225                                                 (uint8_t)(devtype & 0xff),
1226                                                 major, subtype);
1227                                 /* REVISIT also show 0xfc8 DevId */
1228                         }
1229
1230                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1231                                 command_print(cmd_ctx,
1232                                                 "\t\tCID3 0%02x"
1233                                                 ", CID2 0%02x"
1234                                                 ", CID1 0%02x"
1235                                                 ", CID0 0%02x",
1236                                                 (int)c_cid3,
1237                                                 (int)c_cid2,
1238                                                 (int)c_cid1,
1239                                                 (int)c_cid0);
1240                         command_print(cmd_ctx,
1241                                 "\t\tPeripheral ID[4..0] = hex "
1242                                 "%02x %02x %02x %02x %02x",
1243                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1244                                 (int)c_pid1, (int)c_pid0);
1245
1246                         /* Part number interpretations are from Cortex
1247                          * core specs, the CoreSight components TRM
1248                          * (ARM DDI 0314H), CoreSight System Design
1249                          * Guide (ARM DGI 0012D) and ETM specs; also
1250                          * from chip observation (e.g. TI SDTI).
1251                          */
1252                         part_num = (c_pid0 & 0xff);
1253                         part_num |= (c_pid1 & 0x0f) << 8;
1254                         switch (part_num) {
1255                         case 0x000:
1256                                 type = "Cortex-M3 NVIC";
1257                                 full = "(Interrupt Controller)";
1258                                 break;
1259                         case 0x001:
1260                                 type = "Cortex-M3 ITM";
1261                                 full = "(Instrumentation Trace Module)";
1262                                 break;
1263                         case 0x002:
1264                                 type = "Cortex-M3 DWT";
1265                                 full = "(Data Watchpoint and Trace)";
1266                                 break;
1267                         case 0x003:
1268                                 type = "Cortex-M3 FBP";
1269                                 full = "(Flash Patch and Breakpoint)";
1270                                 break;
1271                         case 0x008:
1272                                 type = "Cortex-M0 SCS";
1273                                 full = "(System Control Space)";
1274                                 break;
1275                         case 0x00a:
1276                                 type = "Cortex-M0 DWT";
1277                                 full = "(Data Watchpoint and Trace)";
1278                                 break;
1279                         case 0x00b:
1280                                 type = "Cortex-M0 BPU";
1281                                 full = "(Breakpoint Unit)";
1282                                 break;
1283                         case 0x00c:
1284                                 type = "Cortex-M4 SCS";
1285                                 full = "(System Control Space)";
1286                                 break;
1287                         case 0x00d:
1288                                 type = "CoreSight ETM11";
1289                                 full = "(Embedded Trace)";
1290                                 break;
1291                         /* case 0x113: what? */
1292                         case 0x120:             /* from OMAP3 memmap */
1293                                 type = "TI SDTI";
1294                                 full = "(System Debug Trace Interface)";
1295                                 break;
1296                         case 0x343:             /* from OMAP3 memmap */
1297                                 type = "TI DAPCTL";
1298                                 full = "";
1299                                 break;
1300                         case 0x906:
1301                                 type = "Coresight CTI";
1302                                 full = "(Cross Trigger)";
1303                                 break;
1304                         case 0x907:
1305                                 type = "Coresight ETB";
1306                                 full = "(Trace Buffer)";
1307                                 break;
1308                         case 0x908:
1309                                 type = "Coresight CSTF";
1310                                 full = "(Trace Funnel)";
1311                                 break;
1312                         case 0x910:
1313                                 type = "CoreSight ETM9";
1314                                 full = "(Embedded Trace)";
1315                                 break;
1316                         case 0x912:
1317                                 type = "Coresight TPIU";
1318                                 full = "(Trace Port Interface Unit)";
1319                                 break;
1320                         case 0x913:
1321                                 type = "Coresight ITM";
1322                                 full = "(Instrumentation Trace Macrocell)";
1323                                 break;
1324                         case 0x914:
1325                                 type = "Coresight SWO";
1326                                 full = "(Single Wire Output)";
1327                                 break;
1328                         case 0x917:
1329                                 type = "Coresight HTM";
1330                                 full = "(AHB Trace Macrocell)";
1331                                 break;
1332                         case 0x920:
1333                                 type = "CoreSight ETM11";
1334                                 full = "(Embedded Trace)";
1335                                 break;
1336                         case 0x921:
1337                                 type = "Cortex-A8 ETM";
1338                                 full = "(Embedded Trace)";
1339                                 break;
1340                         case 0x922:
1341                                 type = "Cortex-A8 CTI";
1342                                 full = "(Cross Trigger)";
1343                                 break;
1344                         case 0x923:
1345                                 type = "Cortex-M3 TPIU";
1346                                 full = "(Trace Port Interface Unit)";
1347                                 break;
1348                         case 0x924:
1349                                 type = "Cortex-M3 ETM";
1350                                 full = "(Embedded Trace)";
1351                                 break;
1352                         case 0x925:
1353                                 type = "Cortex-M4 ETM";
1354                                 full = "(Embedded Trace)";
1355                                 break;
1356                         case 0x930:
1357                                 type = "Cortex-R4 ETM";
1358                                 full = "(Embedded Trace)";
1359                                 break;
1360                         case 0x950:
1361                                 type = "CoreSight Component";
1362                                 full = "(unidentified Cortex-A9 component)";
1363                                 break;
1364                         case 0x961:
1365                                 type = "CoreSight TMC";
1366                                 full = "(Trace Memory Controller)";
1367                                 break;
1368                         case 0x962:
1369                                 type = "CoreSight STM";
1370                                 full = "(System Trace Macrocell)";
1371                                 break;
1372                         case 0x9a0:
1373                                 type = "CoreSight PMU";
1374                                 full = "(Performance Monitoring Unit)";
1375                                 break;
1376                         case 0x9a1:
1377                                 type = "Cortex-M4 TPUI";
1378                                 full = "(Trace Port Interface Unit)";
1379                                 break;
1380                         case 0x9a5:
1381                                 type = "Cortex-A5 ETM";
1382                                 full = "(Embedded Trace)";
1383                                 break;
1384                         case 0xc05:
1385                                 type = "Cortex-A5 Debug";
1386                                 full = "(Debug Unit)";
1387                                 break;
1388                         case 0xc08:
1389                                 type = "Cortex-A8 Debug";
1390                                 full = "(Debug Unit)";
1391                                 break;
1392                         case 0xc09:
1393                                 type = "Cortex-A9 Debug";
1394                                 full = "(Debug Unit)";
1395                                 break;
1396                         case 0x4af:
1397                                 type = "Cortex-A15 Debug";
1398                                 full = "(Debug Unit)";
1399                                 break;
1400                         default:
1401                                 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1402                                 type = "-*- unrecognized -*-";
1403                                 full = "";
1404                                 break;
1405                         }
1406                         command_print(cmd_ctx, "\t\tPart is %s %s",
1407                                         type, full);
1408
1409                         /* ROM Table? */
1410                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1411                                 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1412                                 if (retval != ERROR_OK)
1413                                         return retval;
1414                         }
1415                 } else {
1416                         if (romentry)
1417                                 command_print(cmd_ctx, "\t\tComponent not present");
1418                         else
1419                                 break;
1420                 }
1421         }
1422         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1423         return ERROR_OK;
1424 }
1425
1426 static int dap_info_command(struct command_context *cmd_ctx,
1427                 struct adiv5_ap *ap)
1428 {
1429         int retval;
1430         uint32_t dbgbase, apid;
1431         int romtable_present = 0;
1432         uint8_t mem_ap;
1433
1434         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1435         retval = dap_get_debugbase(ap, &dbgbase, &apid);
1436         if (retval != ERROR_OK)
1437                 return retval;
1438
1439         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1440         if (apid == 0) {
1441                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1442                 return ERROR_FAIL;
1443         }
1444
1445         switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1446         case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1447                 command_print(cmd_ctx, "\tType is JTAG-AP");
1448                 break;
1449         case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1450                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1451                 break;
1452         case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1453                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1454                 break;
1455         case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1456                 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1457                 break;
1458         default:
1459                 command_print(cmd_ctx, "\tUnknown AP type");
1460                 break;
1461         }
1462
1463         /* NOTE: a MEM-AP may have a single CoreSight component that's
1464          * not a ROM table ... or have no such components at all.
1465          */
1466         mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1467         if (mem_ap) {
1468                 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1469
1470                 romtable_present = dbgbase != 0xFFFFFFFF;
1471                 if (romtable_present)
1472                         dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1473                 else
1474                         command_print(cmd_ctx, "\tNo ROM table present");
1475         }
1476
1477         return ERROR_OK;
1478 }
1479
1480 COMMAND_HANDLER(handle_dap_info_command)
1481 {
1482         struct target *target = get_current_target(CMD_CTX);
1483         struct arm *arm = target_to_arm(target);
1484         struct adiv5_dap *dap = arm->dap;
1485         uint32_t apsel;
1486
1487         switch (CMD_ARGC) {
1488         case 0:
1489                 apsel = dap->apsel;
1490                 break;
1491         case 1:
1492                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1493                 if (apsel >= 256)
1494                         return ERROR_COMMAND_SYNTAX_ERROR;
1495                 break;
1496         default:
1497                 return ERROR_COMMAND_SYNTAX_ERROR;
1498         }
1499
1500         return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1501 }
1502
1503 COMMAND_HANDLER(dap_baseaddr_command)
1504 {
1505         struct target *target = get_current_target(CMD_CTX);
1506         struct arm *arm = target_to_arm(target);
1507         struct adiv5_dap *dap = arm->dap;
1508
1509         uint32_t apsel, baseaddr;
1510         int retval;
1511
1512         switch (CMD_ARGC) {
1513         case 0:
1514                 apsel = dap->apsel;
1515                 break;
1516         case 1:
1517                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1518                 /* AP address is in bits 31:24 of DP_SELECT */
1519                 if (apsel >= 256)
1520                         return ERROR_COMMAND_SYNTAX_ERROR;
1521                 break;
1522         default:
1523                 return ERROR_COMMAND_SYNTAX_ERROR;
1524         }
1525
1526         dap_ap_select(dap, apsel);
1527
1528         /* NOTE:  assumes we're talking to a MEM-AP, which
1529          * has a base address.  There are other kinds of AP,
1530          * though they're not common for now.  This should
1531          * use the ID register to verify it's a MEM-AP.
1532          */
1533         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1534         if (retval != ERROR_OK)
1535                 return retval;
1536         retval = dap_run(dap);
1537         if (retval != ERROR_OK)
1538                 return retval;
1539
1540         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1541
1542         return retval;
1543 }
1544
1545 COMMAND_HANDLER(dap_memaccess_command)
1546 {
1547         struct target *target = get_current_target(CMD_CTX);
1548         struct arm *arm = target_to_arm(target);
1549         struct adiv5_dap *dap = arm->dap;
1550
1551         uint32_t memaccess_tck;
1552
1553         switch (CMD_ARGC) {
1554         case 0:
1555                 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1556                 break;
1557         case 1:
1558                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1559                 break;
1560         default:
1561                 return ERROR_COMMAND_SYNTAX_ERROR;
1562         }
1563         dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1564
1565         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1566                         dap->ap[dap->apsel].memaccess_tck);
1567
1568         return ERROR_OK;
1569 }
1570
1571 COMMAND_HANDLER(dap_apsel_command)
1572 {
1573         struct target *target = get_current_target(CMD_CTX);
1574         struct arm *arm = target_to_arm(target);
1575         struct adiv5_dap *dap = arm->dap;
1576
1577         uint32_t apsel, apid;
1578         int retval;
1579
1580         switch (CMD_ARGC) {
1581         case 0:
1582                 apsel = 0;
1583                 break;
1584         case 1:
1585                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1586                 /* AP address is in bits 31:24 of DP_SELECT */
1587                 if (apsel >= 256)
1588                         return ERROR_COMMAND_SYNTAX_ERROR;
1589                 break;
1590         default:
1591                 return ERROR_COMMAND_SYNTAX_ERROR;
1592         }
1593
1594         dap->apsel = apsel;
1595         dap_ap_select(dap, apsel);
1596
1597         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1598         if (retval != ERROR_OK)
1599                 return retval;
1600         retval = dap_run(dap);
1601         if (retval != ERROR_OK)
1602                 return retval;
1603
1604         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1605                         apsel, apid);
1606
1607         return retval;
1608 }
1609
1610 COMMAND_HANDLER(dap_apcsw_command)
1611 {
1612         struct target *target = get_current_target(CMD_CTX);
1613         struct arm *arm = target_to_arm(target);
1614         struct adiv5_dap *dap = arm->dap;
1615
1616         uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1617
1618         switch (CMD_ARGC) {
1619         case 0:
1620                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1621                         (dap->apsel), apcsw);
1622                 break;
1623         case 1:
1624                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1625                 /* AP address is in bits 31:24 of DP_SELECT */
1626                 if (sprot > 1)
1627                         return ERROR_COMMAND_SYNTAX_ERROR;
1628                 if (sprot)
1629                         apcsw |= CSW_SPROT;
1630                 else
1631                         apcsw &= ~CSW_SPROT;
1632                 break;
1633         default:
1634                 return ERROR_COMMAND_SYNTAX_ERROR;
1635         }
1636         dap->ap[dap->apsel].csw_default = apcsw;
1637
1638         return 0;
1639 }
1640
1641
1642
1643 COMMAND_HANDLER(dap_apid_command)
1644 {
1645         struct target *target = get_current_target(CMD_CTX);
1646         struct arm *arm = target_to_arm(target);
1647         struct adiv5_dap *dap = arm->dap;
1648
1649         uint32_t apsel, apid;
1650         int retval;
1651
1652         switch (CMD_ARGC) {
1653         case 0:
1654                 apsel = dap->apsel;
1655                 break;
1656         case 1:
1657                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1658                 /* AP address is in bits 31:24 of DP_SELECT */
1659                 if (apsel >= 256)
1660                         return ERROR_COMMAND_SYNTAX_ERROR;
1661                 break;
1662         default:
1663                 return ERROR_COMMAND_SYNTAX_ERROR;
1664         }
1665
1666         dap_ap_select(dap, apsel);
1667
1668         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1669         if (retval != ERROR_OK)
1670                 return retval;
1671         retval = dap_run(dap);
1672         if (retval != ERROR_OK)
1673                 return retval;
1674
1675         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1676
1677         return retval;
1678 }
1679
1680 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1681 {
1682         struct target *target = get_current_target(CMD_CTX);
1683         struct arm *arm = target_to_arm(target);
1684         struct adiv5_dap *dap = arm->dap;
1685
1686         uint32_t enable = dap->ti_be_32_quirks;
1687
1688         switch (CMD_ARGC) {
1689         case 0:
1690                 break;
1691         case 1:
1692                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1693                 if (enable > 1)
1694                         return ERROR_COMMAND_SYNTAX_ERROR;
1695                 break;
1696         default:
1697                 return ERROR_COMMAND_SYNTAX_ERROR;
1698         }
1699         dap->ti_be_32_quirks = enable;
1700         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1701                 enable ? "enabled" : "disabled");
1702
1703         return 0;
1704 }
1705
1706 static const struct command_registration dap_commands[] = {
1707         {
1708                 .name = "info",
1709                 .handler = handle_dap_info_command,
1710                 .mode = COMMAND_EXEC,
1711                 .help = "display ROM table for MEM-AP "
1712                         "(default currently selected AP)",
1713                 .usage = "[ap_num]",
1714         },
1715         {
1716                 .name = "apsel",
1717                 .handler = dap_apsel_command,
1718                 .mode = COMMAND_EXEC,
1719                 .help = "Set the currently selected AP (default 0) "
1720                         "and display the result",
1721                 .usage = "[ap_num]",
1722         },
1723         {
1724                 .name = "apcsw",
1725                 .handler = dap_apcsw_command,
1726                 .mode = COMMAND_EXEC,
1727                 .help = "Set csw access bit ",
1728                 .usage = "[sprot]",
1729         },
1730
1731         {
1732                 .name = "apid",
1733                 .handler = dap_apid_command,
1734                 .mode = COMMAND_EXEC,
1735                 .help = "return ID register from AP "
1736                         "(default currently selected AP)",
1737                 .usage = "[ap_num]",
1738         },
1739         {
1740                 .name = "baseaddr",
1741                 .handler = dap_baseaddr_command,
1742                 .mode = COMMAND_EXEC,
1743                 .help = "return debug base address from MEM-AP "
1744                         "(default currently selected AP)",
1745                 .usage = "[ap_num]",
1746         },
1747         {
1748                 .name = "memaccess",
1749                 .handler = dap_memaccess_command,
1750                 .mode = COMMAND_EXEC,
1751                 .help = "set/get number of extra tck for MEM-AP memory "
1752                         "bus access [0-255]",
1753                 .usage = "[cycles]",
1754         },
1755         {
1756                 .name = "ti_be_32_quirks",
1757                 .handler = dap_ti_be_32_quirks_command,
1758                 .mode = COMMAND_CONFIG,
1759                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1760                 .usage = "[enable]",
1761         },
1762         COMMAND_REGISTRATION_DONE
1763 };
1764
1765 const struct command_registration dap_command_handlers[] = {
1766         {
1767                 .name = "dap",
1768                 .mode = COMMAND_EXEC,
1769                 .help = "DAP command group",
1770                 .usage = "",
1771                 .chain = dap_commands,
1772         },
1773         COMMAND_REGISTRATION_DONE
1774 };