git.sur5r.net Git - openocd/blob - src/target/arm_adi_v5.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         int retval;
 299
 300         if (size == 4)
 301                 csw_size = CSW_32BIT;
 302         else if (size == 2)
 303                 csw_size = CSW_16BIT;
 304         else if (size == 1)
 305                 csw_size = CSW_8BIT;
 306         else
 307                 return ERROR_TARGET_UNALIGNED_ACCESS;
 308
 309         retval = dap_setup_accessport_tar(dap, address);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         while (nbytes > 0) {
 314                 uint32_t this_size = size;
 315
 316                 /* Select packed transfer if possible */
 317                 if (addrinc && dap->packed_transfers && nbytes >= 4
 318                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 319                         this_size = 4;
 320                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 321                 } else {
 322                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 323                 }
 324
 325                 if (retval != ERROR_OK)
 326                         break;
 327
 328                 /* How many source bytes each transfer will consume, and their location in the DRW,
 329                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 330                 uint32_t outvalue = 0;
 331                 switch (this_size) {
 332                 case 4:
 333                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 334                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 335                 case 2:
 336                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 337                 case 1:
 338                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 339                 }
 340
 341                 nbytes -= this_size;
 342
 343                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 344                 if (retval != ERROR_OK)
 345                         break;
 346
 347                 /* Rewrite TAR if it wrapped */
 348                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 349                         retval = dap_setup_accessport_tar(dap, address);
 350                         if (retval != ERROR_OK)
 351                                 break;
 352                 }
 353         }
 354
 355         /* REVISIT: Might want to have a queued version of this function that does not run. */
 356         if (retval == ERROR_OK)
 357                 retval = dap_run(dap);
 358
 359         if (retval != ERROR_OK) {
 360                 uint32_t tar;
 361                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 362                                 && dap_run(dap) == ERROR_OK)
 363                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 364                 else
 365                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 366         }
 367
 368         return retval;
 369 }
 370
 371 /**
 372  * Synchronous read of a block of memory, using a specific access size.
 373  *
 374  * @param dap The DAP connected to the MEM-AP.
 375  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 376  * @param size Which access size to use, in bytes. 1, 2 or 4.
 377  * @param count The number of reads to do (in size units, not bytes).
 378  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 379  * @param addrinc Whether the target address should be increased after each read or not. This
 380  *  should normally be true, except when reading from e.g. a FIFO.
 381  * @return ERROR_OK on success, otherwise an error code.
 382  */
 383 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 384                 uint32_t adr, bool addrinc)
 385 {
 386         size_t nbytes = size * count;
 387         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 388         uint32_t csw_size;
 389         uint32_t address = adr;
 390         int retval;
 391
 392         if (size == 4)
 393                 csw_size = CSW_32BIT;
 394         else if (size == 2)
 395                 csw_size = CSW_16BIT;
 396         else if (size == 1)
 397                 csw_size = CSW_8BIT;
 398         else
 399                 return ERROR_TARGET_UNALIGNED_ACCESS;
 400
 401         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 402          * over-allocation if packed transfers are going to be used, but determining the real need at
 403          * this point would be messy. */
 404         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 405         uint32_t *read_ptr = read_buf;
 406         if (read_buf == NULL) {
 407                 LOG_ERROR("Failed to allocate read buffer");
 408                 return ERROR_FAIL;
 409         }
 410
 411         retval = dap_setup_accessport_tar(dap, address);
 412         if (retval != ERROR_OK) {
 413                 free(read_buf);
 414                 return retval;
 415         }
 416
 417         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 418          * useful bytes it contains, and their location in the word, depends on the type of transfer
 419          * and alignment. */
 420         while (nbytes > 0) {
 421                 uint32_t this_size = size;
 422
 423                 /* Select packed transfer if possible */
 424                 if (addrinc && dap->packed_transfers && nbytes >= 4
 425                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 426                         this_size = 4;
 427                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 428                 } else {
 429                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 430                 }
 431                 if (retval != ERROR_OK)
 432                         break;
 433
 434                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 435                 if (retval != ERROR_OK)
 436                         break;
 437
 438                 nbytes -= this_size;
 439                 address += this_size;
 440
 441                 /* Rewrite TAR if it wrapped */
 442                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 443                         retval = dap_setup_accessport_tar(dap, address);
 444                         if (retval != ERROR_OK)
 445                                 break;
 446                 }
 447         }
 448
 449         if (retval == ERROR_OK)
 450                 retval = dap_run(dap);
 451
 452         /* Restore state */
 453         address = adr;
 454         nbytes = size * count;
 455         read_ptr = read_buf;
 456
 457         /* If something failed, read TAR to find out how much data was successfully read, so we can
 458          * at least give the caller what we have. */
 459         if (retval != ERROR_OK) {
 460                 uint32_t tar;
 461                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 462                                 && dap_run(dap) == ERROR_OK) {
 463                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 464                         if (nbytes > tar - address)
 465                                 nbytes = tar - address;
 466                 } else {
 467                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 468                         nbytes = 0;
 469                 }
 470         }
 471
 472         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 473         while (nbytes > 0) {
 474                 uint32_t this_size = size;
 475
 476                 if (addrinc && dap->packed_transfers && nbytes >= 4
 477                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 478                         this_size = 4;
 479                 }
 480
 481                 switch (this_size) {
 482                 case 4:
 483                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 484                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 485                 case 2:
 486                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 487                 case 1:
 488                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 489                 }
 490
 491                 read_ptr++;
 492                 nbytes -= this_size;
 493         }
 494
 495         free(read_buf);
 496         return retval;
 497 }
 498
 499 /*--------------------------------------------------------------------*/
 500 /*          Wrapping function with selection of AP                    */
 501 /*--------------------------------------------------------------------*/
 502 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 503                 uint32_t address, uint32_t *value)
 504 {
 505         dap_ap_select(swjdp, ap);
 506         return mem_ap_read_u32(swjdp, address, value);
 507 }
 508
 509 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 510                 uint32_t address, uint32_t value)
 511 {
 512         dap_ap_select(swjdp, ap);
 513         return mem_ap_write_u32(swjdp, address, value);
 514 }
 515
 516 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 517                 uint32_t address, uint32_t *value)
 518 {
 519         dap_ap_select(swjdp, ap);
 520         return mem_ap_read_atomic_u32(swjdp, address, value);
 521 }
 522
 523 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 524                 uint32_t address, uint32_t value)
 525 {
 526         dap_ap_select(swjdp, ap);
 527         return mem_ap_write_atomic_u32(swjdp, address, value);
 528 }
 529
 530 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 531                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 532 {
 533         dap_ap_select(swjdp, ap);
 534         return mem_ap_read(swjdp, buffer, size, count, address, true);
 535 }
 536
 537 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 538                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 539 {
 540         dap_ap_select(swjdp, ap);
 541         return mem_ap_write(swjdp, buffer, size, count, address, true);
 542 }
 543
 544 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 545                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 546 {
 547         dap_ap_select(swjdp, ap);
 548         return mem_ap_read(swjdp, buffer, size, count, address, false);
 549 }
 550
 551 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 552                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 553 {
 554         dap_ap_select(swjdp, ap);
 555         return mem_ap_write(swjdp, buffer, size, count, address, false);
 556 }
 557
 558 #define MDM_REG_STAT            0x00
 559 #define MDM_REG_CTRL            0x04
 560 #define MDM_REG_ID              0xfc
 561
 562 #define MDM_STAT_FMEACK         (1<<0)
 563 #define MDM_STAT_FREADY         (1<<1)
 564 #define MDM_STAT_SYSSEC         (1<<2)
 565 #define MDM_STAT_SYSRES         (1<<3)
 566 #define MDM_STAT_FMEEN          (1<<5)
 567 #define MDM_STAT_BACKDOOREN     (1<<6)
 568 #define MDM_STAT_LPEN           (1<<7)
 569 #define MDM_STAT_VLPEN          (1<<8)
 570 #define MDM_STAT_LLSMODEXIT     (1<<9)
 571 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 572 #define MDM_STAT_CORE_HALTED    (1<<16)
 573 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 574 #define MDM_STAT_CORESLEEPING   (1<<18)
 575
 576 #define MEM_CTRL_FMEIP          (1<<0)
 577 #define MEM_CTRL_DBG_DIS        (1<<1)
 578 #define MEM_CTRL_DBG_REQ        (1<<2)
 579 #define MEM_CTRL_SYS_RES_REQ    (1<<3)
 580 #define MEM_CTRL_CORE_HOLD_RES  (1<<4)
 581 #define MEM_CTRL_VLLSX_DBG_REQ  (1<<5)
 582 #define MEM_CTRL_VLLSX_DBG_ACK  (1<<6)
 583 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
 584
 585 #define MDM_ACCESS_TIMEOUT      3000 /* ms */
 586
 587 /**
 588  *
 589  */
 590 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
 591 {
 592         uint32_t val;
 593         int retval;
 594         int timeout = 0;
 595         enum reset_types jtag_reset_config = jtag_get_reset_config();
 596
 597         dap_ap_select(dap, 1);
 598
 599         /* first check mdm-ap id register */
 600         retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
 601         if (retval != ERROR_OK)
 602                 return retval;
 603         dap_run(dap);
 604
 605         if (val != 0x001C0000) {
 606                 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
 607                 dap_ap_select(dap, 0);
 608                 return ERROR_FAIL;
 609         }
 610
 611         /* read and parse status register
 612          * it's important that the device is out of
 613          * reset here
 614          */
 615         while (1) {
 616                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 617                         LOG_DEBUG("MDMAP : flash ready timeout");
 618                         return ERROR_FAIL;
 619                 }
 620                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 621                 if (retval != ERROR_OK)
 622                         return retval;
 623                 dap_run(dap);
 624
 625                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 626                 if (val & MDM_STAT_FREADY)
 627                         break;
 628                 alive_sleep(1);
 629         }
 630
 631         if ((val & MDM_STAT_SYSSEC)) {
 632                 LOG_DEBUG("MDMAP: system is secured, masserase needed");
 633
 634                 if (!(val & MDM_STAT_FMEEN))
 635                         LOG_DEBUG("MDMAP: masserase is disabled");
 636                 else {
 637                         /* we need to assert reset */
 638                         if (jtag_reset_config & RESET_HAS_SRST) {
 639                                 /* default to asserting srst */
 640                                 adapter_assert_reset();
 641                         } else {
 642                                 LOG_DEBUG("SRST not configured");
 643                                 dap_ap_select(dap, 0);
 644                                 return ERROR_FAIL;
 645                         }
 646                         timeout = 0;
 647                         while (1) {
 648                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 649                                         LOG_DEBUG("MDMAP : flash ready timeout");
 650                                         return ERROR_FAIL;
 651                                 }
 652                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
 653                                 if (retval != ERROR_OK)
 654                                         return retval;
 655                                 dap_run(dap);
 656                                 /* read status register and wait for ready */
 657                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 658                                 if (retval != ERROR_OK)
 659                                         return retval;
 660                                 dap_run(dap);
 661                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 662
 663                                 if ((val & 1))
 664                                         break;
 665                                 alive_sleep(1);
 666                         }
 667                         timeout = 0;
 668                         while (1) {
 669                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 670                                         LOG_DEBUG("MDMAP : flash ready timeout");
 671                                         return ERROR_FAIL;
 672                                 }
 673                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
 674                                 if (retval != ERROR_OK)
 675                                         return retval;
 676                                 dap_run(dap);
 677                                 /* read status register */
 678                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 679                                 if (retval != ERROR_OK)
 680                                         return retval;
 681                                 dap_run(dap);
 682                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 683                                 /* read control register and wait for ready */
 684                                 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
 685                                 if (retval != ERROR_OK)
 686                                         return retval;
 687                                 dap_run(dap);
 688                                 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
 689
 690                                 if (val == 0x00)
 691                                         break;
 692                                 alive_sleep(1);
 693                         }
 694                 }
 695         }
 696
 697         dap_ap_select(dap, 0);
 698
 699         return ERROR_OK;
 700 }
 701
 702 /** */
 703 struct dap_syssec_filter {
 704         /** */
 705         uint32_t idcode;
 706         /** */
 707         int (*dap_init)(struct adiv5_dap *dap);
 708 };
 709
 710 /** */
 711 static struct dap_syssec_filter dap_syssec_filter_data[] = {
 712         { 0x4BA00477, dap_syssec_kinetis_mdmap }
 713 };
 714
 715 /**
 716  *
 717  */
 718 int dap_syssec(struct adiv5_dap *dap)
 719 {
 720         unsigned int i;
 721         struct jtag_tap *tap;
 722
 723         for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
 724                 tap = dap->jtag_info->tap;
 725
 726                 while (tap != NULL) {
 727                         if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
 728                                 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
 729                                 dap_syssec_filter_data[i].dap_init(dap);
 730                         }
 731                         tap = tap->next_tap;
 732                 }
 733         }
 734
 735         return ERROR_OK;
 736 }
 737
 738 /*--------------------------------------------------------------------------*/
 739
 740
 741 /* FIXME don't import ... just initialize as
 742  * part of DAP transport setup
 743 */
 744 extern const struct dap_ops jtag_dp_ops;
 745
 746 /*--------------------------------------------------------------------------*/
 747
 748 /**
 749  * Initialize a DAP.  This sets up the power domains, prepares the DP
 750  * for further use, and arranges to use AP #0 for all AP operations
 751  * until dap_ap-select() changes that policy.
 752  *
 753  * @param dap The DAP being initialized.
 754  *
 755  * @todo Rename this.  We also need an initialization scheme which account
 756  * for SWD transports not just JTAG; that will need to address differences
 757  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 758  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 759  */
 760 int ahbap_debugport_init(struct adiv5_dap *dap)
 761 {
 762         uint32_t ctrlstat;
 763         int cnt = 0;
 764         int retval;
 765
 766         LOG_DEBUG(" ");
 767
 768         /* JTAG-DP or SWJ-DP, in JTAG mode
 769          * ... for SWD mode this is patched as part
 770          * of link switchover
 771          */
 772         if (!dap->ops)
 773                 dap->ops = &jtag_dp_ops;
 774
 775         /* Default MEM-AP setup.
 776          *
 777          * REVISIT AP #0 may be an inappropriate default for this.
 778          * Should we probe, or take a hint from the caller?
 779          * Presumably we can ignore the possibility of multiple APs.
 780          */
 781         dap->ap_current = !0;
 782         dap_ap_select(dap, 0);
 783
 784         /* DP initialization */
 785
 786         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 787         if (retval != ERROR_OK)
 788                 return retval;
 789
 790         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 791         if (retval != ERROR_OK)
 792                 return retval;
 793
 794         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 795         if (retval != ERROR_OK)
 796                 return retval;
 797
 798         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 799         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 800         if (retval != ERROR_OK)
 801                 return retval;
 802
 803         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 804         if (retval != ERROR_OK)
 805                 return retval;
 806         retval = dap_run(dap);
 807         if (retval != ERROR_OK)
 808                 return retval;
 809
 810         /* Check that we have debug power domains activated */
 811         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
 812                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 813                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 814                 if (retval != ERROR_OK)
 815                         return retval;
 816                 retval = dap_run(dap);
 817                 if (retval != ERROR_OK)
 818                         return retval;
 819                 alive_sleep(10);
 820         }
 821
 822         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
 823                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 824                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 825                 if (retval != ERROR_OK)
 826                         return retval;
 827                 retval = dap_run(dap);
 828                 if (retval != ERROR_OK)
 829                         return retval;
 830                 alive_sleep(10);
 831         }
 832
 833         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 834         if (retval != ERROR_OK)
 835                 return retval;
 836         /* With debug power on we can activate OVERRUN checking */
 837         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 838         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 839         if (retval != ERROR_OK)
 840                 return retval;
 841         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 842         if (retval != ERROR_OK)
 843                 return retval;
 844
 845         dap_syssec(dap);
 846
 847         /* check that we support packed transfers */
 848         uint32_t csw;
 849
 850         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 851         if (retval != ERROR_OK)
 852                 return retval;
 853
 854         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 855         if (retval != ERROR_OK)
 856                 return retval;
 857
 858         retval = dap_run(dap);
 859         if (retval != ERROR_OK)
 860                 return retval;
 861
 862         if (csw & CSW_ADDRINC_PACKED)
 863                 dap->packed_transfers = true;
 864         else
 865                 dap->packed_transfers = false;
 866
 867         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 868                         dap->packed_transfers ? "enabled" : "disabled");
 869
 870         return ERROR_OK;
 871 }
 872
 873 /* CID interpretation -- see ARM IHI 0029B section 3
 874  * and ARM IHI 0031A table 13-3.
 875  */
 876 static const char *class_description[16] = {
 877         "Reserved", "ROM table", "Reserved", "Reserved",
 878         "Reserved", "Reserved", "Reserved", "Reserved",
 879         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 880         "Reserved", "OptimoDE DESS",
 881         "Generic IP component", "PrimeCell or System component"
 882 };
 883
 884 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 885 {
 886         return cid3 == 0xb1 && cid2 == 0x05
 887                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 888 }
 889
 890 /*
 891  * This function checks the ID for each access port to find the requested Access Port type
 892  */
 893 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 894 {
 895         int ap;
 896
 897         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 898         for (ap = 0; ap <= 255; ap++) {
 899
 900                 /* read the IDR register of the Access Port */
 901                 uint32_t id_val = 0;
 902                 dap_ap_select(dap, ap);
 903
 904                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 905                 if (retval != ERROR_OK)
 906                         return retval;
 907
 908                 retval = dap_run(dap);
 909
 910                 /* IDR bits:
 911                  * 31-28 : Revision
 912                  * 27-24 : JEDEC bank (0x4 for ARM)
 913                  * 23-17 : JEDEC code (0x3B for ARM)
 914                  * 16    : Mem-AP
 915                  * 15-8  : Reserved
 916                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 917                  */
 918
 919                 /* Reading register for a non-existant AP should not cause an error,
 920                  * but just to be sure, try to continue searching if an error does happen.
 921                  */
 922                 if ((retval == ERROR_OK) &&                  /* Register read success */
 923                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 924                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 925
 926                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 927                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 928                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 929                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 930                                                 ap, id_val);
 931
 932                         *ap_num_out = ap;
 933                         return ERROR_OK;
 934                 }
 935         }
 936
 937         LOG_DEBUG("No %s found",
 938                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 939                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 940                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 941         return ERROR_FAIL;
 942 }
 943
 944 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 945                         uint32_t *out_dbgbase, uint32_t *out_apid)
 946 {
 947         uint32_t ap_old;
 948         int retval;
 949         uint32_t dbgbase, apid;
 950
 951         /* AP address is in bits 31:24 of DP_SELECT */
 952         if (ap >= 256)
 953                 return ERROR_COMMAND_SYNTAX_ERROR;
 954
 955         ap_old = dap->ap_current;
 956         dap_ap_select(dap, ap);
 957
 958         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
 962         if (retval != ERROR_OK)
 963                 return retval;
 964         retval = dap_run(dap);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967
 968         /* Excavate the device ID code */
 969         struct jtag_tap *tap = dap->jtag_info->tap;
 970         while (tap != NULL) {
 971                 if (tap->hasidcode)
 972                         break;
 973                 tap = tap->next_tap;
 974         }
 975         if (tap == NULL || !tap->hasidcode)
 976                 return ERROR_OK;
 977
 978         dap_ap_select(dap, ap_old);
 979
 980         /* The asignment happens only here to prevent modification of these
 981          * values before they are certain. */
 982         *out_dbgbase = dbgbase;
 983         *out_apid = apid;
 984
 985         return ERROR_OK;
 986 }
 987
 988 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 989                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
 990 {
 991         uint32_t ap_old;
 992         uint32_t romentry, entry_offset = 0, component_base, devtype;
 993         int retval = ERROR_FAIL;
 994
 995         if (ap >= 256)
 996                 return ERROR_COMMAND_SYNTAX_ERROR;
 997
 998         ap_old = dap->ap_current;
 999         dap_ap_select(dap, ap);
1000
1001         do {
1002                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1003                                                 entry_offset, &romentry);
1004                 if (retval != ERROR_OK)
1005                         return retval;
1006
1007                 component_base = (dbgbase & 0xFFFFF000)
1008                         + (romentry & 0xFFFFF000);
1009
1010                 if (romentry & 0x1) {
1011                         retval = mem_ap_read_atomic_u32(dap,
1012                                         (component_base & 0xfffff000) | 0xfcc,
1013                                         &devtype);
1014                         if (retval != ERROR_OK)
1015                                 return retval;
1016                         if ((devtype & 0xff) == type) {
1017                                 *addr = component_base;
1018                                 retval = ERROR_OK;
1019                                 break;
1020                         }
1021                 }
1022                 entry_offset += 4;
1023         } while (romentry > 0);
1024
1025         dap_ap_select(dap, ap_old);
1026
1027         return retval;
1028 }
1029
1030 static int dap_rom_display(struct command_context *cmd_ctx,
1031                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
1032 {
1033         int retval;
1034         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1035         uint16_t entry_offset;
1036         char tabs[7] = "";
1037
1038         if (depth > 16) {
1039                 command_print(cmd_ctx, "\tTables too deep");
1040                 return ERROR_FAIL;
1041         }
1042
1043         if (depth)
1044                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1045
1046         /* bit 16 of apid indicates a memory access port */
1047         if (dbgbase & 0x02)
1048                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
1049         else
1050                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
1051
1052         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1053         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1054         if (retval != ERROR_OK)
1055                 return retval;
1056         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1057         if (retval != ERROR_OK)
1058                 return retval;
1059         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1060         if (retval != ERROR_OK)
1061                 return retval;
1062         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1063         if (retval != ERROR_OK)
1064                 return retval;
1065         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1066         if (retval != ERROR_OK)
1067                 return retval;
1068         retval = dap_run(dap);
1069         if (retval != ERROR_OK)
1070                 return retval;
1071
1072         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1073                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1074                                 ", CID2 0x%02x"
1075                                 ", CID1 0x%02x"
1076                                 ", CID0 0x%02x",
1077                                 tabs,
1078                                 (unsigned)cid3, (unsigned)cid2,
1079                                 (unsigned)cid1, (unsigned)cid0);
1080         if (memtype & 0x01)
1081                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1082         else
1083                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1084
1085         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1086         for (entry_offset = 0; ; entry_offset += 4) {
1087                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1088                 if (retval != ERROR_OK)
1089                         return retval;
1090                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1091                                 tabs, entry_offset, romentry);
1092                 if (romentry & 0x01) {
1093                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1094                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1095                         uint32_t component_base;
1096                         unsigned part_num;
1097                         char *type, *full;
1098
1099                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1100
1101                         /* IDs are in last 4K section */
1102                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1103                         if (retval != ERROR_OK) {
1104                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1105                                               ", the corresponding core might be turned off", tabs, component_base);
1106                                 continue;
1107                         }
1108                         c_pid0 &= 0xff;
1109                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1110                         if (retval != ERROR_OK)
1111                                 return retval;
1112                         c_pid1 &= 0xff;
1113                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1114                         if (retval != ERROR_OK)
1115                                 return retval;
1116                         c_pid2 &= 0xff;
1117                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1118                         if (retval != ERROR_OK)
1119                                 return retval;
1120                         c_pid3 &= 0xff;
1121                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1122                         if (retval != ERROR_OK)
1123                                 return retval;
1124                         c_pid4 &= 0xff;
1125
1126                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1127                         if (retval != ERROR_OK)
1128                                 return retval;
1129                         c_cid0 &= 0xff;
1130                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1131                         if (retval != ERROR_OK)
1132                                 return retval;
1133                         c_cid1 &= 0xff;
1134                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1135                         if (retval != ERROR_OK)
1136                                 return retval;
1137                         c_cid2 &= 0xff;
1138                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1139                         if (retval != ERROR_OK)
1140                                 return retval;
1141                         c_cid3 &= 0xff;
1142
1143                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1144                                       "start address 0x%" PRIx32, component_base,
1145                                       /* component may take multiple 4K pages */
1146                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1147                         command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1148                                         (c_cid1 >> 4) & 0xf,
1149                                         /* See ARM IHI 0029B Table 3-3 */
1150                                         class_description[(c_cid1 >> 4) & 0xf]);
1151
1152                         /* CoreSight component? */
1153                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1154                                 uint32_t devtype;
1155                                 unsigned minor;
1156                                 char *major = "Reserved", *subtype = "Reserved";
1157
1158                                 retval = mem_ap_read_atomic_u32(dap,
1159                                                 (component_base & 0xfffff000) | 0xfcc,
1160                                                 &devtype);
1161                                 if (retval != ERROR_OK)
1162                                         return retval;
1163                                 minor = (devtype >> 4) & 0x0f;
1164                                 switch (devtype & 0x0f) {
1165                                 case 0:
1166                                         major = "Miscellaneous";
1167                                         switch (minor) {
1168                                         case 0:
1169                                                 subtype = "other";
1170                                                 break;
1171                                         case 4:
1172                                                 subtype = "Validation component";
1173                                                 break;
1174                                         }
1175                                         break;
1176                                 case 1:
1177                                         major = "Trace Sink";
1178                                         switch (minor) {
1179                                         case 0:
1180                                                 subtype = "other";
1181                                                 break;
1182                                         case 1:
1183                                                 subtype = "Port";
1184                                                 break;
1185                                         case 2:
1186                                                 subtype = "Buffer";
1187                                                 break;
1188                                         }
1189                                         break;
1190                                 case 2:
1191                                         major = "Trace Link";
1192                                         switch (minor) {
1193                                         case 0:
1194                                                 subtype = "other";
1195                                                 break;
1196                                         case 1:
1197                                                 subtype = "Funnel, router";
1198                                                 break;
1199                                         case 2:
1200                                                 subtype = "Filter";
1201                                                 break;
1202                                         case 3:
1203                                                 subtype = "FIFO, buffer";
1204                                                 break;
1205                                         }
1206                                         break;
1207                                 case 3:
1208                                         major = "Trace Source";
1209                                         switch (minor) {
1210                                         case 0:
1211                                                 subtype = "other";
1212                                                 break;
1213                                         case 1:
1214                                                 subtype = "Processor";
1215                                                 break;
1216                                         case 2:
1217                                                 subtype = "DSP";
1218                                                 break;
1219                                         case 3:
1220                                                 subtype = "Engine/Coprocessor";
1221                                                 break;
1222                                         case 4:
1223                                                 subtype = "Bus";
1224                                                 break;
1225                                         }
1226                                         break;
1227                                 case 4:
1228                                         major = "Debug Control";
1229                                         switch (minor) {
1230                                         case 0:
1231                                                 subtype = "other";
1232                                                 break;
1233                                         case 1:
1234                                                 subtype = "Trigger Matrix";
1235                                                 break;
1236                                         case 2:
1237                                                 subtype = "Debug Auth";
1238                                                 break;
1239                                         }
1240                                         break;
1241                                 case 5:
1242                                         major = "Debug Logic";
1243                                         switch (minor) {
1244                                         case 0:
1245                                                 subtype = "other";
1246                                                 break;
1247                                         case 1:
1248                                                 subtype = "Processor";
1249                                                 break;
1250                                         case 2:
1251                                                 subtype = "DSP";
1252                                                 break;
1253                                         case 3:
1254                                                 subtype = "Engine/Coprocessor";
1255                                                 break;
1256                                         }
1257                                         break;
1258                                 }
1259                                 command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
1260                                                 devtype & 0xff,
1261                                                 major, subtype);
1262                                 /* REVISIT also show 0xfc8 DevId */
1263                         }
1264
1265                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1266                                 command_print(cmd_ctx,
1267                                                 "\t\tCID3 0%02x"
1268                                                 ", CID2 0%02x"
1269                                                 ", CID1 0%02x"
1270                                                 ", CID0 0%02x",
1271                                                 (int)c_cid3,
1272                                                 (int)c_cid2,
1273                                                 (int)c_cid1,
1274                                                 (int)c_cid0);
1275                         command_print(cmd_ctx,
1276                                 "\t\tPeripheral ID[4..0] = hex "
1277                                 "%02x %02x %02x %02x %02x",
1278                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1279                                 (int)c_pid1, (int)c_pid0);
1280
1281                         /* Part number interpretations are from Cortex
1282                          * core specs, the CoreSight components TRM
1283                          * (ARM DDI 0314H), CoreSight System Design
1284                          * Guide (ARM DGI 0012D) and ETM specs; also
1285                          * from chip observation (e.g. TI SDTI).
1286                          */
1287                         part_num = (c_pid0 & 0xff);
1288                         part_num |= (c_pid1 & 0x0f) << 8;
1289                         switch (part_num) {
1290                         case 0x000:
1291                                 type = "Cortex-M3 NVIC";
1292                                 full = "(Interrupt Controller)";
1293                                 break;
1294                         case 0x001:
1295                                 type = "Cortex-M3 ITM";
1296                                 full = "(Instrumentation Trace Module)";
1297                                 break;
1298                         case 0x002:
1299                                 type = "Cortex-M3 DWT";
1300                                 full = "(Data Watchpoint and Trace)";
1301                                 break;
1302                         case 0x003:
1303                                 type = "Cortex-M3 FBP";
1304                                 full = "(Flash Patch and Breakpoint)";
1305                                 break;
1306                         case 0x00c:
1307                                 type = "Cortex-M4 SCS";
1308                                 full = "(System Control Space)";
1309                                 break;
1310                         case 0x00d:
1311                                 type = "CoreSight ETM11";
1312                                 full = "(Embedded Trace)";
1313                                 break;
1314                         /* case 0x113: what? */
1315                         case 0x120:             /* from OMAP3 memmap */
1316                                 type = "TI SDTI";
1317                                 full = "(System Debug Trace Interface)";
1318                                 break;
1319                         case 0x343:             /* from OMAP3 memmap */
1320                                 type = "TI DAPCTL";
1321                                 full = "";
1322                                 break;
1323                         case 0x906:
1324                                 type = "Coresight CTI";
1325                                 full = "(Cross Trigger)";
1326                                 break;
1327                         case 0x907:
1328                                 type = "Coresight ETB";
1329                                 full = "(Trace Buffer)";
1330                                 break;
1331                         case 0x908:
1332                                 type = "Coresight CSTF";
1333                                 full = "(Trace Funnel)";
1334                                 break;
1335                         case 0x910:
1336                                 type = "CoreSight ETM9";
1337                                 full = "(Embedded Trace)";
1338                                 break;
1339                         case 0x912:
1340                                 type = "Coresight TPIU";
1341                                 full = "(Trace Port Interface Unit)";
1342                                 break;
1343                         case 0x913:
1344                                 type = "Coresight ITM";
1345                                 full = "(Instrumentation Trace Macrocell)";
1346                                 break;
1347                         case 0x921:
1348                                 type = "Cortex-A8 ETM";
1349                                 full = "(Embedded Trace)";
1350                                 break;
1351                         case 0x922:
1352                                 type = "Cortex-A8 CTI";
1353                                 full = "(Cross Trigger)";
1354                                 break;
1355                         case 0x923:
1356                                 type = "Cortex-M3 TPIU";
1357                                 full = "(Trace Port Interface Unit)";
1358                                 break;
1359                         case 0x924:
1360                                 type = "Cortex-M3 ETM";
1361                                 full = "(Embedded Trace)";
1362                                 break;
1363                         case 0x925:
1364                                 type = "Cortex-M4 ETM";
1365                                 full = "(Embedded Trace)";
1366                                 break;
1367                         case 0x930:
1368                                 type = "Cortex-R4 ETM";
1369                                 full = "(Embedded Trace)";
1370                                 break;
1371                         case 0x950:
1372                                 type = "CoreSight Component";
1373                                 full = "(unidentified Cortex-A9 component)";
1374                                 break;
1375                         case 0x9a0:
1376                                 type = "CoreSight PMU";
1377                                 full = "(Performance Monitoring Unit)";
1378                                 break;
1379                         case 0x9a1:
1380                                 type = "Cortex-M4 TPUI";
1381                                 full = "(Trace Port Interface Unit)";
1382                                 break;
1383                         case 0xc08:
1384                                 type = "Cortex-A8 Debug";
1385                                 full = "(Debug Unit)";
1386                                 break;
1387                         case 0xc09:
1388                                 type = "Cortex-A9 Debug";
1389                                 full = "(Debug Unit)";
1390                                 break;
1391                         default:
1392                                 type = "-*- unrecognized -*-";
1393                                 full = "";
1394                                 break;
1395                         }
1396                         command_print(cmd_ctx, "\t\tPart is %s %s",
1397                                         type, full);
1398
1399                         /* ROM Table? */
1400                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1401                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1402                                 if (retval != ERROR_OK)
1403                                         return retval;
1404                         }
1405                 } else {
1406                         if (romentry)
1407                                 command_print(cmd_ctx, "\t\tComponent not present");
1408                         else
1409                                 break;
1410                 }
1411         }
1412         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1413         return ERROR_OK;
1414 }
1415
1416 static int dap_info_command(struct command_context *cmd_ctx,
1417                 struct adiv5_dap *dap, int ap)
1418 {
1419         int retval;
1420         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1421         int romtable_present = 0;
1422         uint8_t mem_ap;
1423         uint32_t ap_old;
1424
1425         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1426         if (retval != ERROR_OK)
1427                 return retval;
1428
1429         ap_old = dap->ap_current;
1430         dap_ap_select(dap, ap);
1431
1432         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1433         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1434         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1435         if (apid) {
1436                 switch (apid&0x0F) {
1437                         case 0:
1438                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1439                                 break;
1440                         case 1:
1441                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1442                                 break;
1443                         case 2:
1444                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1445                                 break;
1446                         default:
1447                                 command_print(cmd_ctx, "\tUnknown AP type");
1448                                 break;
1449                 }
1450
1451                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1452                  * not a ROM table ... or have no such components at all.
1453                  */
1454                 if (mem_ap)
1455                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1456         } else
1457                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1458
1459         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1460         if (romtable_present) {
1461                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1462         } else
1463                 command_print(cmd_ctx, "\tNo ROM table present");
1464         dap_ap_select(dap, ap_old);
1465
1466         return ERROR_OK;
1467 }
1468
1469 COMMAND_HANDLER(handle_dap_info_command)
1470 {
1471         struct target *target = get_current_target(CMD_CTX);
1472         struct arm *arm = target_to_arm(target);
1473         struct adiv5_dap *dap = arm->dap;
1474         uint32_t apsel;
1475
1476         switch (CMD_ARGC) {
1477         case 0:
1478                 apsel = dap->apsel;
1479                 break;
1480         case 1:
1481                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1482                 break;
1483         default:
1484                 return ERROR_COMMAND_SYNTAX_ERROR;
1485         }
1486
1487         return dap_info_command(CMD_CTX, dap, apsel);
1488 }
1489
1490 COMMAND_HANDLER(dap_baseaddr_command)
1491 {
1492         struct target *target = get_current_target(CMD_CTX);
1493         struct arm *arm = target_to_arm(target);
1494         struct adiv5_dap *dap = arm->dap;
1495
1496         uint32_t apsel, baseaddr;
1497         int retval;
1498
1499         switch (CMD_ARGC) {
1500         case 0:
1501                 apsel = dap->apsel;
1502                 break;
1503         case 1:
1504                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1505                 /* AP address is in bits 31:24 of DP_SELECT */
1506                 if (apsel >= 256)
1507                         return ERROR_COMMAND_SYNTAX_ERROR;
1508                 break;
1509         default:
1510                 return ERROR_COMMAND_SYNTAX_ERROR;
1511         }
1512
1513         dap_ap_select(dap, apsel);
1514
1515         /* NOTE:  assumes we're talking to a MEM-AP, which
1516          * has a base address.  There are other kinds of AP,
1517          * though they're not common for now.  This should
1518          * use the ID register to verify it's a MEM-AP.
1519          */
1520         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1521         if (retval != ERROR_OK)
1522                 return retval;
1523         retval = dap_run(dap);
1524         if (retval != ERROR_OK)
1525                 return retval;
1526
1527         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1528
1529         return retval;
1530 }
1531
1532 COMMAND_HANDLER(dap_memaccess_command)
1533 {
1534         struct target *target = get_current_target(CMD_CTX);
1535         struct arm *arm = target_to_arm(target);
1536         struct adiv5_dap *dap = arm->dap;
1537
1538         uint32_t memaccess_tck;
1539
1540         switch (CMD_ARGC) {
1541         case 0:
1542                 memaccess_tck = dap->memaccess_tck;
1543                 break;
1544         case 1:
1545                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1546                 break;
1547         default:
1548                 return ERROR_COMMAND_SYNTAX_ERROR;
1549         }
1550         dap->memaccess_tck = memaccess_tck;
1551
1552         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1553                         dap->memaccess_tck);
1554
1555         return ERROR_OK;
1556 }
1557
1558 COMMAND_HANDLER(dap_apsel_command)
1559 {
1560         struct target *target = get_current_target(CMD_CTX);
1561         struct arm *arm = target_to_arm(target);
1562         struct adiv5_dap *dap = arm->dap;
1563
1564         uint32_t apsel, apid;
1565         int retval;
1566
1567         switch (CMD_ARGC) {
1568         case 0:
1569                 apsel = 0;
1570                 break;
1571         case 1:
1572                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1573                 /* AP address is in bits 31:24 of DP_SELECT */
1574                 if (apsel >= 256)
1575                         return ERROR_COMMAND_SYNTAX_ERROR;
1576                 break;
1577         default:
1578                 return ERROR_COMMAND_SYNTAX_ERROR;
1579         }
1580
1581         dap->apsel = apsel;
1582         dap_ap_select(dap, apsel);
1583
1584         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1585         if (retval != ERROR_OK)
1586                 return retval;
1587         retval = dap_run(dap);
1588         if (retval != ERROR_OK)
1589                 return retval;
1590
1591         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1592                         apsel, apid);
1593
1594         return retval;
1595 }
1596
1597 COMMAND_HANDLER(dap_apcsw_command)
1598 {
1599         struct target *target = get_current_target(CMD_CTX);
1600         struct arm *arm = target_to_arm(target);
1601         struct adiv5_dap *dap = arm->dap;
1602
1603         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1604
1605         switch (CMD_ARGC) {
1606         case 0:
1607                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1608                         (dap->apsel), apcsw);
1609                 break;
1610         case 1:
1611                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1612                 /* AP address is in bits 31:24 of DP_SELECT */
1613                 if (sprot > 1)
1614                         return ERROR_COMMAND_SYNTAX_ERROR;
1615                 if (sprot)
1616                         apcsw |= CSW_SPROT;
1617                 else
1618                         apcsw &= ~CSW_SPROT;
1619                 break;
1620         default:
1621                 return ERROR_COMMAND_SYNTAX_ERROR;
1622         }
1623         dap->apcsw[dap->apsel] = apcsw;
1624
1625         return 0;
1626 }
1627
1628
1629
1630 COMMAND_HANDLER(dap_apid_command)
1631 {
1632         struct target *target = get_current_target(CMD_CTX);
1633         struct arm *arm = target_to_arm(target);
1634         struct adiv5_dap *dap = arm->dap;
1635
1636         uint32_t apsel, apid;
1637         int retval;
1638
1639         switch (CMD_ARGC) {
1640         case 0:
1641                 apsel = dap->apsel;
1642                 break;
1643         case 1:
1644                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1645                 /* AP address is in bits 31:24 of DP_SELECT */
1646                 if (apsel >= 256)
1647                         return ERROR_COMMAND_SYNTAX_ERROR;
1648                 break;
1649         default:
1650                 return ERROR_COMMAND_SYNTAX_ERROR;
1651         }
1652
1653         dap_ap_select(dap, apsel);
1654
1655         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1656         if (retval != ERROR_OK)
1657                 return retval;
1658         retval = dap_run(dap);
1659         if (retval != ERROR_OK)
1660                 return retval;
1661
1662         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1663
1664         return retval;
1665 }
1666
1667 static const struct command_registration dap_commands[] = {
1668         {
1669                 .name = "info",
1670                 .handler = handle_dap_info_command,
1671                 .mode = COMMAND_EXEC,
1672                 .help = "display ROM table for MEM-AP "
1673                         "(default currently selected AP)",
1674                 .usage = "[ap_num]",
1675         },
1676         {
1677                 .name = "apsel",
1678                 .handler = dap_apsel_command,
1679                 .mode = COMMAND_EXEC,
1680                 .help = "Set the currently selected AP (default 0) "
1681                         "and display the result",
1682                 .usage = "[ap_num]",
1683         },
1684         {
1685                 .name = "apcsw",
1686                 .handler = dap_apcsw_command,
1687                 .mode = COMMAND_EXEC,
1688                 .help = "Set csw access bit ",
1689                 .usage = "[sprot]",
1690         },
1691
1692         {
1693                 .name = "apid",
1694                 .handler = dap_apid_command,
1695                 .mode = COMMAND_EXEC,
1696                 .help = "return ID register from AP "
1697                         "(default currently selected AP)",
1698                 .usage = "[ap_num]",
1699         },
1700         {
1701                 .name = "baseaddr",
1702                 .handler = dap_baseaddr_command,
1703                 .mode = COMMAND_EXEC,
1704                 .help = "return debug base address from MEM-AP "
1705                         "(default currently selected AP)",
1706                 .usage = "[ap_num]",
1707         },
1708         {
1709                 .name = "memaccess",
1710                 .handler = dap_memaccess_command,
1711                 .mode = COMMAND_EXEC,
1712                 .help = "set/get number of extra tck for MEM-AP memory "
1713                         "bus access [0-255]",
1714                 .usage = "[cycles]",
1715         },
1716         COMMAND_REGISTRATION_DONE
1717 };
1718
1719 const struct command_registration dap_command_handlers[] = {
1720         {
1721                 .name = "dap",
1722                 .mode = COMMAND_EXEC,
1723                 .help = "DAP command group",
1724                 .usage = "",
1725                 .chain = dap_commands,
1726         },
1727         COMMAND_REGISTRATION_DONE
1728 };