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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116         }
 117 }
 118
 119 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 120 {
 121         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 122                 dap->ap[dap_ap_get_select(dap)].csw_default;
 123
 124         if (csw != dap->ap[dap_ap_get_select(dap)].csw_value) {
 125                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 126                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
 127                 if (retval != ERROR_OK)
 128                         return retval;
 129                 dap->ap[dap_ap_get_select(dap)].csw_value = csw;
 130         }
 131         return ERROR_OK;
 132 }
 133
 134 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 135 {
 136         if (tar != dap->ap[dap_ap_get_select(dap)].tar_value ||
 137                         (dap->ap[dap_ap_get_select(dap)].csw_value & CSW_ADDRINC_MASK)) {
 138                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 139                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
 140                 if (retval != ERROR_OK)
 141                         return retval;
 142                 dap->ap[dap_ap_get_select(dap)].tar_value = tar;
 143         }
 144         return ERROR_OK;
 145 }
 146
 147 /**
 148  * Queue transactions setting up transfer parameters for the
 149  * currently selected MEM-AP.
 150  *
 151  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 152  * initiate data reads or writes using memory or peripheral addresses.
 153  * If the CSW is configured for it, the TAR may be automatically
 154  * incremented after each transfer.
 155  *
 156  * @todo Rename to reflect it being specifically a MEM-AP function.
 157  *
 158  * @param dap The DAP connected to the MEM-AP.
 159  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 160  *      matches the cached value, the register is not changed.
 161  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 162  *      matches the cached address, the register is not changed.
 163  *
 164  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 165  */
 166 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 167 {
 168         int retval;
 169         retval = dap_setup_accessport_csw(dap, csw);
 170         if (retval != ERROR_OK)
 171                 return retval;
 172         retval = dap_setup_accessport_tar(dap, tar);
 173         if (retval != ERROR_OK)
 174                 return retval;
 175         return ERROR_OK;
 176 }
 177
 178 /**
 179  * Asynchronous (queued) read of a word from memory or a system register.
 180  *
 181  * @param dap The DAP connected to the MEM-AP performing the read.
 182  * @param address Address of the 32-bit word to read; it must be
 183  *      readable by the currently selected MEM-AP.
 184  * @param value points to where the word will be stored when the
 185  *      transaction queue is flushed (assuming no errors).
 186  *
 187  * @return ERROR_OK for success.  Otherwise a fault code.
 188  */
 189 static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
 190                 uint32_t *value)
 191 {
 192         int retval;
 193
 194         /* Use banked addressing (REG_BDx) to avoid some link traffic
 195          * (updating TAR) when reading several consecutive addresses.
 196          */
 197         retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
 198                         address & 0xFFFFFFF0);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         return dap_queue_ap_read(ap->dap, MEM_AP_REG_BD0 | (address & 0xC), value);
 203 }
 204
 205 /**
 206  * Synchronous read of a word from memory or a system register.
 207  * As a side effect, this flushes any queued transactions.
 208  *
 209  * @param dap The DAP connected to the MEM-AP performing the read.
 210  * @param address Address of the 32-bit word to read; it must be
 211  *      readable by the currently selected MEM-AP.
 212  * @param value points to where the result will be stored.
 213  *
 214  * @return ERROR_OK for success; *value holds the result.
 215  * Otherwise a fault code.
 216  */
 217 static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 218                 uint32_t *value)
 219 {
 220         int retval;
 221
 222         retval = mem_ap_read_u32(ap, address, value);
 223         if (retval != ERROR_OK)
 224                 return retval;
 225
 226         return dap_run(ap->dap);
 227 }
 228
 229 /**
 230  * Asynchronous (queued) write of a word to memory or a system register.
 231  *
 232  * @param dap The DAP connected to the MEM-AP.
 233  * @param address Address to be written; it must be writable by
 234  *      the currently selected MEM-AP.
 235  * @param value Word that will be written to the address when transaction
 236  *      queue is flushed (assuming no errors).
 237  *
 238  * @return ERROR_OK for success.  Otherwise a fault code.
 239  */
 240 static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
 241                 uint32_t value)
 242 {
 243         int retval;
 244
 245         /* Use banked addressing (REG_BDx) to avoid some link traffic
 246          * (updating TAR) when writing several consecutive addresses.
 247          */
 248         retval = dap_setup_accessport(ap->dap, CSW_32BIT | CSW_ADDRINC_OFF,
 249                         address & 0xFFFFFFF0);
 250         if (retval != ERROR_OK)
 251                 return retval;
 252
 253         return dap_queue_ap_write(ap->dap, MEM_AP_REG_BD0 | (address & 0xC),
 254                         value);
 255 }
 256
 257 /**
 258  * Synchronous write of a word to memory or a system register.
 259  * As a side effect, this flushes any queued transactions.
 260  *
 261  * @param dap The DAP connected to the MEM-AP.
 262  * @param address Address to be written; it must be writable by
 263  *      the currently selected MEM-AP.
 264  * @param value Word that will be written.
 265  *
 266  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 267  */
 268 static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 269                 uint32_t value)
 270 {
 271         int retval = mem_ap_write_u32(ap, address, value);
 272
 273         if (retval != ERROR_OK)
 274                 return retval;
 275
 276         return dap_run(ap->dap);
 277 }
 278
 279 /**
 280  * Synchronous write of a block of memory, using a specific access size.
 281  *
 282  * @param dap The DAP connected to the MEM-AP.
 283  * @param buffer The data buffer to write. No particular alignment is assumed.
 284  * @param size Which access size to use, in bytes. 1, 2 or 4.
 285  * @param count The number of writes to do (in size units, not bytes).
 286  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 287  * @param addrinc Whether the target address should be increased for each write or not. This
 288  *  should normally be true, except when writing to e.g. a FIFO.
 289  * @return ERROR_OK on success, otherwise an error code.
 290  */
 291 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
 292                 uint32_t address, bool addrinc)
 293 {
 294         struct adiv5_dap *dap = ap->dap;
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (ap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && ap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         struct adiv5_dap *dap = ap->dap;
 426         size_t nbytes = size * count;
 427         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 428         uint32_t csw_size;
 429         uint32_t address = adr;
 430         int retval;
 431
 432         /* TI BE-32 Quirks mode:
 433          * Reads on big-endian TMS570 behave strangely differently than writes.
 434          * They read from the physical address requested, but with DRW byte-reversed.
 435          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 436          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 437          * so avoid them. */
 438
 439         if (size == 4)
 440                 csw_size = CSW_32BIT;
 441         else if (size == 2)
 442                 csw_size = CSW_16BIT;
 443         else if (size == 1)
 444                 csw_size = CSW_8BIT;
 445         else
 446                 return ERROR_TARGET_UNALIGNED_ACCESS;
 447
 448         if (ap->unaligned_access_bad && (adr % size != 0))
 449                 return ERROR_TARGET_UNALIGNED_ACCESS;
 450
 451         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 452          * over-allocation if packed transfers are going to be used, but determining the real need at
 453          * this point would be messy. */
 454         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 455         uint32_t *read_ptr = read_buf;
 456         if (read_buf == NULL) {
 457                 LOG_ERROR("Failed to allocate read buffer");
 458                 return ERROR_FAIL;
 459         }
 460
 461         retval = dap_setup_accessport_tar(dap, address);
 462         if (retval != ERROR_OK) {
 463                 free(read_buf);
 464                 return retval;
 465         }
 466
 467         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 468          * useful bytes it contains, and their location in the word, depends on the type of transfer
 469          * and alignment. */
 470         while (nbytes > 0) {
 471                 uint32_t this_size = size;
 472
 473                 /* Select packed transfer if possible */
 474                 if (addrinc && ap->packed_transfers && nbytes >= 4
 475                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 476                         this_size = 4;
 477                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 478                 } else {
 479                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 480                 }
 481                 if (retval != ERROR_OK)
 482                         break;
 483
 484                 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
 485                 if (retval != ERROR_OK)
 486                         break;
 487
 488                 nbytes -= this_size;
 489                 address += this_size;
 490
 491                 /* Rewrite TAR if it wrapped */
 492                 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
 493                         retval = dap_setup_accessport_tar(dap, address);
 494                         if (retval != ERROR_OK)
 495                                 break;
 496                 }
 497         }
 498
 499         if (retval == ERROR_OK)
 500                 retval = dap_run(dap);
 501
 502         /* Restore state */
 503         address = adr;
 504         nbytes = size * count;
 505         read_ptr = read_buf;
 506
 507         /* If something failed, read TAR to find out how much data was successfully read, so we can
 508          * at least give the caller what we have. */
 509         if (retval != ERROR_OK) {
 510                 uint32_t tar;
 511                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 512                                 && dap_run(dap) == ERROR_OK) {
 513                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 514                         if (nbytes > tar - address)
 515                                 nbytes = tar - address;
 516                 } else {
 517                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 518                         nbytes = 0;
 519                 }
 520         }
 521
 522         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 523         while (nbytes > 0) {
 524                 uint32_t this_size = size;
 525
 526                 if (addrinc && ap->packed_transfers && nbytes >= 4
 527                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 528                         this_size = 4;
 529                 }
 530
 531                 if (dap->ti_be_32_quirks) {
 532                         switch (this_size) {
 533                         case 4:
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 536                         case 2:
 537                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 538                         case 1:
 539                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 540                         }
 541                 } else {
 542                         switch (this_size) {
 543                         case 4:
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 546                         case 2:
 547                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 548                         case 1:
 549                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 550                         }
 551                 }
 552
 553                 read_ptr++;
 554                 nbytes -= this_size;
 555         }
 556
 557         free(read_buf);
 558         return retval;
 559 }
 560
 561 /*--------------------------------------------------------------------*/
 562 /*          Wrapping function with selection of AP                    */
 563 /*--------------------------------------------------------------------*/
 564 int mem_ap_sel_read_u32(struct adiv5_ap *ap,
 565                 uint32_t address, uint32_t *value)
 566 {
 567         dap_ap_select(ap->dap, ap->ap_num);
 568         return mem_ap_read_u32(ap, address, value);
 569 }
 570
 571 int mem_ap_sel_write_u32(struct adiv5_ap *ap,
 572                 uint32_t address, uint32_t value)
 573 {
 574         dap_ap_select(ap->dap, ap->ap_num);
 575         return mem_ap_write_u32(ap, address, value);
 576 }
 577
 578 int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
 579                 uint32_t address, uint32_t *value)
 580 {
 581         dap_ap_select(ap->dap, ap->ap_num);
 582         return mem_ap_read_atomic_u32(ap, address, value);
 583 }
 584
 585 int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
 586                 uint32_t address, uint32_t value)
 587 {
 588         dap_ap_select(ap->dap, ap->ap_num);
 589         return mem_ap_write_atomic_u32(ap, address, value);
 590 }
 591
 592 int mem_ap_sel_read_buf(struct adiv5_ap *ap,
 593                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 594 {
 595         dap_ap_select(ap->dap, ap->ap_num);
 596         return mem_ap_read(ap, buffer, size, count, address, true);
 597 }
 598
 599 int mem_ap_sel_write_buf(struct adiv5_ap *ap,
 600                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 601 {
 602         dap_ap_select(ap->dap, ap->ap_num);
 603         return mem_ap_write(ap, buffer, size, count, address, true);
 604 }
 605
 606 int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
 607                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 608 {
 609         dap_ap_select(ap->dap, ap->ap_num);
 610         return mem_ap_read(ap, buffer, size, count, address, false);
 611 }
 612
 613 int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
 614                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 615 {
 616         dap_ap_select(ap->dap, ap->ap_num);
 617         return mem_ap_write(ap, buffer, size, count, address, false);
 618 }
 619
 620 /*--------------------------------------------------------------------------*/
 621
 622
 623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 624
 625 /* FIXME don't import ... just initialize as
 626  * part of DAP transport setup
 627 */
 628 extern const struct dap_ops jtag_dp_ops;
 629
 630 /*--------------------------------------------------------------------------*/
 631
 632 /**
 633  * Create a new DAP
 634  */
 635 struct adiv5_dap *dap_init(void)
 636 {
 637         struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
 638         int i;
 639         /* Set up with safe defaults */
 640         for (i = 0; i <= 255; i++) {
 641                 dap->ap[i].dap = dap;
 642                 dap->ap[i].ap_num = i;
 643                 /* memaccess_tck max is 255 */
 644                 dap->ap[i].memaccess_tck = 255;
 645                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
 646                 dap->ap[i].tar_autoincr_block = (1<<10);
 647         }
 648         return dap;
 649 }
 650
 651 /**
 652  * Initialize a DAP.  This sets up the power domains, prepares the DP
 653  * for further use, and arranges to use AP #0 for all AP operations
 654  * until dap_ap-select() changes that policy.
 655  *
 656  * @param dap The DAP being initialized.
 657  *
 658  * @todo Rename this.  We also need an initialization scheme which account
 659  * for SWD transports not just JTAG; that will need to address differences
 660  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 661  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 662  */
 663 int ahbap_debugport_init(struct adiv5_ap *ap)
 664 {
 665         /* check that we support packed transfers */
 666         uint32_t csw, cfg;
 667         int retval;
 668         struct adiv5_dap *dap = ap->dap;
 669
 670         LOG_DEBUG(" ");
 671
 672         /* JTAG-DP or SWJ-DP, in JTAG mode
 673          * ... for SWD mode this is patched as part
 674          * of link switchover
 675          */
 676         if (!dap->ops)
 677                 dap->ops = &jtag_dp_ops;
 678
 679         /* Default MEM-AP setup.
 680          *
 681          * REVISIT AP #0 may be an inappropriate default for this.
 682          * Should we probe, or take a hint from the caller?
 683          * Presumably we can ignore the possibility of multiple APs.
 684          */
 685         dap->ap_current = -1;
 686         dap_ap_select(dap, ap->ap_num);
 687         dap->last_read = NULL;
 688
 689         for (size_t i = 0; i < 10; i++) {
 690                 /* DP initialization */
 691
 692                 dap->dp_bank_value = 0;
 693
 694                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 695                 if (retval != ERROR_OK)
 696                         continue;
 697
 698                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 699                 if (retval != ERROR_OK)
 700                         continue;
 701
 702                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 703                 if (retval != ERROR_OK)
 704                         continue;
 705
 706                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 707                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 708                 if (retval != ERROR_OK)
 709                         continue;
 710
 711                 /* Check that we have debug power domains activated */
 712                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 713                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 714                                               CDBGPWRUPACK, CDBGPWRUPACK,
 715                                               DAP_POWER_DOMAIN_TIMEOUT);
 716                 if (retval != ERROR_OK)
 717                         continue;
 718
 719                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 720                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 721                                               CSYSPWRUPACK, CSYSPWRUPACK,
 722                                               DAP_POWER_DOMAIN_TIMEOUT);
 723                 if (retval != ERROR_OK)
 724                         continue;
 725
 726                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 727                 if (retval != ERROR_OK)
 728                         continue;
 729                 /* With debug power on we can activate OVERRUN checking */
 730                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 731                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 732                 if (retval != ERROR_OK)
 733                         continue;
 734                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 735                 if (retval != ERROR_OK)
 736                         continue;
 737
 738                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 739                 if (retval != ERROR_OK)
 740                         continue;
 741
 742                 retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
 743                 if (retval != ERROR_OK)
 744                         continue;
 745
 746                 retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
 747                 if (retval != ERROR_OK)
 748                         continue;
 749
 750                 retval = dap_run(dap);
 751                 if (retval != ERROR_OK)
 752                         continue;
 753
 754                 break;
 755         }
 756
 757         if (retval != ERROR_OK)
 758                 return retval;
 759
 760         if (csw & CSW_ADDRINC_PACKED)
 761                 ap->packed_transfers = true;
 762         else
 763                 ap->packed_transfers = false;
 764
 765         /* Packed transfers on TI BE-32 processors do not work correctly in
 766          * many cases. */
 767         if (dap->ti_be_32_quirks)
 768                 ap->packed_transfers = false;
 769
 770         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 771                         ap->packed_transfers ? "enabled" : "disabled");
 772
 773         /* The ARM ADI spec leaves implementation-defined whether unaligned
 774          * memory accesses work, only work partially, or cause a sticky error.
 775          * On TI BE-32 processors, reads seem to return garbage in some bytes
 776          * and unaligned writes seem to cause a sticky error.
 777          * TODO: it would be nice to have a way to detect whether unaligned
 778          * operations are supported on other processors. */
 779         ap->unaligned_access_bad = dap->ti_be_32_quirks;
 780
 781         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 782                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 783
 784         return ERROR_OK;
 785 }
 786
 787 /* CID interpretation -- see ARM IHI 0029B section 3
 788  * and ARM IHI 0031A table 13-3.
 789  */
 790 static const char *class_description[16] = {
 791         "Reserved", "ROM table", "Reserved", "Reserved",
 792         "Reserved", "Reserved", "Reserved", "Reserved",
 793         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 794         "Reserved", "OptimoDE DESS",
 795         "Generic IP component", "PrimeCell or System component"
 796 };
 797
 798 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 799 {
 800         return cid3 == 0xb1 && cid2 == 0x05
 801                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 802 }
 803
 804 /*
 805  * This function checks the ID for each access port to find the requested Access Port type
 806  */
 807 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 808 {
 809         int ap_num;
 810
 811         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 812         for (ap_num = 0; ap_num <= 255; ap_num++) {
 813
 814                 /* read the IDR register of the Access Port */
 815                 uint32_t id_val = 0;
 816                 dap_ap_select(dap, ap_num);
 817
 818                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 819                 if (retval != ERROR_OK)
 820                         return retval;
 821
 822                 retval = dap_run(dap);
 823
 824                 /* IDR bits:
 825                  * 31-28 : Revision
 826                  * 27-24 : JEDEC bank (0x4 for ARM)
 827                  * 23-17 : JEDEC code (0x3B for ARM)
 828                  * 16-13 : Class (0b1000=Mem-AP)
 829                  * 12-8  : Reserved
 830                  *  7-4  : AP Variant (non-zero for JTAG-AP)
 831                  *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 832                  */
 833
 834                 /* Reading register for a non-existant AP should not cause an error,
 835                  * but just to be sure, try to continue searching if an error does happen.
 836                  */
 837                 if ((retval == ERROR_OK) &&                  /* Register read success */
 838                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 839                         ((id_val & 0xF) == type_to_find)) {      /* type matches*/
 840
 841                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 842                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 843                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 844                                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 845                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 846                                                 ap_num, id_val);
 847
 848                         *ap_out = &dap->ap[ap_num];
 849                         return ERROR_OK;
 850                 }
 851         }
 852
 853         LOG_DEBUG("No %s found",
 854                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 855                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 856                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 857                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 858         return ERROR_FAIL;
 859 }
 860
 861 int dap_get_debugbase(struct adiv5_ap *ap,
 862                         uint32_t *dbgbase, uint32_t *apid)
 863 {
 864         struct adiv5_dap *dap = ap->dap;
 865         uint32_t ap_old;
 866         int retval;
 867
 868         ap_old = dap_ap_get_select(dap);
 869         dap_ap_select(dap, ap->ap_num);
 870
 871         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
 872         if (retval != ERROR_OK)
 873                 return retval;
 874         retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
 875         if (retval != ERROR_OK)
 876                 return retval;
 877         retval = dap_run(dap);
 878         if (retval != ERROR_OK)
 879                 return retval;
 880
 881         dap_ap_select(dap, ap_old);
 882
 883         return ERROR_OK;
 884 }
 885
 886 int dap_lookup_cs_component(struct adiv5_ap *ap,
 887                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 888 {
 889         struct adiv5_dap *dap = ap->dap;
 890         uint32_t ap_old;
 891         uint32_t romentry, entry_offset = 0, component_base, devtype;
 892         int retval;
 893
 894         *addr = 0;
 895         ap_old = dap_ap_get_select(dap);
 896
 897         do {
 898                 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
 899                                                 entry_offset, &romentry);
 900                 if (retval != ERROR_OK)
 901                         return retval;
 902
 903                 component_base = (dbgbase & 0xFFFFF000)
 904                         + (romentry & 0xFFFFF000);
 905
 906                 if (romentry & 0x1) {
 907                         uint32_t c_cid1;
 908                         retval = mem_ap_sel_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
 909                         if (retval != ERROR_OK) {
 910                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 911                                           ", the corresponding core might be turned off", component_base);
 912                                 return retval;
 913                         }
 914                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 915                                 retval = dap_lookup_cs_component(ap, component_base,
 916                                                         type, addr, idx);
 917                                 if (retval == ERROR_OK)
 918                                         break;
 919                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 920                                         return retval;
 921                         }
 922
 923                         retval = mem_ap_sel_read_atomic_u32(ap,
 924                                         (component_base & 0xfffff000) | 0xfcc,
 925                                         &devtype);
 926                         if (retval != ERROR_OK)
 927                                 return retval;
 928                         if ((devtype & 0xff) == type) {
 929                                 if (!*idx) {
 930                                         *addr = component_base;
 931                                         break;
 932                                 } else
 933                                         (*idx)--;
 934                         }
 935                 }
 936                 entry_offset += 4;
 937         } while (romentry > 0);
 938
 939         dap_ap_select(dap, ap_old);
 940
 941         if (!*addr)
 942                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 943
 944         return ERROR_OK;
 945 }
 946
 947 static int dap_rom_display(struct command_context *cmd_ctx,
 948                                 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 949 {
 950         struct adiv5_dap *dap = ap->dap;
 951         int retval;
 952         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 953         uint16_t entry_offset;
 954         char tabs[7] = "";
 955
 956         if (depth > 16) {
 957                 command_print(cmd_ctx, "\tTables too deep");
 958                 return ERROR_FAIL;
 959         }
 960
 961         if (depth)
 962                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 963
 964         /* bit 16 of apid indicates a memory access port */
 965         if (dbgbase & 0x02)
 966                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 967         else
 968                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 969
 970         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 971         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 972         if (retval != ERROR_OK)
 973                 return retval;
 974         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 975         if (retval != ERROR_OK)
 976                 return retval;
 977         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 978         if (retval != ERROR_OK)
 979                 return retval;
 980         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 981         if (retval != ERROR_OK)
 982                 return retval;
 983         retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 984         if (retval != ERROR_OK)
 985                 return retval;
 986         retval = dap_run(dap);
 987         if (retval != ERROR_OK)
 988                 return retval;
 989
 990         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 991                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 992                                 ", CID2 0x%02x"
 993                                 ", CID1 0x%02x"
 994                                 ", CID0 0x%02x",
 995                                 tabs,
 996                                 (unsigned)cid3, (unsigned)cid2,
 997                                 (unsigned)cid1, (unsigned)cid0);
 998         if (memtype & 0x01)
 999                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1000         else
1001                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1002
1003         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1004         for (entry_offset = 0; ; entry_offset += 4) {
1005                 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1006                 if (retval != ERROR_OK)
1007                         return retval;
1008                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1009                                 tabs, entry_offset, romentry);
1010                 if (romentry & 0x01) {
1011                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1012                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1013                         uint32_t component_base;
1014                         uint32_t part_num;
1015                         const char *type, *full;
1016
1017                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1018
1019                         /* IDs are in last 4K section */
1020                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
1021                         if (retval != ERROR_OK) {
1022                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1023                                               ", the corresponding core might be turned off", tabs, component_base);
1024                                 continue;
1025                         }
1026                         c_pid0 &= 0xff;
1027                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
1028                         if (retval != ERROR_OK)
1029                                 return retval;
1030                         c_pid1 &= 0xff;
1031                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1032                         if (retval != ERROR_OK)
1033                                 return retval;
1034                         c_pid2 &= 0xff;
1035                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1036                         if (retval != ERROR_OK)
1037                                 return retval;
1038                         c_pid3 &= 0xff;
1039                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1040                         if (retval != ERROR_OK)
1041                                 return retval;
1042                         c_pid4 &= 0xff;
1043
1044                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1045                         if (retval != ERROR_OK)
1046                                 return retval;
1047                         c_cid0 &= 0xff;
1048                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1049                         if (retval != ERROR_OK)
1050                                 return retval;
1051                         c_cid1 &= 0xff;
1052                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1053                         if (retval != ERROR_OK)
1054                                 return retval;
1055                         c_cid2 &= 0xff;
1056                         retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1057                         if (retval != ERROR_OK)
1058                                 return retval;
1059                         c_cid3 &= 0xff;
1060
1061                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1062                                       "start address 0x%" PRIx32, component_base,
1063                                       /* component may take multiple 4K pages */
1064                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1065                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1066                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1067                                         /* See ARM IHI 0029B Table 3-3 */
1068                                         class_description[(c_cid1 >> 4) & 0xf]);
1069
1070                         /* CoreSight component? */
1071                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1072                                 uint32_t devtype;
1073                                 unsigned minor;
1074                                 const char *major = "Reserved", *subtype = "Reserved";
1075
1076                                 retval = mem_ap_sel_read_atomic_u32(ap,
1077                                                 (component_base & 0xfffff000) | 0xfcc,
1078                                                 &devtype);
1079                                 if (retval != ERROR_OK)
1080                                         return retval;
1081                                 minor = (devtype >> 4) & 0x0f;
1082                                 switch (devtype & 0x0f) {
1083                                 case 0:
1084                                         major = "Miscellaneous";
1085                                         switch (minor) {
1086                                         case 0:
1087                                                 subtype = "other";
1088                                                 break;
1089                                         case 4:
1090                                                 subtype = "Validation component";
1091                                                 break;
1092                                         }
1093                                         break;
1094                                 case 1:
1095                                         major = "Trace Sink";
1096                                         switch (minor) {
1097                                         case 0:
1098                                                 subtype = "other";
1099                                                 break;
1100                                         case 1:
1101                                                 subtype = "Port";
1102                                                 break;
1103                                         case 2:
1104                                                 subtype = "Buffer";
1105                                                 break;
1106                                         case 3:
1107                                                 subtype = "Router";
1108                                                 break;
1109                                         }
1110                                         break;
1111                                 case 2:
1112                                         major = "Trace Link";
1113                                         switch (minor) {
1114                                         case 0:
1115                                                 subtype = "other";
1116                                                 break;
1117                                         case 1:
1118                                                 subtype = "Funnel, router";
1119                                                 break;
1120                                         case 2:
1121                                                 subtype = "Filter";
1122                                                 break;
1123                                         case 3:
1124                                                 subtype = "FIFO, buffer";
1125                                                 break;
1126                                         }
1127                                         break;
1128                                 case 3:
1129                                         major = "Trace Source";
1130                                         switch (minor) {
1131                                         case 0:
1132                                                 subtype = "other";
1133                                                 break;
1134                                         case 1:
1135                                                 subtype = "Processor";
1136                                                 break;
1137                                         case 2:
1138                                                 subtype = "DSP";
1139                                                 break;
1140                                         case 3:
1141                                                 subtype = "Engine/Coprocessor";
1142                                                 break;
1143                                         case 4:
1144                                                 subtype = "Bus";
1145                                                 break;
1146                                         case 6:
1147                                                 subtype = "Software";
1148                                                 break;
1149                                         }
1150                                         break;
1151                                 case 4:
1152                                         major = "Debug Control";
1153                                         switch (minor) {
1154                                         case 0:
1155                                                 subtype = "other";
1156                                                 break;
1157                                         case 1:
1158                                                 subtype = "Trigger Matrix";
1159                                                 break;
1160                                         case 2:
1161                                                 subtype = "Debug Auth";
1162                                                 break;
1163                                         case 3:
1164                                                 subtype = "Power Requestor";
1165                                                 break;
1166                                         }
1167                                         break;
1168                                 case 5:
1169                                         major = "Debug Logic";
1170                                         switch (minor) {
1171                                         case 0:
1172                                                 subtype = "other";
1173                                                 break;
1174                                         case 1:
1175                                                 subtype = "Processor";
1176                                                 break;
1177                                         case 2:
1178                                                 subtype = "DSP";
1179                                                 break;
1180                                         case 3:
1181                                                 subtype = "Engine/Coprocessor";
1182                                                 break;
1183                                         case 4:
1184                                                 subtype = "Bus";
1185                                                 break;
1186                                         case 5:
1187                                                 subtype = "Memory";
1188                                                 break;
1189                                         }
1190                                         break;
1191                                 case 6:
1192                                         major = "Perfomance Monitor";
1193                                         switch (minor) {
1194                                         case 0:
1195                                                 subtype = "other";
1196                                                 break;
1197                                         case 1:
1198                                                 subtype = "Processor";
1199                                                 break;
1200                                         case 2:
1201                                                 subtype = "DSP";
1202                                                 break;
1203                                         case 3:
1204                                                 subtype = "Engine/Coprocessor";
1205                                                 break;
1206                                         case 4:
1207                                                 subtype = "Bus";
1208                                                 break;
1209                                         case 5:
1210                                                 subtype = "Memory";
1211                                                 break;
1212                                         }
1213                                         break;
1214                                 }
1215                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1216                                                 (uint8_t)(devtype & 0xff),
1217                                                 major, subtype);
1218                                 /* REVISIT also show 0xfc8 DevId */
1219                         }
1220
1221                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1222                                 command_print(cmd_ctx,
1223                                                 "\t\tCID3 0%02x"
1224                                                 ", CID2 0%02x"
1225                                                 ", CID1 0%02x"
1226                                                 ", CID0 0%02x",
1227                                                 (int)c_cid3,
1228                                                 (int)c_cid2,
1229                                                 (int)c_cid1,
1230                                                 (int)c_cid0);
1231                         command_print(cmd_ctx,
1232                                 "\t\tPeripheral ID[4..0] = hex "
1233                                 "%02x %02x %02x %02x %02x",
1234                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1235                                 (int)c_pid1, (int)c_pid0);
1236
1237                         /* Part number interpretations are from Cortex
1238                          * core specs, the CoreSight components TRM
1239                          * (ARM DDI 0314H), CoreSight System Design
1240                          * Guide (ARM DGI 0012D) and ETM specs; also
1241                          * from chip observation (e.g. TI SDTI).
1242                          */
1243                         part_num = (c_pid0 & 0xff);
1244                         part_num |= (c_pid1 & 0x0f) << 8;
1245                         switch (part_num) {
1246                         case 0x000:
1247                                 type = "Cortex-M3 NVIC";
1248                                 full = "(Interrupt Controller)";
1249                                 break;
1250                         case 0x001:
1251                                 type = "Cortex-M3 ITM";
1252                                 full = "(Instrumentation Trace Module)";
1253                                 break;
1254                         case 0x002:
1255                                 type = "Cortex-M3 DWT";
1256                                 full = "(Data Watchpoint and Trace)";
1257                                 break;
1258                         case 0x003:
1259                                 type = "Cortex-M3 FBP";
1260                                 full = "(Flash Patch and Breakpoint)";
1261                                 break;
1262                         case 0x008:
1263                                 type = "Cortex-M0 SCS";
1264                                 full = "(System Control Space)";
1265                                 break;
1266                         case 0x00a:
1267                                 type = "Cortex-M0 DWT";
1268                                 full = "(Data Watchpoint and Trace)";
1269                                 break;
1270                         case 0x00b:
1271                                 type = "Cortex-M0 BPU";
1272                                 full = "(Breakpoint Unit)";
1273                                 break;
1274                         case 0x00c:
1275                                 type = "Cortex-M4 SCS";
1276                                 full = "(System Control Space)";
1277                                 break;
1278                         case 0x00d:
1279                                 type = "CoreSight ETM11";
1280                                 full = "(Embedded Trace)";
1281                                 break;
1282                         /* case 0x113: what? */
1283                         case 0x120:             /* from OMAP3 memmap */
1284                                 type = "TI SDTI";
1285                                 full = "(System Debug Trace Interface)";
1286                                 break;
1287                         case 0x343:             /* from OMAP3 memmap */
1288                                 type = "TI DAPCTL";
1289                                 full = "";
1290                                 break;
1291                         case 0x906:
1292                                 type = "Coresight CTI";
1293                                 full = "(Cross Trigger)";
1294                                 break;
1295                         case 0x907:
1296                                 type = "Coresight ETB";
1297                                 full = "(Trace Buffer)";
1298                                 break;
1299                         case 0x908:
1300                                 type = "Coresight CSTF";
1301                                 full = "(Trace Funnel)";
1302                                 break;
1303                         case 0x910:
1304                                 type = "CoreSight ETM9";
1305                                 full = "(Embedded Trace)";
1306                                 break;
1307                         case 0x912:
1308                                 type = "Coresight TPIU";
1309                                 full = "(Trace Port Interface Unit)";
1310                                 break;
1311                         case 0x913:
1312                                 type = "Coresight ITM";
1313                                 full = "(Instrumentation Trace Macrocell)";
1314                                 break;
1315                         case 0x914:
1316                                 type = "Coresight SWO";
1317                                 full = "(Single Wire Output)";
1318                                 break;
1319                         case 0x917:
1320                                 type = "Coresight HTM";
1321                                 full = "(AHB Trace Macrocell)";
1322                                 break;
1323                         case 0x920:
1324                                 type = "CoreSight ETM11";
1325                                 full = "(Embedded Trace)";
1326                                 break;
1327                         case 0x921:
1328                                 type = "Cortex-A8 ETM";
1329                                 full = "(Embedded Trace)";
1330                                 break;
1331                         case 0x922:
1332                                 type = "Cortex-A8 CTI";
1333                                 full = "(Cross Trigger)";
1334                                 break;
1335                         case 0x923:
1336                                 type = "Cortex-M3 TPIU";
1337                                 full = "(Trace Port Interface Unit)";
1338                                 break;
1339                         case 0x924:
1340                                 type = "Cortex-M3 ETM";
1341                                 full = "(Embedded Trace)";
1342                                 break;
1343                         case 0x925:
1344                                 type = "Cortex-M4 ETM";
1345                                 full = "(Embedded Trace)";
1346                                 break;
1347                         case 0x930:
1348                                 type = "Cortex-R4 ETM";
1349                                 full = "(Embedded Trace)";
1350                                 break;
1351                         case 0x950:
1352                                 type = "CoreSight Component";
1353                                 full = "(unidentified Cortex-A9 component)";
1354                                 break;
1355                         case 0x961:
1356                                 type = "CoreSight TMC";
1357                                 full = "(Trace Memory Controller)";
1358                                 break;
1359                         case 0x962:
1360                                 type = "CoreSight STM";
1361                                 full = "(System Trace Macrocell)";
1362                                 break;
1363                         case 0x9a0:
1364                                 type = "CoreSight PMU";
1365                                 full = "(Performance Monitoring Unit)";
1366                                 break;
1367                         case 0x9a1:
1368                                 type = "Cortex-M4 TPUI";
1369                                 full = "(Trace Port Interface Unit)";
1370                                 break;
1371                         case 0x9a5:
1372                                 type = "Cortex-A5 ETM";
1373                                 full = "(Embedded Trace)";
1374                                 break;
1375                         case 0xc05:
1376                                 type = "Cortex-A5 Debug";
1377                                 full = "(Debug Unit)";
1378                                 break;
1379                         case 0xc08:
1380                                 type = "Cortex-A8 Debug";
1381                                 full = "(Debug Unit)";
1382                                 break;
1383                         case 0xc09:
1384                                 type = "Cortex-A9 Debug";
1385                                 full = "(Debug Unit)";
1386                                 break;
1387                         case 0x4af:
1388                                 type = "Cortex-A15 Debug";
1389                                 full = "(Debug Unit)";
1390                                 break;
1391                         default:
1392                                 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1393                                 type = "-*- unrecognized -*-";
1394                                 full = "";
1395                                 break;
1396                         }
1397                         command_print(cmd_ctx, "\t\tPart is %s %s",
1398                                         type, full);
1399
1400                         /* ROM Table? */
1401                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1402                                 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1403                                 if (retval != ERROR_OK)
1404                                         return retval;
1405                         }
1406                 } else {
1407                         if (romentry)
1408                                 command_print(cmd_ctx, "\t\tComponent not present");
1409                         else
1410                                 break;
1411                 }
1412         }
1413         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1414         return ERROR_OK;
1415 }
1416
1417 static int dap_info_command(struct command_context *cmd_ctx,
1418                 struct adiv5_ap *ap)
1419 {
1420         struct adiv5_dap *dap = ap->dap;
1421         int retval;
1422         uint32_t dbgbase, apid;
1423         int romtable_present = 0;
1424         uint8_t mem_ap;
1425         uint32_t ap_old;
1426
1427         retval = dap_get_debugbase(ap, &dbgbase, &apid);
1428         if (retval != ERROR_OK)
1429                 return retval;
1430
1431         ap_old = dap_ap_get_select(dap);
1432         dap_ap_select(dap, ap->ap_num);
1433
1434         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1435         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1436         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1437         if (apid) {
1438                 switch (apid&0x0F) {
1439                         case 0:
1440                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1441                                 break;
1442                         case 1:
1443                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1444                                 break;
1445                         case 2:
1446                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1447                                 break;
1448                         default:
1449                                 command_print(cmd_ctx, "\tUnknown AP type");
1450                                 break;
1451                 }
1452
1453                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1454                  * not a ROM table ... or have no such components at all.
1455                  */
1456                 if (mem_ap)
1457                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1458         } else
1459                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1460
1461         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1462         if (romtable_present)
1463                 dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1464         else
1465                 command_print(cmd_ctx, "\tNo ROM table present");
1466         dap_ap_select(dap, ap_old);
1467
1468         return ERROR_OK;
1469 }
1470
1471 COMMAND_HANDLER(handle_dap_info_command)
1472 {
1473         struct target *target = get_current_target(CMD_CTX);
1474         struct arm *arm = target_to_arm(target);
1475         struct adiv5_dap *dap = arm->dap;
1476         uint32_t apsel;
1477
1478         switch (CMD_ARGC) {
1479         case 0:
1480                 apsel = dap->apsel;
1481                 break;
1482         case 1:
1483                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1484                 if (apsel >= 256)
1485                         return ERROR_COMMAND_SYNTAX_ERROR;
1486                 break;
1487         default:
1488                 return ERROR_COMMAND_SYNTAX_ERROR;
1489         }
1490
1491         return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1492 }
1493
1494 COMMAND_HANDLER(dap_baseaddr_command)
1495 {
1496         struct target *target = get_current_target(CMD_CTX);
1497         struct arm *arm = target_to_arm(target);
1498         struct adiv5_dap *dap = arm->dap;
1499
1500         uint32_t apsel, baseaddr;
1501         int retval;
1502
1503         switch (CMD_ARGC) {
1504         case 0:
1505                 apsel = dap->apsel;
1506                 break;
1507         case 1:
1508                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1509                 /* AP address is in bits 31:24 of DP_SELECT */
1510                 if (apsel >= 256)
1511                         return ERROR_COMMAND_SYNTAX_ERROR;
1512                 break;
1513         default:
1514                 return ERROR_COMMAND_SYNTAX_ERROR;
1515         }
1516
1517         dap_ap_select(dap, apsel);
1518
1519         /* NOTE:  assumes we're talking to a MEM-AP, which
1520          * has a base address.  There are other kinds of AP,
1521          * though they're not common for now.  This should
1522          * use the ID register to verify it's a MEM-AP.
1523          */
1524         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1525         if (retval != ERROR_OK)
1526                 return retval;
1527         retval = dap_run(dap);
1528         if (retval != ERROR_OK)
1529                 return retval;
1530
1531         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1532
1533         return retval;
1534 }
1535
1536 COMMAND_HANDLER(dap_memaccess_command)
1537 {
1538         struct target *target = get_current_target(CMD_CTX);
1539         struct arm *arm = target_to_arm(target);
1540         struct adiv5_dap *dap = arm->dap;
1541
1542         uint32_t memaccess_tck;
1543
1544         switch (CMD_ARGC) {
1545         case 0:
1546                 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1547                 break;
1548         case 1:
1549                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1550                 break;
1551         default:
1552                 return ERROR_COMMAND_SYNTAX_ERROR;
1553         }
1554         dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1555
1556         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1557                         dap->ap[dap->apsel].memaccess_tck);
1558
1559         return ERROR_OK;
1560 }
1561
1562 COMMAND_HANDLER(dap_apsel_command)
1563 {
1564         struct target *target = get_current_target(CMD_CTX);
1565         struct arm *arm = target_to_arm(target);
1566         struct adiv5_dap *dap = arm->dap;
1567
1568         uint32_t apsel, apid;
1569         int retval;
1570
1571         switch (CMD_ARGC) {
1572         case 0:
1573                 apsel = 0;
1574                 break;
1575         case 1:
1576                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1577                 /* AP address is in bits 31:24 of DP_SELECT */
1578                 if (apsel >= 256)
1579                         return ERROR_COMMAND_SYNTAX_ERROR;
1580                 break;
1581         default:
1582                 return ERROR_COMMAND_SYNTAX_ERROR;
1583         }
1584
1585         dap->apsel = apsel;
1586         dap_ap_select(dap, apsel);
1587
1588         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1589         if (retval != ERROR_OK)
1590                 return retval;
1591         retval = dap_run(dap);
1592         if (retval != ERROR_OK)
1593                 return retval;
1594
1595         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1596                         apsel, apid);
1597
1598         return retval;
1599 }
1600
1601 COMMAND_HANDLER(dap_apcsw_command)
1602 {
1603         struct target *target = get_current_target(CMD_CTX);
1604         struct arm *arm = target_to_arm(target);
1605         struct adiv5_dap *dap = arm->dap;
1606
1607         uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1608
1609         switch (CMD_ARGC) {
1610         case 0:
1611                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1612                         (dap->apsel), apcsw);
1613                 break;
1614         case 1:
1615                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1616                 /* AP address is in bits 31:24 of DP_SELECT */
1617                 if (sprot > 1)
1618                         return ERROR_COMMAND_SYNTAX_ERROR;
1619                 if (sprot)
1620                         apcsw |= CSW_SPROT;
1621                 else
1622                         apcsw &= ~CSW_SPROT;
1623                 break;
1624         default:
1625                 return ERROR_COMMAND_SYNTAX_ERROR;
1626         }
1627         dap->ap[dap->apsel].csw_default = apcsw;
1628
1629         return 0;
1630 }
1631
1632
1633
1634 COMMAND_HANDLER(dap_apid_command)
1635 {
1636         struct target *target = get_current_target(CMD_CTX);
1637         struct arm *arm = target_to_arm(target);
1638         struct adiv5_dap *dap = arm->dap;
1639
1640         uint32_t apsel, apid;
1641         int retval;
1642
1643         switch (CMD_ARGC) {
1644         case 0:
1645                 apsel = dap->apsel;
1646                 break;
1647         case 1:
1648                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1649                 /* AP address is in bits 31:24 of DP_SELECT */
1650                 if (apsel >= 256)
1651                         return ERROR_COMMAND_SYNTAX_ERROR;
1652                 break;
1653         default:
1654                 return ERROR_COMMAND_SYNTAX_ERROR;
1655         }
1656
1657         dap_ap_select(dap, apsel);
1658
1659         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1660         if (retval != ERROR_OK)
1661                 return retval;
1662         retval = dap_run(dap);
1663         if (retval != ERROR_OK)
1664                 return retval;
1665
1666         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1667
1668         return retval;
1669 }
1670
1671 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1672 {
1673         struct target *target = get_current_target(CMD_CTX);
1674         struct arm *arm = target_to_arm(target);
1675         struct adiv5_dap *dap = arm->dap;
1676
1677         uint32_t enable = dap->ti_be_32_quirks;
1678
1679         switch (CMD_ARGC) {
1680         case 0:
1681                 break;
1682         case 1:
1683                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1684                 if (enable > 1)
1685                         return ERROR_COMMAND_SYNTAX_ERROR;
1686                 break;
1687         default:
1688                 return ERROR_COMMAND_SYNTAX_ERROR;
1689         }
1690         dap->ti_be_32_quirks = enable;
1691         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1692                 enable ? "enabled" : "disabled");
1693
1694         return 0;
1695 }
1696
1697 static const struct command_registration dap_commands[] = {
1698         {
1699                 .name = "info",
1700                 .handler = handle_dap_info_command,
1701                 .mode = COMMAND_EXEC,
1702                 .help = "display ROM table for MEM-AP "
1703                         "(default currently selected AP)",
1704                 .usage = "[ap_num]",
1705         },
1706         {
1707                 .name = "apsel",
1708                 .handler = dap_apsel_command,
1709                 .mode = COMMAND_EXEC,
1710                 .help = "Set the currently selected AP (default 0) "
1711                         "and display the result",
1712                 .usage = "[ap_num]",
1713         },
1714         {
1715                 .name = "apcsw",
1716                 .handler = dap_apcsw_command,
1717                 .mode = COMMAND_EXEC,
1718                 .help = "Set csw access bit ",
1719                 .usage = "[sprot]",
1720         },
1721
1722         {
1723                 .name = "apid",
1724                 .handler = dap_apid_command,
1725                 .mode = COMMAND_EXEC,
1726                 .help = "return ID register from AP "
1727                         "(default currently selected AP)",
1728                 .usage = "[ap_num]",
1729         },
1730         {
1731                 .name = "baseaddr",
1732                 .handler = dap_baseaddr_command,
1733                 .mode = COMMAND_EXEC,
1734                 .help = "return debug base address from MEM-AP "
1735                         "(default currently selected AP)",
1736                 .usage = "[ap_num]",
1737         },
1738         {
1739                 .name = "memaccess",
1740                 .handler = dap_memaccess_command,
1741                 .mode = COMMAND_EXEC,
1742                 .help = "set/get number of extra tck for MEM-AP memory "
1743                         "bus access [0-255]",
1744                 .usage = "[cycles]",
1745         },
1746         {
1747                 .name = "ti_be_32_quirks",
1748                 .handler = dap_ti_be_32_quirks_command,
1749                 .mode = COMMAND_CONFIG,
1750                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1751                 .usage = "[enable]",
1752         },
1753         COMMAND_REGISTRATION_DONE
1754 };
1755
1756 const struct command_registration dap_command_handlers[] = {
1757         {
1758                 .name = "dap",
1759                 .mode = COMMAND_EXEC,
1760                 .help = "DAP command group",
1761                 .usage = "",
1762                 .chain = dap_commands,
1763         },
1764         COMMAND_REGISTRATION_DONE
1765 };