1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
119 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
121 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
122 dap->ap[dap_ap_get_select(dap)].csw_default;
124 if (csw != dap->ap[dap_ap_get_select(dap)].csw_value) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
127 if (retval != ERROR_OK)
129 dap->ap[dap_ap_get_select(dap)].csw_value = csw;
134 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
136 if (tar != dap->ap[dap_ap_get_select(dap)].tar_value ||
137 (dap->ap[dap_ap_get_select(dap)].csw_value & CSW_ADDRINC_MASK)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
140 if (retval != ERROR_OK)
142 dap->ap[dap_ap_get_select(dap)].tar_value = tar;
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @todo Rename to reflect it being specifically a MEM-AP function.
158 * @param dap The DAP connected to the MEM-AP.
159 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
160 * matches the cached value, the register is not changed.
161 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
162 * matches the cached address, the register is not changed.
164 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
169 retval = dap_setup_accessport_csw(dap, csw);
170 if (retval != ERROR_OK)
172 retval = dap_setup_accessport_tar(dap, tar);
173 if (retval != ERROR_OK)
179 * Asynchronous (queued) read of a word from memory or a system register.
181 * @param dap The DAP connected to the MEM-AP performing the read.
182 * @param address Address of the 32-bit word to read; it must be
183 * readable by the currently selected MEM-AP.
184 * @param value points to where the word will be stored when the
185 * transaction queue is flushed (assuming no errors).
187 * @return ERROR_OK for success. Otherwise a fault code.
189 static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
194 /* Use banked addressing (REG_BDx) to avoid some link traffic
195 * (updating TAR) when reading several consecutive addresses.
197 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
198 address & 0xFFFFFFF0);
199 if (retval != ERROR_OK)
202 return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
206 * Synchronous read of a word from memory or a system register.
207 * As a side effect, this flushes any queued transactions.
209 * @param dap The DAP connected to the MEM-AP performing the read.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the result will be stored.
214 * @return ERROR_OK for success; *value holds the result.
215 * Otherwise a fault code.
217 static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
222 retval = mem_ap_read_u32(dap, address, value);
223 if (retval != ERROR_OK)
230 * Asynchronous (queued) write of a word to memory or a system register.
232 * @param dap The DAP connected to the MEM-AP.
233 * @param address Address to be written; it must be writable by
234 * the currently selected MEM-AP.
235 * @param value Word that will be written to the address when transaction
236 * queue is flushed (assuming no errors).
238 * @return ERROR_OK for success. Otherwise a fault code.
240 static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
245 /* Use banked addressing (REG_BDx) to avoid some link traffic
246 * (updating TAR) when writing several consecutive addresses.
248 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
249 address & 0xFFFFFFF0);
250 if (retval != ERROR_OK)
253 return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
258 * Synchronous write of a word to memory or a system register.
259 * As a side effect, this flushes any queued transactions.
261 * @param dap The DAP connected to the MEM-AP.
262 * @param address Address to be written; it must be writable by
263 * the currently selected MEM-AP.
264 * @param value Word that will be written.
266 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
271 int retval = mem_ap_write_u32(dap, address, value);
273 if (retval != ERROR_OK)
280 * Synchronous write of a block of memory, using a specific access size.
282 * @param dap The DAP connected to the MEM-AP.
283 * @param buffer The data buffer to write. No particular alignment is assumed.
284 * @param size Which access size to use, in bytes. 1, 2 or 4.
285 * @param count The number of writes to do (in size units, not bytes).
286 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
287 * @param addrinc Whether the target address should be increased for each write or not. This
288 * should normally be true, except when writing to e.g. a FIFO.
289 * @return ERROR_OK on success, otherwise an error code.
291 static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
292 uint32_t address, bool addrinc)
294 struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
301 /* TI BE-32 Quirks mode:
302 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
303 * size write address bytes written in order
304 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
305 * 2 TAR ^ 2 (val >> 8), (val)
307 * For example, if you attempt to write a single byte to address 0, the processor
308 * will actually write a byte to address 3.
310 * To make writes of size < 4 work as expected, we xor a value with the address before
311 * setting the TAP, and we set the TAP after every transfer rather then relying on
312 * address increment. */
315 csw_size = CSW_32BIT;
317 } else if (size == 2) {
318 csw_size = CSW_16BIT;
319 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
320 } else if (size == 1) {
322 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
324 return ERROR_TARGET_UNALIGNED_ACCESS;
327 if (ap->unaligned_access_bad && (address % size != 0))
328 return ERROR_TARGET_UNALIGNED_ACCESS;
330 retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
331 if (retval != ERROR_OK)
335 uint32_t this_size = size;
337 /* Select packed transfer if possible */
338 if (addrinc && ap->packed_transfers && nbytes >= 4
339 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
341 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
343 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
346 if (retval != ERROR_OK)
349 /* How many source bytes each transfer will consume, and their location in the DRW,
350 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
351 uint32_t outvalue = 0;
352 if (dap->ti_be_32_quirks) {
355 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
356 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
357 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
358 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
361 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
362 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
365 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
371 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
372 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
374 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
376 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
382 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
383 if (retval != ERROR_OK)
386 /* Rewrite TAR if it wrapped or we're xoring addresses */
387 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
388 retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
389 if (retval != ERROR_OK)
394 /* REVISIT: Might want to have a queued version of this function that does not run. */
395 if (retval == ERROR_OK)
396 retval = dap_run(dap);
398 if (retval != ERROR_OK) {
400 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
401 && dap_run(dap) == ERROR_OK)
402 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
404 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
411 * Synchronous read of a block of memory, using a specific access size.
413 * @param dap The DAP connected to the MEM-AP.
414 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
415 * @param size Which access size to use, in bytes. 1, 2 or 4.
416 * @param count The number of reads to do (in size units, not bytes).
417 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
418 * @param addrinc Whether the target address should be increased after each read or not. This
419 * should normally be true, except when reading from e.g. a FIFO.
420 * @return ERROR_OK on success, otherwise an error code.
422 static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
423 uint32_t adr, bool addrinc)
425 struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
426 size_t nbytes = size * count;
427 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
429 uint32_t address = adr;
432 /* TI BE-32 Quirks mode:
433 * Reads on big-endian TMS570 behave strangely differently than writes.
434 * They read from the physical address requested, but with DRW byte-reversed.
435 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
436 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
440 csw_size = CSW_32BIT;
442 csw_size = CSW_16BIT;
446 return ERROR_TARGET_UNALIGNED_ACCESS;
448 if (ap->unaligned_access_bad && (adr % size != 0))
449 return ERROR_TARGET_UNALIGNED_ACCESS;
451 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
452 * over-allocation if packed transfers are going to be used, but determining the real need at
453 * this point would be messy. */
454 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
455 uint32_t *read_ptr = read_buf;
456 if (read_buf == NULL) {
457 LOG_ERROR("Failed to allocate read buffer");
461 retval = dap_setup_accessport_tar(dap, address);
462 if (retval != ERROR_OK) {
467 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
468 * useful bytes it contains, and their location in the word, depends on the type of transfer
471 uint32_t this_size = size;
473 /* Select packed transfer if possible */
474 if (addrinc && ap->packed_transfers && nbytes >= 4
475 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
477 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
479 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
481 if (retval != ERROR_OK)
484 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
485 if (retval != ERROR_OK)
489 address += this_size;
491 /* Rewrite TAR if it wrapped */
492 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
493 retval = dap_setup_accessport_tar(dap, address);
494 if (retval != ERROR_OK)
499 if (retval == ERROR_OK)
500 retval = dap_run(dap);
504 nbytes = size * count;
507 /* If something failed, read TAR to find out how much data was successfully read, so we can
508 * at least give the caller what we have. */
509 if (retval != ERROR_OK) {
511 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
512 && dap_run(dap) == ERROR_OK) {
513 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
514 if (nbytes > tar - address)
515 nbytes = tar - address;
517 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
522 /* Replay loop to populate caller's buffer from the correct word and byte lane */
524 uint32_t this_size = size;
526 if (addrinc && ap->packed_transfers && nbytes >= 4
527 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
531 if (dap->ti_be_32_quirks) {
534 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
535 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
537 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
539 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
544 *buffer++ = *read_ptr >> 8 * (address++ & 3);
545 *buffer++ = *read_ptr >> 8 * (address++ & 3);
547 *buffer++ = *read_ptr >> 8 * (address++ & 3);
549 *buffer++ = *read_ptr >> 8 * (address++ & 3);
561 /*--------------------------------------------------------------------*/
562 /* Wrapping function with selection of AP */
563 /*--------------------------------------------------------------------*/
564 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
565 uint32_t address, uint32_t *value)
567 dap_ap_select(swjdp, ap);
568 return mem_ap_read_u32(swjdp, address, value);
571 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
572 uint32_t address, uint32_t value)
574 dap_ap_select(swjdp, ap);
575 return mem_ap_write_u32(swjdp, address, value);
578 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
579 uint32_t address, uint32_t *value)
581 dap_ap_select(swjdp, ap);
582 return mem_ap_read_atomic_u32(swjdp, address, value);
585 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
586 uint32_t address, uint32_t value)
588 dap_ap_select(swjdp, ap);
589 return mem_ap_write_atomic_u32(swjdp, address, value);
592 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
593 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
595 dap_ap_select(swjdp, ap);
596 return mem_ap_read(swjdp, buffer, size, count, address, true);
599 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
600 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 dap_ap_select(swjdp, ap);
603 return mem_ap_write(swjdp, buffer, size, count, address, true);
606 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
607 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
609 dap_ap_select(swjdp, ap);
610 return mem_ap_read(swjdp, buffer, size, count, address, false);
613 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
614 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
616 dap_ap_select(swjdp, ap);
617 return mem_ap_write(swjdp, buffer, size, count, address, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /* FIXME don't import ... just initialize as
626 * part of DAP transport setup
628 extern const struct dap_ops jtag_dp_ops;
630 /*--------------------------------------------------------------------------*/
635 struct adiv5_dap *dap_init(void)
637 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
639 /* Set up with safe defaults */
640 for (i = 0; i <= 255; i++) {
641 dap->ap[i].dap = dap;
642 dap->ap[i].ap_num = i;
643 /* memaccess_tck max is 255 */
644 dap->ap[i].memaccess_tck = 255;
645 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
646 dap->ap[i].tar_autoincr_block = (1<<10);
652 * Initialize a DAP. This sets up the power domains, prepares the DP
653 * for further use, and arranges to use AP #0 for all AP operations
654 * until dap_ap-select() changes that policy.
656 * @param dap The DAP being initialized.
658 * @todo Rename this. We also need an initialization scheme which account
659 * for SWD transports not just JTAG; that will need to address differences
660 * in layering. (JTAG is useful without any debug target; but not SWD.)
661 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
663 int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
665 /* check that we support packed transfers */
668 struct adiv5_ap *ap = &dap->ap[apsel];
672 /* JTAG-DP or SWJ-DP, in JTAG mode
673 * ... for SWD mode this is patched as part
677 dap->ops = &jtag_dp_ops;
679 /* Default MEM-AP setup.
681 * REVISIT AP #0 may be an inappropriate default for this.
682 * Should we probe, or take a hint from the caller?
683 * Presumably we can ignore the possibility of multiple APs.
685 dap->ap_current = -1;
686 dap_ap_select(dap, apsel);
687 dap->last_read = NULL;
689 for (size_t i = 0; i < 10; i++) {
690 /* DP initialization */
692 dap->dp_bank_value = 0;
694 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
695 if (retval != ERROR_OK)
698 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
699 if (retval != ERROR_OK)
702 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
703 if (retval != ERROR_OK)
706 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
707 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
708 if (retval != ERROR_OK)
711 /* Check that we have debug power domains activated */
712 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
713 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
714 CDBGPWRUPACK, CDBGPWRUPACK,
715 DAP_POWER_DOMAIN_TIMEOUT);
716 if (retval != ERROR_OK)
719 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
720 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
721 CSYSPWRUPACK, CSYSPWRUPACK,
722 DAP_POWER_DOMAIN_TIMEOUT);
723 if (retval != ERROR_OK)
726 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
727 if (retval != ERROR_OK)
729 /* With debug power on we can activate OVERRUN checking */
730 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
731 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
732 if (retval != ERROR_OK)
734 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
735 if (retval != ERROR_OK)
738 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
739 if (retval != ERROR_OK)
742 retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
743 if (retval != ERROR_OK)
746 retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
747 if (retval != ERROR_OK)
750 retval = dap_run(dap);
751 if (retval != ERROR_OK)
757 if (retval != ERROR_OK)
760 if (csw & CSW_ADDRINC_PACKED)
761 ap->packed_transfers = true;
763 ap->packed_transfers = false;
765 /* Packed transfers on TI BE-32 processors do not work correctly in
767 if (dap->ti_be_32_quirks)
768 ap->packed_transfers = false;
770 LOG_DEBUG("MEM_AP Packed Transfers: %s",
771 ap->packed_transfers ? "enabled" : "disabled");
773 /* The ARM ADI spec leaves implementation-defined whether unaligned
774 * memory accesses work, only work partially, or cause a sticky error.
775 * On TI BE-32 processors, reads seem to return garbage in some bytes
776 * and unaligned writes seem to cause a sticky error.
777 * TODO: it would be nice to have a way to detect whether unaligned
778 * operations are supported on other processors. */
779 ap->unaligned_access_bad = dap->ti_be_32_quirks;
781 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
782 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
787 /* CID interpretation -- see ARM IHI 0029B section 3
788 * and ARM IHI 0031A table 13-3.
790 static const char *class_description[16] = {
791 "Reserved", "ROM table", "Reserved", "Reserved",
792 "Reserved", "Reserved", "Reserved", "Reserved",
793 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
794 "Reserved", "OptimoDE DESS",
795 "Generic IP component", "PrimeCell or System component"
798 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
800 return cid3 == 0xb1 && cid2 == 0x05
801 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
805 * This function checks the ID for each access port to find the requested Access Port type
807 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
811 /* Maximum AP number is 255 since the SELECT register is 8 bits */
812 for (ap = 0; ap <= 255; ap++) {
814 /* read the IDR register of the Access Port */
816 dap_ap_select(dap, ap);
818 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
819 if (retval != ERROR_OK)
822 retval = dap_run(dap);
826 * 27-24 : JEDEC bank (0x4 for ARM)
827 * 23-17 : JEDEC code (0x3B for ARM)
828 * 16-13 : Class (0b1000=Mem-AP)
830 * 7-4 : AP Variant (non-zero for JTAG-AP)
831 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
834 /* Reading register for a non-existant AP should not cause an error,
835 * but just to be sure, try to continue searching if an error does happen.
837 if ((retval == ERROR_OK) && /* Register read success */
838 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
839 ((id_val & 0xF) == type_to_find)) { /* type matches*/
841 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
842 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
843 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
844 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
845 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
853 LOG_DEBUG("No %s found",
854 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
855 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
856 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
857 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
861 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
862 uint32_t *dbgbase, uint32_t *apid)
867 /* AP address is in bits 31:24 of DP_SELECT */
869 return ERROR_COMMAND_SYNTAX_ERROR;
871 ap_old = dap_ap_get_select(dap);
872 dap_ap_select(dap, ap);
874 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
875 if (retval != ERROR_OK)
877 retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
878 if (retval != ERROR_OK)
880 retval = dap_run(dap);
881 if (retval != ERROR_OK)
884 dap_ap_select(dap, ap_old);
889 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
890 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
893 uint32_t romentry, entry_offset = 0, component_base, devtype;
897 return ERROR_COMMAND_SYNTAX_ERROR;
900 ap_old = dap_ap_get_select(dap);
901 dap_ap_select(dap, ap);
904 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
905 entry_offset, &romentry);
906 if (retval != ERROR_OK)
909 component_base = (dbgbase & 0xFFFFF000)
910 + (romentry & 0xFFFFF000);
912 if (romentry & 0x1) {
914 retval = mem_ap_read_atomic_u32(dap, component_base | 0xff4, &c_cid1);
915 if (retval != ERROR_OK) {
916 LOG_ERROR("Can't read component with base address 0x%" PRIx32
917 ", the corresponding core might be turned off", component_base);
920 if (((c_cid1 >> 4) & 0x0f) == 1) {
921 retval = dap_lookup_cs_component(dap, ap, component_base,
923 if (retval == ERROR_OK)
925 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
929 retval = mem_ap_read_atomic_u32(dap,
930 (component_base & 0xfffff000) | 0xfcc,
932 if (retval != ERROR_OK)
934 if ((devtype & 0xff) == type) {
936 *addr = component_base;
943 } while (romentry > 0);
945 dap_ap_select(dap, ap_old);
948 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
953 static int dap_rom_display(struct command_context *cmd_ctx,
954 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
957 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
958 uint16_t entry_offset;
962 command_print(cmd_ctx, "\tTables too deep");
967 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
969 /* bit 16 of apid indicates a memory access port */
971 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
973 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
975 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
976 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
977 if (retval != ERROR_OK)
979 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
980 if (retval != ERROR_OK)
982 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
983 if (retval != ERROR_OK)
985 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
986 if (retval != ERROR_OK)
988 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
989 if (retval != ERROR_OK)
991 retval = dap_run(dap);
992 if (retval != ERROR_OK)
995 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
996 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1001 (unsigned)cid3, (unsigned)cid2,
1002 (unsigned)cid1, (unsigned)cid0);
1004 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1006 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1008 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1009 for (entry_offset = 0; ; entry_offset += 4) {
1010 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1011 if (retval != ERROR_OK)
1013 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1014 tabs, entry_offset, romentry);
1015 if (romentry & 0x01) {
1016 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1017 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1018 uint32_t component_base;
1020 const char *type, *full;
1022 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1024 /* IDs are in last 4K section */
1025 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1026 if (retval != ERROR_OK) {
1027 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1028 ", the corresponding core might be turned off", tabs, component_base);
1032 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1033 if (retval != ERROR_OK)
1036 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1037 if (retval != ERROR_OK)
1040 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1041 if (retval != ERROR_OK)
1044 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1045 if (retval != ERROR_OK)
1049 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1050 if (retval != ERROR_OK)
1053 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1054 if (retval != ERROR_OK)
1057 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1058 if (retval != ERROR_OK)
1061 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1062 if (retval != ERROR_OK)
1066 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1067 "start address 0x%" PRIx32, component_base,
1068 /* component may take multiple 4K pages */
1069 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1070 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1071 (uint8_t)((c_cid1 >> 4) & 0xf),
1072 /* See ARM IHI 0029B Table 3-3 */
1073 class_description[(c_cid1 >> 4) & 0xf]);
1075 /* CoreSight component? */
1076 if (((c_cid1 >> 4) & 0x0f) == 9) {
1079 const char *major = "Reserved", *subtype = "Reserved";
1081 retval = mem_ap_read_atomic_u32(dap,
1082 (component_base & 0xfffff000) | 0xfcc,
1084 if (retval != ERROR_OK)
1086 minor = (devtype >> 4) & 0x0f;
1087 switch (devtype & 0x0f) {
1089 major = "Miscellaneous";
1095 subtype = "Validation component";
1100 major = "Trace Sink";
1117 major = "Trace Link";
1123 subtype = "Funnel, router";
1129 subtype = "FIFO, buffer";
1134 major = "Trace Source";
1140 subtype = "Processor";
1146 subtype = "Engine/Coprocessor";
1152 subtype = "Software";
1157 major = "Debug Control";
1163 subtype = "Trigger Matrix";
1166 subtype = "Debug Auth";
1169 subtype = "Power Requestor";
1174 major = "Debug Logic";
1180 subtype = "Processor";
1186 subtype = "Engine/Coprocessor";
1197 major = "Perfomance Monitor";
1203 subtype = "Processor";
1209 subtype = "Engine/Coprocessor";
1220 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1221 (uint8_t)(devtype & 0xff),
1223 /* REVISIT also show 0xfc8 DevId */
1226 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1227 command_print(cmd_ctx,
1236 command_print(cmd_ctx,
1237 "\t\tPeripheral ID[4..0] = hex "
1238 "%02x %02x %02x %02x %02x",
1239 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1240 (int)c_pid1, (int)c_pid0);
1242 /* Part number interpretations are from Cortex
1243 * core specs, the CoreSight components TRM
1244 * (ARM DDI 0314H), CoreSight System Design
1245 * Guide (ARM DGI 0012D) and ETM specs; also
1246 * from chip observation (e.g. TI SDTI).
1248 part_num = (c_pid0 & 0xff);
1249 part_num |= (c_pid1 & 0x0f) << 8;
1252 type = "Cortex-M3 NVIC";
1253 full = "(Interrupt Controller)";
1256 type = "Cortex-M3 ITM";
1257 full = "(Instrumentation Trace Module)";
1260 type = "Cortex-M3 DWT";
1261 full = "(Data Watchpoint and Trace)";
1264 type = "Cortex-M3 FBP";
1265 full = "(Flash Patch and Breakpoint)";
1268 type = "Cortex-M0 SCS";
1269 full = "(System Control Space)";
1272 type = "Cortex-M0 DWT";
1273 full = "(Data Watchpoint and Trace)";
1276 type = "Cortex-M0 BPU";
1277 full = "(Breakpoint Unit)";
1280 type = "Cortex-M4 SCS";
1281 full = "(System Control Space)";
1284 type = "CoreSight ETM11";
1285 full = "(Embedded Trace)";
1287 /* case 0x113: what? */
1288 case 0x120: /* from OMAP3 memmap */
1290 full = "(System Debug Trace Interface)";
1292 case 0x343: /* from OMAP3 memmap */
1297 type = "Coresight CTI";
1298 full = "(Cross Trigger)";
1301 type = "Coresight ETB";
1302 full = "(Trace Buffer)";
1305 type = "Coresight CSTF";
1306 full = "(Trace Funnel)";
1309 type = "CoreSight ETM9";
1310 full = "(Embedded Trace)";
1313 type = "Coresight TPIU";
1314 full = "(Trace Port Interface Unit)";
1317 type = "Coresight ITM";
1318 full = "(Instrumentation Trace Macrocell)";
1321 type = "Coresight SWO";
1322 full = "(Single Wire Output)";
1325 type = "Coresight HTM";
1326 full = "(AHB Trace Macrocell)";
1329 type = "CoreSight ETM11";
1330 full = "(Embedded Trace)";
1333 type = "Cortex-A8 ETM";
1334 full = "(Embedded Trace)";
1337 type = "Cortex-A8 CTI";
1338 full = "(Cross Trigger)";
1341 type = "Cortex-M3 TPIU";
1342 full = "(Trace Port Interface Unit)";
1345 type = "Cortex-M3 ETM";
1346 full = "(Embedded Trace)";
1349 type = "Cortex-M4 ETM";
1350 full = "(Embedded Trace)";
1353 type = "Cortex-R4 ETM";
1354 full = "(Embedded Trace)";
1357 type = "CoreSight Component";
1358 full = "(unidentified Cortex-A9 component)";
1361 type = "CoreSight TMC";
1362 full = "(Trace Memory Controller)";
1365 type = "CoreSight STM";
1366 full = "(System Trace Macrocell)";
1369 type = "CoreSight PMU";
1370 full = "(Performance Monitoring Unit)";
1373 type = "Cortex-M4 TPUI";
1374 full = "(Trace Port Interface Unit)";
1377 type = "Cortex-A5 ETM";
1378 full = "(Embedded Trace)";
1381 type = "Cortex-A5 Debug";
1382 full = "(Debug Unit)";
1385 type = "Cortex-A8 Debug";
1386 full = "(Debug Unit)";
1389 type = "Cortex-A9 Debug";
1390 full = "(Debug Unit)";
1393 type = "Cortex-A15 Debug";
1394 full = "(Debug Unit)";
1397 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1398 type = "-*- unrecognized -*-";
1402 command_print(cmd_ctx, "\t\tPart is %s %s",
1406 if (((c_cid1 >> 4) & 0x0f) == 1) {
1407 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1408 if (retval != ERROR_OK)
1413 command_print(cmd_ctx, "\t\tComponent not present");
1418 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1422 static int dap_info_command(struct command_context *cmd_ctx,
1423 struct adiv5_dap *dap, int ap)
1426 uint32_t dbgbase, apid;
1427 int romtable_present = 0;
1431 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1432 if (retval != ERROR_OK)
1435 ap_old = dap_ap_get_select(dap);
1436 dap_ap_select(dap, ap);
1438 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1439 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1440 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1442 switch (apid&0x0F) {
1444 command_print(cmd_ctx, "\tType is JTAG-AP");
1447 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1450 command_print(cmd_ctx, "\tType is MEM-AP APB");
1453 command_print(cmd_ctx, "\tUnknown AP type");
1457 /* NOTE: a MEM-AP may have a single CoreSight component that's
1458 * not a ROM table ... or have no such components at all.
1461 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1463 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1465 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1466 if (romtable_present)
1467 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1469 command_print(cmd_ctx, "\tNo ROM table present");
1470 dap_ap_select(dap, ap_old);
1475 COMMAND_HANDLER(handle_dap_info_command)
1477 struct target *target = get_current_target(CMD_CTX);
1478 struct arm *arm = target_to_arm(target);
1479 struct adiv5_dap *dap = arm->dap;
1487 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1490 return ERROR_COMMAND_SYNTAX_ERROR;
1493 return dap_info_command(CMD_CTX, dap, apsel);
1496 COMMAND_HANDLER(dap_baseaddr_command)
1498 struct target *target = get_current_target(CMD_CTX);
1499 struct arm *arm = target_to_arm(target);
1500 struct adiv5_dap *dap = arm->dap;
1502 uint32_t apsel, baseaddr;
1510 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1511 /* AP address is in bits 31:24 of DP_SELECT */
1513 return ERROR_COMMAND_SYNTAX_ERROR;
1516 return ERROR_COMMAND_SYNTAX_ERROR;
1519 dap_ap_select(dap, apsel);
1521 /* NOTE: assumes we're talking to a MEM-AP, which
1522 * has a base address. There are other kinds of AP,
1523 * though they're not common for now. This should
1524 * use the ID register to verify it's a MEM-AP.
1526 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1527 if (retval != ERROR_OK)
1529 retval = dap_run(dap);
1530 if (retval != ERROR_OK)
1533 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1538 COMMAND_HANDLER(dap_memaccess_command)
1540 struct target *target = get_current_target(CMD_CTX);
1541 struct arm *arm = target_to_arm(target);
1542 struct adiv5_dap *dap = arm->dap;
1544 uint32_t memaccess_tck;
1548 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1551 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1554 return ERROR_COMMAND_SYNTAX_ERROR;
1556 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1558 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1559 dap->ap[dap->apsel].memaccess_tck);
1564 COMMAND_HANDLER(dap_apsel_command)
1566 struct target *target = get_current_target(CMD_CTX);
1567 struct arm *arm = target_to_arm(target);
1568 struct adiv5_dap *dap = arm->dap;
1570 uint32_t apsel, apid;
1578 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1579 /* AP address is in bits 31:24 of DP_SELECT */
1581 return ERROR_COMMAND_SYNTAX_ERROR;
1584 return ERROR_COMMAND_SYNTAX_ERROR;
1588 dap_ap_select(dap, apsel);
1590 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1591 if (retval != ERROR_OK)
1593 retval = dap_run(dap);
1594 if (retval != ERROR_OK)
1597 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1603 COMMAND_HANDLER(dap_apcsw_command)
1605 struct target *target = get_current_target(CMD_CTX);
1606 struct arm *arm = target_to_arm(target);
1607 struct adiv5_dap *dap = arm->dap;
1609 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1613 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1614 (dap->apsel), apcsw);
1617 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1618 /* AP address is in bits 31:24 of DP_SELECT */
1620 return ERROR_COMMAND_SYNTAX_ERROR;
1624 apcsw &= ~CSW_SPROT;
1627 return ERROR_COMMAND_SYNTAX_ERROR;
1629 dap->ap[dap->apsel].csw_default = apcsw;
1636 COMMAND_HANDLER(dap_apid_command)
1638 struct target *target = get_current_target(CMD_CTX);
1639 struct arm *arm = target_to_arm(target);
1640 struct adiv5_dap *dap = arm->dap;
1642 uint32_t apsel, apid;
1650 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1651 /* AP address is in bits 31:24 of DP_SELECT */
1653 return ERROR_COMMAND_SYNTAX_ERROR;
1656 return ERROR_COMMAND_SYNTAX_ERROR;
1659 dap_ap_select(dap, apsel);
1661 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1662 if (retval != ERROR_OK)
1664 retval = dap_run(dap);
1665 if (retval != ERROR_OK)
1668 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1673 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1675 struct target *target = get_current_target(CMD_CTX);
1676 struct arm *arm = target_to_arm(target);
1677 struct adiv5_dap *dap = arm->dap;
1679 uint32_t enable = dap->ti_be_32_quirks;
1685 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1687 return ERROR_COMMAND_SYNTAX_ERROR;
1690 return ERROR_COMMAND_SYNTAX_ERROR;
1692 dap->ti_be_32_quirks = enable;
1693 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1694 enable ? "enabled" : "disabled");
1699 static const struct command_registration dap_commands[] = {
1702 .handler = handle_dap_info_command,
1703 .mode = COMMAND_EXEC,
1704 .help = "display ROM table for MEM-AP "
1705 "(default currently selected AP)",
1706 .usage = "[ap_num]",
1710 .handler = dap_apsel_command,
1711 .mode = COMMAND_EXEC,
1712 .help = "Set the currently selected AP (default 0) "
1713 "and display the result",
1714 .usage = "[ap_num]",
1718 .handler = dap_apcsw_command,
1719 .mode = COMMAND_EXEC,
1720 .help = "Set csw access bit ",
1726 .handler = dap_apid_command,
1727 .mode = COMMAND_EXEC,
1728 .help = "return ID register from AP "
1729 "(default currently selected AP)",
1730 .usage = "[ap_num]",
1734 .handler = dap_baseaddr_command,
1735 .mode = COMMAND_EXEC,
1736 .help = "return debug base address from MEM-AP "
1737 "(default currently selected AP)",
1738 .usage = "[ap_num]",
1741 .name = "memaccess",
1742 .handler = dap_memaccess_command,
1743 .mode = COMMAND_EXEC,
1744 .help = "set/get number of extra tck for MEM-AP memory "
1745 "bus access [0-255]",
1746 .usage = "[cycles]",
1749 .name = "ti_be_32_quirks",
1750 .handler = dap_ti_be_32_quirks_command,
1751 .mode = COMMAND_CONFIG,
1752 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1753 .usage = "[enable]",
1755 COMMAND_REGISTRATION_DONE
1758 const struct command_registration dap_command_handlers[] = {
1761 .mode = COMMAND_EXEC,
1762 .help = "DAP command group",
1764 .chain = dap_commands,
1766 COMMAND_REGISTRATION_DONE