1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
16 ***************************************************************************/
21 #include "arm_adi_v5.h"
22 #include "armv7a_cache.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
33 #define ARMV7_COMMON_MAGIC 0x0A450999
35 /* VA to PA translation operations opc2 values*/
44 /* L210/L220 cache controller support */
45 struct armv7a_l2x_cache {
50 struct armv7a_cachesize {
52 /* cache dimensionning */
54 uint32_t associativity;
57 /* info for set way operation on cache */
64 /* information about one architecture cache at any level */
65 struct armv7a_arch_cache {
66 int ctype; /* cache type, CLIDR encoding */
67 struct armv7a_cachesize d_u_size; /* data cache */
68 struct armv7a_cachesize i_size; /* instruction cache */
71 /* common cache information */
72 struct armv7a_cache_common {
73 int info; /* -1 invalid, else valid */
74 int loc; /* level of coherency */
75 uint32_t dminline; /* minimum d-cache linelen */
76 uint32_t iminline; /* minimum i-cache linelen */
77 struct armv7a_arch_cache arch[6]; /* cache info, L1 - L7 */
79 int d_u_cache_enabled;
80 int auto_cache_enabled; /* openocd automatic
82 /* outer unified cache if some */
84 int (*flush_all_data_cache)(struct target *target);
87 struct armv7a_mmu_common {
88 /* following field mmu working way */
89 int32_t cached; /* 0: not initialized, 1: initialized */
90 uint32_t ttbcr; /* cache for ttbcr register */
91 uint32_t ttbr_mask[2];
92 uint32_t ttbr_range[2];
94 int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
95 uint32_t count, uint8_t *buffer);
96 struct armv7a_cache_common armv7a_cache;
100 struct armv7a_common {
103 struct reg_cache *core_cache;
105 /* Core Debug Unit */
108 struct adiv5_ap *debug_ap;
109 struct adiv5_ap *memory_ap;
110 bool memory_ap_available;
112 uint8_t multi_processor_system;
120 uint32_t implementor;
122 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
123 struct armv7a_mmu_common armv7a_mmu;
125 int (*examine_debug_reason)(struct target *target);
126 int (*post_debug_entry)(struct target *target);
128 void (*pre_restore_context)(struct target *target);
131 static inline struct armv7a_common *
132 target_to_armv7a(struct target *target)
134 return container_of(target->arch_info, struct armv7a_common, arm);
137 /* register offsets from armv7a.debug_base */
139 /* See ARMv7a arch spec section C10.2 */
140 #define CPUDBG_DIDR 0x000
142 /* See ARMv7a arch spec section C10.3 */
143 #define CPUDBG_WFAR 0x018
144 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
145 #define CPUDBG_DSCR 0x088
146 #define CPUDBG_DRCR 0x090
147 #define CPUDBG_PRCR 0x310
148 #define CPUDBG_PRSR 0x314
150 /* See ARMv7a arch spec section C10.4 */
151 #define CPUDBG_DTRRX 0x080
152 #define CPUDBG_ITR 0x084
153 #define CPUDBG_DTRTX 0x08c
155 /* See ARMv7a arch spec section C10.5 */
156 #define CPUDBG_BVR_BASE 0x100
157 #define CPUDBG_BCR_BASE 0x140
158 #define CPUDBG_WVR_BASE 0x180
159 #define CPUDBG_WCR_BASE 0x1C0
160 #define CPUDBG_VCR 0x01C
162 /* See ARMv7a arch spec section C10.6 */
163 #define CPUDBG_OSLAR 0x300
164 #define CPUDBG_OSLSR 0x304
165 #define CPUDBG_OSSRR 0x308
166 #define CPUDBG_ECR 0x024
168 /* See ARMv7a arch spec section C10.7 */
169 #define CPUDBG_DSCCR 0x028
170 #define CPUDBG_DSMCR 0x02C
172 /* See ARMv7a arch spec section C10.8 */
173 #define CPUDBG_AUTHSTATUS 0xFB8
175 int armv7a_arch_state(struct target *target);
176 int armv7a_identify_cache(struct target *target);
177 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
178 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
179 uint32_t *val, int meminfo);
180 int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
182 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
183 struct armv7a_cache_common *armv7a_cache);
185 extern const struct command_registration armv7a_command_handlers[];
187 #endif /* ARMV4_5_H */