git.sur5r.net Git - openocd/blob - src/target/avr32_jtag.h

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17
  18 #ifndef OPENOCD_TARGET_AVR32_JTAG_H
  19 #define OPENOCD_TARGET_AVR32_JTAG_H
  20
  21 #define AVR32NUMCOREREGS        17
  22
  23 /* tap instructions */
  24 #define AVR32_INST_IDCODE               0x01
  25 #define AVR32_INST_NEXUS_ACCESS 0x10
  26 #define AVR32_INST_MW_ACCESS    0x11
  27 #define AVR32_INST_MB_ACCESS    0x12
  28
  29 #define SLAVE_OCD                               0x01
  30 #define SLAVE_HSB_CACHED                0x04
  31 #define SLAVE_HSB_UNCACHED              0x05
  32
  33 /*
  34  * Registers
  35  */
  36
  37 #define AVR32_OCDREG_DID                0x00
  38 #define AVR32_OCDREG_DC                 0x02
  39 #define         OCDREG_DC_SS                    (1 <<  8)
  40 #define         OCDREG_DC_DBR                   (1 << 12)
  41 #define         OCDREG_DC_DBE                   (1 << 13)
  42 #define         OCDREG_DC_SQA                   (1 << 22)
  43 #define         OCDREG_DC_RES                   (1 << 30)
  44 #define         OCDREG_DC_ABORT                 (1 << 31)
  45 #define AVR32_OCDREG_DS                 0x04
  46 #define         OCDREG_DS_SSS                   (1 <<  0)
  47 #define         OCDREG_DS_SWB                   (1 <<  1)
  48 #define         OCDREG_DS_HWB                   (1 <<  2)
  49 #define         OCDREG_DS_STP                   (1 <<  4)
  50 #define         OCDREG_DS_DBS                   (1 <<  5)
  51 #define         OCDREG_DS_BP_SHIFT              8
  52 #define         OCDREG_DS_BP_MASK               0xff
  53 #define         OCDREG_DS_INC                   (1 << 24)
  54 #define         OCDREG_DS_BOZ                   (1 << 25)
  55 #define         OCDREG_DS_DBA                   (1 << 26)
  56 #define         OCDREG_DS_EXB                   (1 << 27)
  57 #define         OCDREG_DS_NTBF                  (1 << 28)
  58
  59 #define AVR32_OCDREG_DINST              0x41
  60 #define AVR32_OCDREG_DPC                0x42
  61 #define AVR32_OCDREG_DCCPU              0x44
  62 #define AVR32_OCDREG_DCEMU              0x45
  63 #define AVR32_OCDREG_DCSR               0x46
  64 #define         OCDREG_DCSR_CPUD                (1 <<  0)
  65 #define         OCDREG_DCSR_EMUD                (1 <<  1)
  66
  67 /*
  68  * Direction bit
  69  */
  70 #define MODE_WRITE                              0x00
  71 #define MODE_READ                               0x01
  72
  73 /*
  74  * Some instructions
  75  */
  76
  77 #define RETD                                    0xd703d623
  78 #define MTDR(dreg, reg)                 (0xe7b00044 | ((reg) << 16) | dreg)
  79 #define MFDR(reg, dreg)                 (0xe5b00044 | ((reg) << 16) | dreg)
  80 #define MTSR(sysreg, reg)               (0xe3b00002 | ((reg) << 16) | sysreg)
  81 #define MFSR(reg, sysreg)               (0xe1b00002 | ((reg) << 16) | sysreg)
  82
  83 struct avr32_jtag {
  84         struct jtag_tap *tap;
  85         uint32_t dpc; /* Debug PC value */
  86 };
  87
  88 int avr32_jtag_nexus_read(struct avr32_jtag *jtag_info,
  89                 uint32_t addr, uint32_t *value);
  90 int avr32_jtag_nexus_write(struct avr32_jtag *jtag_info,
  91                 uint32_t addr, uint32_t value);
  92
  93 int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave,
  94                 uint32_t addr, uint32_t *value);
  95 int avr32_jtag_mwa_write(struct avr32_jtag *jtag_info, int slave,
  96                 uint32_t addr, uint32_t value);
  97
  98 int avr32_ocd_setbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
  99 int avr32_ocd_clearbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
 100
 101 int avr32_jtag_exec(struct avr32_jtag *jtag_info, uint32_t inst);
 102
 103 #endif /* OPENOCD_TARGET_AVR32_JTAG_H */