git.sur5r.net Git - openocd/blob - src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "breakpoints.h"
  29 #include "mips32.h"
  30 #include "mips_m4k.h"
  31 #include "mips32_dmaacc.h"
  32 #include "target_type.h"
  33 #include "register.h"
  34
  35 int mips_m4k_examine_debug_reason(struct target *target)
  36 {
  37         uint32_t break_status;
  38         int retval;
  39
  40         if ((target->debug_reason != DBG_REASON_DBGRQ)
  41                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
  42         {
  43                 /* get info about inst breakpoint support */
  44                 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
  45                         return retval;
  46                 if (break_status & 0x1f)
  47                 {
  48                         /* we have halted on a  breakpoint */
  49                         if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
  50                                 return retval;
  51                         target->debug_reason = DBG_REASON_BREAKPOINT;
  52                 }
  53
  54                 /* get info about data breakpoint support */
  55                 if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
  56                         return retval;
  57                 if (break_status & 0x1f)
  58                 {
  59                         /* we have halted on a  breakpoint */
  60                         if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
  61                                 return retval;
  62                         target->debug_reason = DBG_REASON_WATCHPOINT;
  63                 }
  64         }
  65
  66         return ERROR_OK;
  67 }
  68
  69 int mips_m4k_debug_entry(struct target *target)
  70 {
  71         struct mips32_common *mips32 = target_to_mips32(target);
  72         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  73         uint32_t debug_reg;
  74
  75         /* read debug register */
  76         mips_ejtag_read_debug(ejtag_info, &debug_reg);
  77
  78         /* make sure break unit configured */
  79         mips32_configure_break_unit(target);
  80
  81         /* attempt to find halt reason */
  82         mips_m4k_examine_debug_reason(target);
  83
  84         /* clear single step if active */
  85         if (debug_reg & EJTAG_DEBUG_DSS)
  86         {
  87                 /* stopped due to single step - clear step bit */
  88                 mips_ejtag_config_step(ejtag_info, 0);
  89         }
  90
  91         mips32_save_context(target);
  92
  93         /* default to mips32 isa, it will be changed below if required */
  94         mips32->isa_mode = MIPS32_ISA_MIPS32;
  95
  96         if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
  97                 mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1);
  98         }
  99
 100         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 101                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 102                         target_state_name(target));
 103
 104         return ERROR_OK;
 105 }
 106
 107 int mips_m4k_poll(struct target *target)
 108 {
 109         int retval;
 110         struct mips32_common *mips32 = target_to_mips32(target);
 111         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 112         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 113
 114         /* read ejtag control reg */
 115         jtag_set_end_state(TAP_IDLE);
 116         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 117         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 118
 119         /* clear this bit before handling polling
 120          * as after reset registers will read zero */
 121         if (ejtag_ctrl & EJTAG_CTRL_ROCC)
 122         {
 123                 /* we have detected a reset, clear flag
 124                  * otherwise ejtag will not work */
 125                 jtag_set_end_state(TAP_IDLE);
 126                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 127
 128                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 129                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 130                 LOG_DEBUG("Reset Detected");
 131         }
 132
 133         /* check for processor halted */
 134         if (ejtag_ctrl & EJTAG_CTRL_BRKST)
 135         {
 136                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 137                 {
 138                         jtag_set_end_state(TAP_IDLE);
 139                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 140
 141                         target->state = TARGET_HALTED;
 142
 143                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 144                                 return retval;
 145
 146                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 147                 }
 148                 else if (target->state == TARGET_DEBUG_RUNNING)
 149                 {
 150                         target->state = TARGET_HALTED;
 151
 152                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 153                                 return retval;
 154
 155                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 156                 }
 157         }
 158         else
 159         {
 160                 target->state = TARGET_RUNNING;
 161         }
 162
 163 //      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
 164
 165         return ERROR_OK;
 166 }
 167
 168 int mips_m4k_halt(struct target *target)
 169 {
 170         struct mips32_common *mips32 = target_to_mips32(target);
 171         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 172
 173         LOG_DEBUG("target->state: %s",
 174                   target_state_name(target));
 175
 176         if (target->state == TARGET_HALTED)
 177         {
 178                 LOG_DEBUG("target was already halted");
 179                 return ERROR_OK;
 180         }
 181
 182         if (target->state == TARGET_UNKNOWN)
 183         {
 184                 LOG_WARNING("target was in unknown state when halt was requested");
 185         }
 186
 187         if (target->state == TARGET_RESET)
 188         {
 189                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 190                 {
 191                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 192                         return ERROR_TARGET_FAILURE;
 193                 }
 194                 else
 195                 {
 196                         /* we came here in a reset_halt or reset_init sequence
 197                          * debug entry was already prepared in mips32_prepare_reset_halt()
 198                          */
 199                         target->debug_reason = DBG_REASON_DBGRQ;
 200
 201                         return ERROR_OK;
 202                 }
 203         }
 204
 205         /* break processor */
 206         mips_ejtag_enter_debug(ejtag_info);
 207
 208         target->debug_reason = DBG_REASON_DBGRQ;
 209
 210         return ERROR_OK;
 211 }
 212
 213 int mips_m4k_assert_reset(struct target *target)
 214 {
 215         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 216         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 217         int assert_srst = 1;
 218
 219         LOG_DEBUG("target->state: %s",
 220                 target_state_name(target));
 221
 222         enum reset_types jtag_reset_config = jtag_get_reset_config();
 223
 224         if (!(jtag_reset_config & RESET_HAS_SRST))
 225                 assert_srst = 0;
 226
 227         if (target->reset_halt)
 228         {
 229                 /* use hardware to catch reset */
 230                 jtag_set_end_state(TAP_IDLE);
 231                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
 232         }
 233         else
 234         {
 235                 jtag_set_end_state(TAP_IDLE);
 236                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 237         }
 238
 239         if (assert_srst)
 240         {
 241                 /* here we should issue a srst only, but we may have to assert trst as well */
 242                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 243                 {
 244                         jtag_add_reset(1, 1);
 245                 }
 246                 else
 247                 {
 248                         jtag_add_reset(0, 1);
 249                 }
 250         }
 251         else
 252         {
 253                 if (mips_m4k->is_pic32mx)
 254                 {
 255                         uint32_t mchip_cmd;
 256
 257                         LOG_DEBUG("Using MTAP reset to reset processor...");
 258
 259                         /* use microchip specific MTAP reset */
 260                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL);
 261                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL);
 262
 263                         mchip_cmd = MCHP_ASERT_RST;
 264                         mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
 265                         mchip_cmd = MCHP_DE_ASSERT_RST;
 266                         mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
 267                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
 268                 }
 269                 else
 270                 {
 271                         /* use ejtag reset - not supported by all cores */
 272                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 273                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 274                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 275                         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 276                 }
 277         }
 278
 279         target->state = TARGET_RESET;
 280         jtag_add_sleep(50000);
 281
 282         register_cache_invalidate(mips_m4k->mips32.core_cache);
 283
 284         if (target->reset_halt)
 285         {
 286                 int retval;
 287                 if ((retval = target_halt(target)) != ERROR_OK)
 288                         return retval;
 289         }
 290
 291         return ERROR_OK;
 292 }
 293
 294 int mips_m4k_deassert_reset(struct target *target)
 295 {
 296         LOG_DEBUG("target->state: %s",
 297                 target_state_name(target));
 298
 299         /* deassert reset lines */
 300         jtag_add_reset(0, 0);
 301
 302         return ERROR_OK;
 303 }
 304
 305 int mips_m4k_soft_reset_halt(struct target *target)
 306 {
 307         /* TODO */
 308         return ERROR_OK;
 309 }
 310
 311 int mips_m4k_single_step_core(struct target *target)
 312 {
 313         struct mips32_common *mips32 = target_to_mips32(target);
 314         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 315
 316         /* configure single step mode */
 317         mips_ejtag_config_step(ejtag_info, 1);
 318
 319         /* disable interrupts while stepping */
 320         mips32_enable_interrupts(target, 0);
 321
 322         /* exit debug mode */
 323         mips_ejtag_exit_debug(ejtag_info);
 324
 325         mips_m4k_debug_entry(target);
 326
 327         return ERROR_OK;
 328 }
 329
 330 int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 331 {
 332         struct mips32_common *mips32 = target_to_mips32(target);
 333         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 334         struct breakpoint *breakpoint = NULL;
 335         uint32_t resume_pc;
 336
 337         if (target->state != TARGET_HALTED)
 338         {
 339                 LOG_WARNING("target not halted");
 340                 return ERROR_TARGET_NOT_HALTED;
 341         }
 342
 343         if (!debug_execution)
 344         {
 345                 target_free_all_working_areas(target);
 346                 mips_m4k_enable_breakpoints(target);
 347                 mips_m4k_enable_watchpoints(target);
 348         }
 349
 350         /* current = 1: continue on current pc, otherwise continue at <address> */
 351         if (!current)
 352         {
 353                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 354                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 355                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 356         }
 357
 358         if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
 359                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 360         }
 361
 362         resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 363
 364         mips32_restore_context(target);
 365
 366         /* the front-end may request us not to handle breakpoints */
 367         if (handle_breakpoints)
 368         {
 369                 /* Single step past breakpoint at current address */
 370                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 371                 {
 372                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 373                         mips_m4k_unset_breakpoint(target, breakpoint);
 374                         mips_m4k_single_step_core(target);
 375                         mips_m4k_set_breakpoint(target, breakpoint);
 376                 }
 377         }
 378
 379         /* enable interrupts if we are running */
 380         mips32_enable_interrupts(target, !debug_execution);
 381
 382         /* exit debug mode */
 383         mips_ejtag_exit_debug(ejtag_info);
 384         target->debug_reason = DBG_REASON_NOTHALTED;
 385
 386         /* registers are now invalid */
 387         register_cache_invalidate(mips32->core_cache);
 388
 389         if (!debug_execution)
 390         {
 391                 target->state = TARGET_RUNNING;
 392                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 393                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 394         }
 395         else
 396         {
 397                 target->state = TARGET_DEBUG_RUNNING;
 398                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 399                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 400         }
 401
 402         return ERROR_OK;
 403 }
 404
 405 int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
 406 {
 407         /* get pointers to arch-specific information */
 408         struct mips32_common *mips32 = target_to_mips32(target);
 409         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 410         struct breakpoint *breakpoint = NULL;
 411
 412         if (target->state != TARGET_HALTED)
 413         {
 414                 LOG_WARNING("target not halted");
 415                 return ERROR_TARGET_NOT_HALTED;
 416         }
 417
 418         /* current = 1: continue on current pc, otherwise continue at <address> */
 419         if (!current)
 420                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 421
 422         /* the front-end may request us not to handle breakpoints */
 423         if (handle_breakpoints) {
 424                 breakpoint = breakpoint_find(target,
 425                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 426                 if (breakpoint)
 427                         mips_m4k_unset_breakpoint(target, breakpoint);
 428         }
 429
 430         /* restore context */
 431         mips32_restore_context(target);
 432
 433         /* configure single step mode */
 434         mips_ejtag_config_step(ejtag_info, 1);
 435
 436         target->debug_reason = DBG_REASON_SINGLESTEP;
 437
 438         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 439
 440         /* disable interrupts while stepping */
 441         mips32_enable_interrupts(target, 0);
 442
 443         /* exit debug mode */
 444         mips_ejtag_exit_debug(ejtag_info);
 445
 446         /* registers are now invalid */
 447         register_cache_invalidate(mips32->core_cache);
 448
 449         if (breakpoint)
 450                 mips_m4k_set_breakpoint(target, breakpoint);
 451
 452         LOG_DEBUG("target stepped ");
 453
 454         mips_m4k_debug_entry(target);
 455         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 456
 457         return ERROR_OK;
 458 }
 459
 460 void mips_m4k_enable_breakpoints(struct target *target)
 461 {
 462         struct breakpoint *breakpoint = target->breakpoints;
 463
 464         /* set any pending breakpoints */
 465         while (breakpoint)
 466         {
 467                 if (breakpoint->set == 0)
 468                         mips_m4k_set_breakpoint(target, breakpoint);
 469                 breakpoint = breakpoint->next;
 470         }
 471 }
 472
 473 int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 474 {
 475         struct mips32_common *mips32 = target_to_mips32(target);
 476         struct mips32_comparator * comparator_list = mips32->inst_break_list;
 477         int retval;
 478
 479         if (breakpoint->set)
 480         {
 481                 LOG_WARNING("breakpoint already set");
 482                 return ERROR_OK;
 483         }
 484
 485         if (breakpoint->type == BKPT_HARD)
 486         {
 487                 int bp_num = 0;
 488
 489                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 490                         bp_num++;
 491                 if (bp_num >= mips32->num_inst_bpoints)
 492                 {
 493                         LOG_ERROR("Can not find free FP Comparator(bpid: %d)",
 494                                           breakpoint->unique_id );
 495                         return ERROR_FAIL;
 496                 }
 497                 breakpoint->set = bp_num + 1;
 498                 comparator_list[bp_num].used = 1;
 499                 comparator_list[bp_num].bp_value = breakpoint->address;
 500                 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
 501                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
 502                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
 503                 LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
 504                                   breakpoint->unique_id,
 505                                   bp_num, comparator_list[bp_num].bp_value);
 506         }
 507         else if (breakpoint->type == BKPT_SOFT)
 508         {
 509                 LOG_DEBUG("bpid: %d", breakpoint->unique_id );
 510                 if (breakpoint->length == 4)
 511                 {
 512                         uint32_t verify = 0xffffffff;
 513
 514                         if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 515                                         breakpoint->orig_instr)) != ERROR_OK)
 516                         {
 517                                 return retval;
 518                         }
 519                         if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
 520                         {
 521                                 return retval;
 522                         }
 523
 524                         if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 525                         {
 526                                 return retval;
 527                         }
 528                         if (verify != MIPS32_SDBBP)
 529                         {
 530                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 531                                 return ERROR_OK;
 532                         }
 533                 }
 534                 else
 535                 {
 536                         uint16_t verify = 0xffff;
 537
 538                         if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 539                                         breakpoint->orig_instr)) != ERROR_OK)
 540                         {
 541                                 return retval;
 542                         }
 543                         if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
 544                         {
 545                                 return retval;
 546                         }
 547
 548                         if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 549                         {
 550                                 return retval;
 551                         }
 552                         if (verify != MIPS16_SDBBP)
 553                         {
 554                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 555                                 return ERROR_OK;
 556                         }
 557                 }
 558
 559                 breakpoint->set = 20; /* Any nice value but 0 */
 560         }
 561
 562         return ERROR_OK;
 563 }
 564
 565 int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 566 {
 567         /* get pointers to arch-specific information */
 568         struct mips32_common *mips32 = target_to_mips32(target);
 569         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 570         int retval;
 571
 572         if (!breakpoint->set)
 573         {
 574                 LOG_WARNING("breakpoint not set");
 575                 return ERROR_OK;
 576         }
 577
 578         if (breakpoint->type == BKPT_HARD)
 579         {
 580                 int bp_num = breakpoint->set - 1;
 581                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
 582                 {
 583                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
 584                                           breakpoint->unique_id);
 585                         return ERROR_OK;
 586                 }
 587                 LOG_DEBUG("bpid: %d - releasing hw: %d",
 588                                   breakpoint->unique_id,
 589                                   bp_num );
 590                 comparator_list[bp_num].used = 0;
 591                 comparator_list[bp_num].bp_value = 0;
 592                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
 593
 594         }
 595         else
 596         {
 597                 /* restore original instruction (kept in target endianness) */
 598                 LOG_DEBUG("bpid: %d", breakpoint->unique_id);
 599                 if (breakpoint->length == 4)
 600                 {
 601                         uint32_t current_instr;
 602
 603                         /* check that user program has not modified breakpoint instruction */
 604                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1,
 605                                         (uint8_t*)&current_instr)) != ERROR_OK)
 606                         {
 607                                 return retval;
 608                         }
 609                         if (current_instr == MIPS32_SDBBP)
 610                         {
 611                                 if ((retval = target_write_memory(target, breakpoint->address, 4, 1,
 612                                                 breakpoint->orig_instr)) != ERROR_OK)
 613                                 {
 614                                         return retval;
 615                                 }
 616                         }
 617                 }
 618                 else
 619                 {
 620                         uint16_t current_instr;
 621
 622                         /* check that user program has not modified breakpoint instruction */
 623                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1,
 624                                         (uint8_t*)&current_instr)) != ERROR_OK)
 625                         {
 626                                 return retval;
 627                         }
 628
 629                         if (current_instr == MIPS16_SDBBP)
 630                         {
 631                                 if ((retval = target_write_memory(target, breakpoint->address, 2, 1,
 632                                                 breakpoint->orig_instr)) != ERROR_OK)
 633                                 {
 634                                         return retval;
 635                                 }
 636                         }
 637                 }
 638         }
 639         breakpoint->set = 0;
 640
 641         return ERROR_OK;
 642 }
 643
 644 int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 645 {
 646         struct mips32_common *mips32 = target_to_mips32(target);
 647
 648         if (breakpoint->type == BKPT_HARD)
 649         {
 650                 if (mips32->num_inst_bpoints_avail < 1)
 651                 {
 652                         LOG_INFO("no hardware breakpoint available");
 653                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 654                 }
 655
 656                 mips32->num_inst_bpoints_avail--;
 657         }
 658
 659         mips_m4k_set_breakpoint(target, breakpoint);
 660
 661         return ERROR_OK;
 662 }
 663
 664 int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 665 {
 666         /* get pointers to arch-specific information */
 667         struct mips32_common *mips32 = target_to_mips32(target);
 668
 669         if (target->state != TARGET_HALTED)
 670         {
 671                 LOG_WARNING("target not halted");
 672                 return ERROR_TARGET_NOT_HALTED;
 673         }
 674
 675         if (breakpoint->set)
 676         {
 677                 mips_m4k_unset_breakpoint(target, breakpoint);
 678         }
 679
 680         if (breakpoint->type == BKPT_HARD)
 681                 mips32->num_inst_bpoints_avail++;
 682
 683         return ERROR_OK;
 684 }
 685
 686 int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 687 {
 688         struct mips32_common *mips32 = target_to_mips32(target);
 689         struct mips32_comparator *comparator_list = mips32->data_break_list;
 690         int wp_num = 0;
 691         /*
 692          * watchpoint enabled, ignore all byte lanes in value register
 693          * and exclude both load and store accesses from  watchpoint
 694          * condition evaluation
 695         */
 696         int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
 697                 (0xff << EJTAG_DBCn_BLM_SHIFT);
 698
 699         if (watchpoint->set)
 700         {
 701                 LOG_WARNING("watchpoint already set");
 702                 return ERROR_OK;
 703         }
 704
 705         while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 706                 wp_num++;
 707         if (wp_num >= mips32->num_data_bpoints)
 708         {
 709                 LOG_ERROR("Can not find free FP Comparator");
 710                 return ERROR_FAIL;
 711         }
 712
 713         if (watchpoint->length != 4)
 714         {
 715                 LOG_ERROR("Only watchpoints of length 4 are supported");
 716                 return ERROR_TARGET_UNALIGNED_ACCESS;
 717         }
 718
 719         if (watchpoint->address % 4)
 720         {
 721                 LOG_ERROR("Watchpoints address should be word aligned");
 722                 return ERROR_TARGET_UNALIGNED_ACCESS;
 723         }
 724
 725         switch (watchpoint->rw)
 726         {
 727                 case WPT_READ:
 728                         enable &= ~EJTAG_DBCn_NOLB;
 729                         break;
 730                 case WPT_WRITE:
 731                         enable &= ~EJTAG_DBCn_NOSB;
 732                         break;
 733                 case WPT_ACCESS:
 734                         enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
 735                         break;
 736                 default:
 737                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 738         }
 739
 740         watchpoint->set = wp_num + 1;
 741         comparator_list[wp_num].used = 1;
 742         comparator_list[wp_num].bp_value = watchpoint->address;
 743         target_write_u32(target, comparator_list[wp_num].reg_address, comparator_list[wp_num].bp_value);
 744         target_write_u32(target, comparator_list[wp_num].reg_address + 0x08, 0x00000000);
 745         target_write_u32(target, comparator_list[wp_num].reg_address + 0x10, 0x00000000);
 746         target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
 747         target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
 748         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 749
 750         return ERROR_OK;
 751 }
 752
 753 int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
 754 {
 755         /* get pointers to arch-specific information */
 756         struct mips32_common *mips32 = target_to_mips32(target);
 757         struct mips32_comparator *comparator_list = mips32->data_break_list;
 758
 759         if (!watchpoint->set)
 760         {
 761                 LOG_WARNING("watchpoint not set");
 762                 return ERROR_OK;
 763         }
 764
 765         int wp_num = watchpoint->set - 1;
 766         if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints))
 767         {
 768                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 769                 return ERROR_OK;
 770         }
 771         comparator_list[wp_num].used = 0;
 772         comparator_list[wp_num].bp_value = 0;
 773         target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, 0);
 774         watchpoint->set = 0;
 775
 776         return ERROR_OK;
 777 }
 778
 779 int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 780 {
 781         struct mips32_common *mips32 = target_to_mips32(target);
 782
 783         if (mips32->num_data_bpoints_avail < 1)
 784         {
 785                 LOG_INFO("no hardware watchpoints available");
 786                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 787         }
 788
 789         mips32->num_data_bpoints_avail--;
 790
 791         mips_m4k_set_watchpoint(target, watchpoint);
 792         return ERROR_OK;
 793 }
 794
 795 int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 796 {
 797         /* get pointers to arch-specific information */
 798         struct mips32_common *mips32 = target_to_mips32(target);
 799
 800         if (target->state != TARGET_HALTED)
 801         {
 802                 LOG_WARNING("target not halted");
 803                 return ERROR_TARGET_NOT_HALTED;
 804         }
 805
 806         if (watchpoint->set)
 807         {
 808                 mips_m4k_unset_watchpoint(target, watchpoint);
 809         }
 810
 811         mips32->num_data_bpoints_avail++;
 812
 813         return ERROR_OK;
 814 }
 815
 816 void mips_m4k_enable_watchpoints(struct target *target)
 817 {
 818         struct watchpoint *watchpoint = target->watchpoints;
 819
 820         /* set any pending watchpoints */
 821         while (watchpoint)
 822         {
 823                 if (watchpoint->set == 0)
 824                         mips_m4k_set_watchpoint(target, watchpoint);
 825                 watchpoint = watchpoint->next;
 826         }
 827 }
 828
 829 int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 830 {
 831         struct mips32_common *mips32 = target_to_mips32(target);
 832         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 833
 834         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 835
 836         if (target->state != TARGET_HALTED)
 837         {
 838                 LOG_WARNING("target not halted");
 839                 return ERROR_TARGET_NOT_HALTED;
 840         }
 841
 842         /* sanitize arguments */
 843         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 844                 return ERROR_INVALID_ARGUMENTS;
 845
 846         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 847                 return ERROR_TARGET_UNALIGNED_ACCESS;
 848
 849         /* if noDMA off, use DMAACC mode for memory read */
 850         int retval;
 851         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 852                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 853         else
 854                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 855         if (ERROR_OK != retval)
 856                 return retval;
 857
 858         return ERROR_OK;
 859 }
 860
 861 int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size,
 862                 uint32_t count, uint8_t *buffer)
 863 {
 864         struct mips32_common *mips32 = target_to_mips32(target);
 865         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 866
 867         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
 868                         address, size, count);
 869
 870         if (target->state != TARGET_HALTED)
 871         {
 872                 LOG_WARNING("target not halted");
 873                 return ERROR_TARGET_NOT_HALTED;
 874         }
 875
 876         /* sanitize arguments */
 877         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 878                 return ERROR_INVALID_ARGUMENTS;
 879
 880         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 881                 return ERROR_TARGET_UNALIGNED_ACCESS;
 882
 883         /* if noDMA off, use DMAACC mode for memory write */
 884         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 885                 return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 886         else
 887                 return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 888 }
 889
 890 int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
 891 {
 892         mips32_build_reg_cache(target);
 893
 894         return ERROR_OK;
 895 }
 896
 897 int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
 898                 struct jtag_tap *tap)
 899 {
 900         struct mips32_common *mips32 = &mips_m4k->mips32;
 901
 902         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 903
 904         /* initialize mips4k specific info */
 905         mips32_init_arch_info(target, mips32, tap);
 906         mips32->arch_info = mips_m4k;
 907
 908         return ERROR_OK;
 909 }
 910
 911 int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 912 {
 913         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
 914
 915         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 916
 917         return ERROR_OK;
 918 }
 919
 920 int mips_m4k_examine(struct target *target)
 921 {
 922         int retval;
 923         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 924         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 925         uint32_t idcode = 0;
 926
 927         if (!target_was_examined(target))
 928         {
 929                 mips_ejtag_get_idcode(ejtag_info, &idcode);
 930                 ejtag_info->idcode = idcode;
 931
 932                 if (((idcode >> 1) & 0x7FF) == 0x29)
 933                 {
 934                         /* we are using a pic32mx so select ejtag port
 935                          * as it is not selected by default */
 936                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
 937                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 938                         mips_m4k->is_pic32mx = true;
 939                 }
 940         }
 941
 942         /* init rest of ejtag interface */
 943         if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 944                 return retval;
 945
 946         if ((retval = mips32_examine(target)) != ERROR_OK)
 947                 return retval;
 948
 949         return ERROR_OK;
 950 }
 951
 952 int mips_m4k_bulk_write_memory(struct target *target, uint32_t address,
 953                 uint32_t count, uint8_t *buffer)
 954 {
 955         struct mips32_common *mips32 = target_to_mips32(target);
 956         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 957         struct working_area *source;
 958         int retval;
 959         int write = 1;
 960
 961         LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count);
 962
 963         if (target->state != TARGET_HALTED)
 964         {
 965                 LOG_WARNING("target not halted");
 966                 return ERROR_TARGET_NOT_HALTED;
 967         }
 968
 969         /* check alignment */
 970         if (address & 0x3u)
 971                 return ERROR_TARGET_UNALIGNED_ACCESS;
 972
 973         /* Get memory for block write handler */
 974         retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &source);
 975         if (retval != ERROR_OK)
 976         {
 977                 LOG_WARNING("No working area available, falling back to non-bulk write");
 978                 return mips_m4k_write_memory(target, address, 4, count, buffer);
 979         }
 980
 981         /* TAP data register is loaded LSB first (little endian) */
 982         if (target->endianness == TARGET_BIG_ENDIAN)
 983         {
 984                 uint32_t i, t32;
 985                 for(i = 0; i < (count * 4); i += 4)
 986                 {
 987                         t32 = be_to_h_u32((uint8_t *) &buffer[i]);
 988                         h_u32_to_le(&buffer[i], t32);
 989                 }
 990         }
 991
 992         retval = mips32_pracc_fastdata_xfer(ejtag_info, source, write, address,
 993                         count, (uint32_t*) buffer);
 994         if (retval != ERROR_OK)
 995         {
 996                 /* FASTDATA access failed, try normal memory write */
 997                 LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write");
 998                 retval = mips_m4k_write_memory(target, address, 4, count, buffer);
 999         }
1000
1001         if (source)
1002                 target_free_working_area(target, source);
1003
1004         return retval;
1005 }
1006
1007 struct target_type mips_m4k_target =
1008 {
1009         .name = "mips_m4k",
1010
1011         .poll = mips_m4k_poll,
1012         .arch_state = mips32_arch_state,
1013
1014         .target_request_data = NULL,
1015
1016         .halt = mips_m4k_halt,
1017         .resume = mips_m4k_resume,
1018         .step = mips_m4k_step,
1019
1020         .assert_reset = mips_m4k_assert_reset,
1021         .deassert_reset = mips_m4k_deassert_reset,
1022         .soft_reset_halt = mips_m4k_soft_reset_halt,
1023
1024         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1025
1026         .read_memory = mips_m4k_read_memory,
1027         .write_memory = mips_m4k_write_memory,
1028         .bulk_write_memory = mips_m4k_bulk_write_memory,
1029         .checksum_memory = mips32_checksum_memory,
1030         .blank_check_memory = mips32_blank_check_memory,
1031
1032         .run_algorithm = mips32_run_algorithm,
1033
1034         .add_breakpoint = mips_m4k_add_breakpoint,
1035         .remove_breakpoint = mips_m4k_remove_breakpoint,
1036         .add_watchpoint = mips_m4k_add_watchpoint,
1037         .remove_watchpoint = mips_m4k_remove_watchpoint,
1038
1039         .target_create = mips_m4k_target_create,
1040         .init_target = mips_m4k_init_target,
1041         .examine = mips_m4k_examine,
1042 };