git.sur5r.net Git - openocd/blob - src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "mips32.h"
  27 #include "mips_m4k.h"
  28 #include "mips32_dmaacc.h"
  29 #include "target_type.h"
  30
  31
  32 /* cli handling */
  33
  34 /* forward declarations */
  35 int mips_m4k_poll(target_t *target);
  36 int mips_m4k_halt(struct target_s *target);
  37 int mips_m4k_soft_reset_halt(struct target_s *target);
  38 int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
  39 int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
  40 int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  41 int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  42 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
  43 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  44 int mips_m4k_quit(void);
  45 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
  46
  47 int mips_m4k_examine(struct target_s *target);
  48 int mips_m4k_assert_reset(target_t *target);
  49 int mips_m4k_deassert_reset(target_t *target);
  50 int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum);
  51
  52 target_type_t mips_m4k_target =
  53 {
  54         .name = "mips_m4k",
  55
  56         .poll = mips_m4k_poll,
  57         .arch_state = mips32_arch_state,
  58
  59         .target_request_data = NULL,
  60
  61         .halt = mips_m4k_halt,
  62         .resume = mips_m4k_resume,
  63         .step = mips_m4k_step,
  64
  65         .assert_reset = mips_m4k_assert_reset,
  66         .deassert_reset = mips_m4k_deassert_reset,
  67         .soft_reset_halt = mips_m4k_soft_reset_halt,
  68
  69         .get_gdb_reg_list = mips32_get_gdb_reg_list,
  70
  71         .read_memory = mips_m4k_read_memory,
  72         .write_memory = mips_m4k_write_memory,
  73         .bulk_write_memory = mips_m4k_bulk_write_memory,
  74         .checksum_memory = mips_m4k_checksum_memory,
  75         .blank_check_memory = NULL,
  76
  77         .run_algorithm = mips32_run_algorithm,
  78
  79         .add_breakpoint = mips_m4k_add_breakpoint,
  80         .remove_breakpoint = mips_m4k_remove_breakpoint,
  81         .add_watchpoint = mips_m4k_add_watchpoint,
  82         .remove_watchpoint = mips_m4k_remove_watchpoint,
  83
  84         .register_commands = mips_m4k_register_commands,
  85         .target_create = mips_m4k_target_create,
  86         .init_target = mips_m4k_init_target,
  87         .examine = mips_m4k_examine,
  88         .quit = mips_m4k_quit
  89 };
  90
  91 int mips_m4k_examine_debug_reason(target_t *target)
  92 {
  93         uint32_t break_status;
  94         int retval;
  95
  96         if ((target->debug_reason != DBG_REASON_DBGRQ)
  97                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
  98         {
  99                 /* get info about inst breakpoint support */
 100                 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
 101                         return retval;
 102                 if (break_status & 0x1f)
 103                 {
 104                         /* we have halted on a  breakpoint */
 105                         if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 106                                 return retval;
 107                         target->debug_reason = DBG_REASON_BREAKPOINT;
 108                 }
 109
 110                 /* get info about data breakpoint support */
 111                 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
 112                         return retval;
 113                 if (break_status & 0x1f)
 114                 {
 115                         /* we have halted on a  breakpoint */
 116                         if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
 117                                 return retval;
 118                         target->debug_reason = DBG_REASON_WATCHPOINT;
 119                 }
 120         }
 121
 122         return ERROR_OK;
 123 }
 124
 125 int mips_m4k_debug_entry(target_t *target)
 126 {
 127         mips32_common_t *mips32 = target->arch_info;
 128         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 129         uint32_t debug_reg;
 130
 131         /* read debug register */
 132         mips_ejtag_read_debug(ejtag_info, &debug_reg);
 133
 134         /* make sure break uit configured */
 135         mips32_configure_break_unit(target);
 136
 137         /* attempt to find halt reason */
 138         mips_m4k_examine_debug_reason(target);
 139
 140         /* clear single step if active */
 141         if (debug_reg & EJTAG_DEBUG_DSS)
 142         {
 143                 /* stopped due to single step - clear step bit */
 144                 mips_ejtag_config_step(ejtag_info, 0);
 145         }
 146
 147         mips32_save_context(target);
 148
 149         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 150                 *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
 151                   Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
 152
 153         return ERROR_OK;
 154 }
 155
 156 int mips_m4k_poll(target_t *target)
 157 {
 158         int retval;
 159         mips32_common_t *mips32 = target->arch_info;
 160         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 161         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 162
 163         /* read ejtag control reg */
 164         jtag_set_end_state(TAP_IDLE);
 165         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 166         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 167
 168         /* clear this bit before handling polling
 169          * as after reset registers will read zero */
 170         if (ejtag_ctrl & EJTAG_CTRL_ROCC)
 171         {
 172                 /* we have detected a reset, clear flag
 173                  * otherwise ejtag will not work */
 174                 jtag_set_end_state(TAP_IDLE);
 175                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 176
 177                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 178                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 179                 LOG_DEBUG("Reset Detected");
 180         }
 181
 182         /* check for processor halted */
 183         if (ejtag_ctrl & EJTAG_CTRL_BRKST)
 184         {
 185                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 186                 {
 187                         jtag_set_end_state(TAP_IDLE);
 188                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 189
 190                         target->state = TARGET_HALTED;
 191
 192                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 193                                 return retval;
 194
 195                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 196                 }
 197                 else if (target->state == TARGET_DEBUG_RUNNING)
 198                 {
 199                         target->state = TARGET_HALTED;
 200
 201                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 202                                 return retval;
 203
 204                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 205                 }
 206         }
 207         else
 208         {
 209                 target->state = TARGET_RUNNING;
 210         }
 211
 212 //      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl);
 213
 214         return ERROR_OK;
 215 }
 216
 217 int mips_m4k_halt(struct target_s *target)
 218 {
 219         mips32_common_t *mips32 = target->arch_info;
 220         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 221
 222         LOG_DEBUG("target->state: %s",
 223                   Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
 224
 225         if (target->state == TARGET_HALTED)
 226         {
 227                 LOG_DEBUG("target was already halted");
 228                 return ERROR_OK;
 229         }
 230
 231         if (target->state == TARGET_UNKNOWN)
 232         {
 233                 LOG_WARNING("target was in unknown state when halt was requested");
 234         }
 235
 236         if (target->state == TARGET_RESET)
 237         {
 238                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 239                 {
 240                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 241                         return ERROR_TARGET_FAILURE;
 242                 }
 243                 else
 244                 {
 245                         /* we came here in a reset_halt or reset_init sequence
 246                          * debug entry was already prepared in mips32_prepare_reset_halt()
 247                          */
 248                         target->debug_reason = DBG_REASON_DBGRQ;
 249
 250                         return ERROR_OK;
 251                 }
 252         }
 253
 254         /* break processor */
 255         mips_ejtag_enter_debug(ejtag_info);
 256
 257         target->debug_reason = DBG_REASON_DBGRQ;
 258
 259         return ERROR_OK;
 260 }
 261
 262 int mips_m4k_assert_reset(target_t *target)
 263 {
 264         mips32_common_t *mips32 = target->arch_info;
 265         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 266
 267         LOG_DEBUG("target->state: %s",
 268                 Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
 269
 270         enum reset_types jtag_reset_config = jtag_get_reset_config();
 271         if (!(jtag_reset_config & RESET_HAS_SRST))
 272         {
 273                 LOG_ERROR("Can't assert SRST");
 274                 return ERROR_FAIL;
 275         }
 276
 277         if (target->reset_halt)
 278         {
 279                 /* use hardware to catch reset */
 280                 jtag_set_end_state(TAP_IDLE);
 281                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
 282         }
 283         else
 284         {
 285                 jtag_set_end_state(TAP_IDLE);
 286                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 287         }
 288
 289         if (strcmp(target->variant, "ejtag_srst") == 0)
 290         {
 291                 uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 292                 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 293                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 294                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 295         }
 296         else
 297         {
 298                 /* here we should issue a srst only, but we may have to assert trst as well */
 299                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 300                 {
 301                         jtag_add_reset(1, 1);
 302                 }
 303                 else
 304                 {
 305                         jtag_add_reset(0, 1);
 306                 }
 307         }
 308
 309         target->state = TARGET_RESET;
 310         jtag_add_sleep(50000);
 311
 312         mips32_invalidate_core_regs(target);
 313
 314         if (target->reset_halt)
 315         {
 316                 int retval;
 317                 if ((retval = target_halt(target)) != ERROR_OK)
 318                         return retval;
 319         }
 320
 321         return ERROR_OK;
 322 }
 323
 324 int mips_m4k_deassert_reset(target_t *target)
 325 {
 326         LOG_DEBUG("target->state: %s",
 327                 Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
 328
 329         /* deassert reset lines */
 330         jtag_add_reset(0, 0);
 331
 332         return ERROR_OK;
 333 }
 334
 335 int mips_m4k_soft_reset_halt(struct target_s *target)
 336 {
 337         /* TODO */
 338         return ERROR_OK;
 339 }
 340
 341 int mips_m4k_single_step_core(target_t *target)
 342 {
 343         mips32_common_t *mips32 = target->arch_info;
 344         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 345
 346         /* configure single step mode */
 347         mips_ejtag_config_step(ejtag_info, 1);
 348
 349         /* disable interrupts while stepping */
 350         mips32_enable_interrupts(target, 0);
 351
 352         /* exit debug mode */
 353         mips_ejtag_exit_debug(ejtag_info);
 354
 355         mips_m4k_debug_entry(target);
 356
 357         return ERROR_OK;
 358 }
 359
 360 int mips_m4k_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 361 {
 362         mips32_common_t *mips32 = target->arch_info;
 363         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 364         breakpoint_t *breakpoint = NULL;
 365         uint32_t resume_pc;
 366
 367         if (target->state != TARGET_HALTED)
 368         {
 369                 LOG_WARNING("target not halted");
 370                 return ERROR_TARGET_NOT_HALTED;
 371         }
 372
 373         if (!debug_execution)
 374         {
 375                 target_free_all_working_areas(target);
 376                 mips_m4k_enable_breakpoints(target);
 377                 mips_m4k_enable_watchpoints(target);
 378         }
 379
 380         /* current = 1: continue on current pc, otherwise continue at <address> */
 381         if (!current)
 382         {
 383                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 384                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 385                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 386         }
 387
 388         resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 389
 390         mips32_restore_context(target);
 391
 392         /* the front-end may request us not to handle breakpoints */
 393         if (handle_breakpoints)
 394         {
 395                 /* Single step past breakpoint at current address */
 396                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 397                 {
 398                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 399                         mips_m4k_unset_breakpoint(target, breakpoint);
 400                         mips_m4k_single_step_core(target);
 401                         mips_m4k_set_breakpoint(target, breakpoint);
 402                 }
 403         }
 404
 405         /* enable interrupts if we are running */
 406         mips32_enable_interrupts(target, !debug_execution);
 407
 408         /* exit debug mode */
 409         mips_ejtag_exit_debug(ejtag_info);
 410         target->debug_reason = DBG_REASON_NOTHALTED;
 411
 412         /* registers are now invalid */
 413         mips32_invalidate_core_regs(target);
 414
 415         if (!debug_execution)
 416         {
 417                 target->state = TARGET_RUNNING;
 418                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 419                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 420         }
 421         else
 422         {
 423                 target->state = TARGET_DEBUG_RUNNING;
 424                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 425                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 426         }
 427
 428         return ERROR_OK;
 429 }
 430
 431 int mips_m4k_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 432 {
 433         /* get pointers to arch-specific information */
 434         mips32_common_t *mips32 = target->arch_info;
 435         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 436         breakpoint_t *breakpoint = NULL;
 437
 438         if (target->state != TARGET_HALTED)
 439         {
 440                 LOG_WARNING("target not halted");
 441                 return ERROR_TARGET_NOT_HALTED;
 442         }
 443
 444         /* current = 1: continue on current pc, otherwise continue at <address> */
 445         if (!current)
 446                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 447
 448         /* the front-end may request us not to handle breakpoints */
 449         if (handle_breakpoints)
 450                 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
 451                         mips_m4k_unset_breakpoint(target, breakpoint);
 452
 453         /* restore context */
 454         mips32_restore_context(target);
 455
 456         /* configure single step mode */
 457         mips_ejtag_config_step(ejtag_info, 1);
 458
 459         target->debug_reason = DBG_REASON_SINGLESTEP;
 460
 461         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 462
 463         /* disable interrupts while stepping */
 464         mips32_enable_interrupts(target, 0);
 465
 466         /* exit debug mode */
 467         mips_ejtag_exit_debug(ejtag_info);
 468
 469         /* registers are now invalid */
 470         mips32_invalidate_core_regs(target);
 471
 472         if (breakpoint)
 473                 mips_m4k_set_breakpoint(target, breakpoint);
 474
 475         LOG_DEBUG("target stepped ");
 476
 477         mips_m4k_debug_entry(target);
 478         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 479
 480         return ERROR_OK;
 481 }
 482
 483 void mips_m4k_enable_breakpoints(struct target_s *target)
 484 {
 485         breakpoint_t *breakpoint = target->breakpoints;
 486
 487         /* set any pending breakpoints */
 488         while (breakpoint)
 489         {
 490                 if (breakpoint->set == 0)
 491                         mips_m4k_set_breakpoint(target, breakpoint);
 492                 breakpoint = breakpoint->next;
 493         }
 494 }
 495
 496 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 497 {
 498         mips32_common_t *mips32 = target->arch_info;
 499         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 500         int retval;
 501
 502         if (breakpoint->set)
 503         {
 504                 LOG_WARNING("breakpoint already set");
 505                 return ERROR_OK;
 506         }
 507
 508         if (breakpoint->type == BKPT_HARD)
 509         {
 510                 int bp_num = 0;
 511
 512                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 513                         bp_num++;
 514                 if (bp_num >= mips32->num_inst_bpoints)
 515                 {
 516                         LOG_DEBUG("ERROR Can not find free FP Comparator");
 517                         LOG_WARNING("ERROR Can not find free FP Comparator");
 518                         exit(-1);
 519                 }
 520                 breakpoint->set = bp_num + 1;
 521                 comparator_list[bp_num].used = 1;
 522                 comparator_list[bp_num].bp_value = breakpoint->address;
 523                 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
 524                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
 525                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
 526                 LOG_DEBUG("bp_num %i bp_value 0x%" PRIx32 "", bp_num, comparator_list[bp_num].bp_value);
 527         }
 528         else if (breakpoint->type == BKPT_SOFT)
 529         {
 530                 if (breakpoint->length == 4)
 531                 {
 532                         uint32_t verify = 0xffffffff;
 533
 534                         if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 535                         {
 536                                 return retval;
 537                         }
 538                         if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
 539                         {
 540                                 return retval;
 541                         }
 542
 543                         if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 544                         {
 545                                 return retval;
 546                         }
 547                         if (verify != MIPS32_SDBBP)
 548                         {
 549                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 550                                 return ERROR_OK;
 551                         }
 552                 }
 553                 else
 554                 {
 555                         uint16_t verify = 0xffff;
 556
 557                         if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 558                         {
 559                                 return retval;
 560                         }
 561                         if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
 562                         {
 563                                 return retval;
 564                         }
 565
 566                         if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 567                         {
 568                                 return retval;
 569                         }
 570                         if (verify != MIPS16_SDBBP)
 571                         {
 572                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 573                                 return ERROR_OK;
 574                         }
 575                 }
 576
 577                 breakpoint->set = 20; /* Any nice value but 0 */
 578         }
 579
 580         return ERROR_OK;
 581 }
 582
 583 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 584 {
 585         /* get pointers to arch-specific information */
 586         mips32_common_t *mips32 = target->arch_info;
 587         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 588         int retval;
 589
 590         if (!breakpoint->set)
 591         {
 592                 LOG_WARNING("breakpoint not set");
 593                 return ERROR_OK;
 594         }
 595
 596         if (breakpoint->type == BKPT_HARD)
 597         {
 598                 int bp_num = breakpoint->set - 1;
 599                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
 600                 {
 601                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 602                         return ERROR_OK;
 603                 }
 604                 comparator_list[bp_num].used = 0;
 605                 comparator_list[bp_num].bp_value = 0;
 606                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
 607         }
 608         else
 609         {
 610                 /* restore original instruction (kept in target endianness) */
 611                 if (breakpoint->length == 4)
 612                 {
 613                         uint32_t current_instr;
 614
 615                         /* check that user program has not modified breakpoint instruction */
 616                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 617                         {
 618                                 return retval;
 619                         }
 620                         if (current_instr == MIPS32_SDBBP)
 621                         {
 622                                 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 623                                 {
 624                                         return retval;
 625                                 }
 626                         }
 627                 }
 628                 else
 629                 {
 630                         uint16_t current_instr;
 631
 632                         /* check that user program has not modified breakpoint instruction */
 633                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
 634                         {
 635                                 return retval;
 636                         }
 637
 638                         if (current_instr == MIPS16_SDBBP)
 639                         {
 640                                 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 641                                 {
 642                                         return retval;
 643                                 }
 644                         }
 645                 }
 646         }
 647         breakpoint->set = 0;
 648
 649         return ERROR_OK;
 650 }
 651
 652 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 653 {
 654         mips32_common_t *mips32 = target->arch_info;
 655
 656         if (breakpoint->type == BKPT_HARD)
 657         {
 658                 if (mips32->num_inst_bpoints_avail < 1)
 659                 {
 660                         LOG_INFO("no hardware breakpoint available");
 661                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 662                 }
 663
 664                 mips32->num_inst_bpoints_avail--;
 665         }
 666
 667         mips_m4k_set_breakpoint(target, breakpoint);
 668
 669         return ERROR_OK;
 670 }
 671
 672 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 673 {
 674         /* get pointers to arch-specific information */
 675         mips32_common_t *mips32 = target->arch_info;
 676
 677         if (target->state != TARGET_HALTED)
 678         {
 679                 LOG_WARNING("target not halted");
 680                 return ERROR_TARGET_NOT_HALTED;
 681         }
 682
 683         if (breakpoint->set)
 684         {
 685                 mips_m4k_unset_breakpoint(target, breakpoint);
 686         }
 687
 688         if (breakpoint->type == BKPT_HARD)
 689                 mips32->num_inst_bpoints_avail++;
 690
 691         return ERROR_OK;
 692 }
 693
 694 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 695 {
 696         /* TODO */
 697         return ERROR_OK;
 698 }
 699
 700 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 701 {
 702         /* TODO */
 703         return ERROR_OK;
 704 }
 705
 706 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 707 {
 708         /* TODO */
 709         return ERROR_OK;
 710 }
 711
 712 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 713 {
 714         /* TODO */
 715         return ERROR_OK;
 716 }
 717
 718 void mips_m4k_enable_watchpoints(struct target_s *target)
 719 {
 720         watchpoint_t *watchpoint = target->watchpoints;
 721
 722         /* set any pending watchpoints */
 723         while (watchpoint)
 724         {
 725                 if (watchpoint->set == 0)
 726                         mips_m4k_set_watchpoint(target, watchpoint);
 727                 watchpoint = watchpoint->next;
 728         }
 729 }
 730
 731 int mips_m4k_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 732 {
 733         mips32_common_t *mips32 = target->arch_info;
 734         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 735
 736         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 737
 738         if (target->state != TARGET_HALTED)
 739         {
 740                 LOG_WARNING("target not halted");
 741                 return ERROR_TARGET_NOT_HALTED;
 742         }
 743
 744         /* sanitize arguments */
 745         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 746                 return ERROR_INVALID_ARGUMENTS;
 747
 748         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 749                 return ERROR_TARGET_UNALIGNED_ACCESS;
 750
 751         /* if noDMA off, use DMAACC mode for memory read */
 752         int retval;
 753         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 754                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 755         else
 756                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 757         if (ERROR_OK != retval)
 758                 return retval;
 759
 760         /* TAP data register is loaded LSB first (little endian) */
 761         if (target->endianness == TARGET_BIG_ENDIAN)
 762         {
 763                 uint32_t i, t32;
 764                 uint16_t t16;
 765
 766                 for (i = 0; i < (count*size); i += size)
 767                 {
 768                         switch (size)
 769                         {
 770                                 case 4:
 771                                         t32 = le_to_h_u32(&buffer[i]);
 772                                         h_u32_to_be(&buffer[i], t32);
 773                                         break;
 774                                 case 2:
 775                                         t16 = le_to_h_u16(&buffer[i]);
 776                                         h_u16_to_be(&buffer[i], t16);
 777                                         break;
 778                         }
 779                 }
 780         }
 781
 782         return ERROR_OK;
 783 }
 784
 785 int mips_m4k_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 786 {
 787         mips32_common_t *mips32 = target->arch_info;
 788         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 789
 790         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 791
 792         if (target->state != TARGET_HALTED)
 793         {
 794                 LOG_WARNING("target not halted");
 795                 return ERROR_TARGET_NOT_HALTED;
 796         }
 797
 798         /* sanitize arguments */
 799         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 800                 return ERROR_INVALID_ARGUMENTS;
 801
 802         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 803                 return ERROR_TARGET_UNALIGNED_ACCESS;
 804
 805         /* TAP data register is loaded LSB first (little endian) */
 806         if (target->endianness == TARGET_BIG_ENDIAN)
 807         {
 808                 uint32_t i, t32;
 809                 uint16_t t16;
 810
 811                 for (i = 0; i < (count*size); i += size)
 812                 {
 813                         switch (size)
 814                         {
 815                                 case 4:
 816                                         t32 = be_to_h_u32(&buffer[i]);
 817                                         h_u32_to_le(&buffer[i], t32);
 818                                         break;
 819                                 case 2:
 820                                         t16 = be_to_h_u16(&buffer[i]);
 821                                         h_u16_to_le(&buffer[i], t16);
 822                                         break;
 823                         }
 824                 }
 825         }
 826
 827         /* if noDMA off, use DMAACC mode for memory write */
 828         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
 829                 return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 830         else
 831                 return mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 832 }
 833
 834 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
 835 {
 836         int retval;
 837
 838         retval = mips32_register_commands(cmd_ctx);
 839         return retval;
 840 }
 841
 842 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 843 {
 844         mips32_build_reg_cache(target);
 845
 846         return ERROR_OK;
 847 }
 848
 849 int mips_m4k_quit(void)
 850 {
 851         return ERROR_OK;
 852 }
 853
 854 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
 855 {
 856         mips32_common_t *mips32 = &mips_m4k->mips32_common;
 857
 858         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 859
 860         /* initialize mips4k specific info */
 861         mips32_init_arch_info(target, mips32, tap);
 862         mips32->arch_info = mips_m4k;
 863
 864         return ERROR_OK;
 865 }
 866
 867 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
 868 {
 869         mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 870
 871         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 872
 873         return ERROR_OK;
 874 }
 875
 876 int mips_m4k_examine(struct target_s *target)
 877 {
 878         int retval;
 879         mips32_common_t *mips32 = target->arch_info;
 880         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 881         uint32_t idcode = 0;
 882
 883         if (!target_was_examined(target))
 884         {
 885                 mips_ejtag_get_idcode(ejtag_info, &idcode);
 886                 ejtag_info->idcode = idcode;
 887
 888                 if (((idcode >> 1) & 0x7FF) == 0x29)
 889                 {
 890                         /* we are using a pic32mx so select ejtag port
 891                          * as it is not selected by default */
 892                         mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
 893                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 894                 }
 895         }
 896
 897         /* init rest of ejtag interface */
 898         if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 899                 return retval;
 900
 901         if ((retval = mips32_examine(target)) != ERROR_OK)
 902                 return retval;
 903
 904         return ERROR_OK;
 905 }
 906
 907 int mips_m4k_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 908 {
 909         return mips_m4k_write_memory(target, address, 4, count, buffer);
 910 }
 911
 912 int mips_m4k_checksum_memory(target_t *target, uint32_t address, uint32_t size, uint32_t *checksum)
 913 {
 914         return ERROR_FAIL; /* use bulk read method */
 915 }