git.sur5r.net Git - openocd/blob - src/target/riscv/riscv.c

   1 #include <assert.h>
   2 #include <stdlib.h>
   3 #include <time.h>
   4
   5 #ifdef HAVE_CONFIG_H
   6 #include "config.h"
   7 #endif
   8
   9 #include "target/target.h"
  10 #include "target/algorithm.h"
  11 #include "target/target_type.h"
  12 #include "log.h"
  13 #include "jtag/jtag.h"
  14 #include "target/register.h"
  15 #include "target/breakpoints.h"
  16 #include "helper/time_support.h"
  17 #include "riscv.h"
  18 #include "gdb_regs.h"
  19 #include "rtos/rtos.h"
  20
  21 /**
  22  * Since almost everything can be accomplish by scanning the dbus register, all
  23  * functions here assume dbus is already selected. The exception are functions
  24  * called directly by OpenOCD, which can't assume anything about what's
  25  * currently in IR. They should set IR to dbus explicitly.
  26  */
  27
  28 /**
  29  * Code structure
  30  *
  31  * At the bottom of the stack are the OpenOCD JTAG functions:
  32  *              jtag_add_[id]r_scan
  33  *              jtag_execute_query
  34  *              jtag_add_runtest
  35  *
  36  * There are a few functions to just instantly shift a register and get its
  37  * value:
  38  *              dtmcontrol_scan
  39  *              idcode_scan
  40  *              dbus_scan
  41  *
  42  * Because doing one scan and waiting for the result is slow, most functions
  43  * batch up a bunch of dbus writes and then execute them all at once. They use
  44  * the scans "class" for this:
  45  *              scans_new
  46  *              scans_delete
  47  *              scans_execute
  48  *              scans_add_...
  49  * Usually you new(), call a bunch of add functions, then execute() and look
  50  * at the results by calling scans_get...()
  51  *
  52  * Optimized functions will directly use the scans class above, but slightly
  53  * lazier code will use the cache functions that in turn use the scans
  54  * functions:
  55  *              cache_get...
  56  *              cache_set...
  57  *              cache_write
  58  * cache_set... update a local structure, which is then synced to the target
  59  * with cache_write(). Only Debug RAM words that are actually changed are sent
  60  * to the target. Afterwards use cache_get... to read results.
  61  */
  62
  63 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  64 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  65
  66 #define DIM(x)          (sizeof(x)/sizeof(*x))
  67
  68 /* Constants for legacy SiFive hardware breakpoints. */
  69 #define CSR_BPCONTROL_X                 (1<<0)
  70 #define CSR_BPCONTROL_W                 (1<<1)
  71 #define CSR_BPCONTROL_R                 (1<<2)
  72 #define CSR_BPCONTROL_U                 (1<<3)
  73 #define CSR_BPCONTROL_S                 (1<<4)
  74 #define CSR_BPCONTROL_H                 (1<<5)
  75 #define CSR_BPCONTROL_M                 (1<<6)
  76 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  77 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  78
  79 #define DEBUG_ROM_START         0x800
  80 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  81 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  82 #define DEBUG_RAM_START         0x400
  83
  84 #define SETHALTNOT                              0x10c
  85
  86 /*** JTAG registers. ***/
  87
  88 #define DTMCONTROL                                      0x10
  89 #define DTMCONTROL_DBUS_RESET           (1<<16)
  90 #define DTMCONTROL_IDLE                         (7<<10)
  91 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  92 #define DTMCONTROL_VERSION                      (0xf)
  93
  94 #define DBUS                                            0x11
  95 #define DBUS_OP_START                           0
  96 #define DBUS_OP_SIZE                            2
  97 typedef enum {
  98         DBUS_OP_NOP = 0,
  99         DBUS_OP_READ = 1,
 100         DBUS_OP_WRITE = 2
 101 } dbus_op_t;
 102 typedef enum {
 103         DBUS_STATUS_SUCCESS = 0,
 104         DBUS_STATUS_FAILED = 2,
 105         DBUS_STATUS_BUSY = 3
 106 } dbus_status_t;
 107 #define DBUS_DATA_START                         2
 108 #define DBUS_DATA_SIZE                          34
 109 #define DBUS_ADDRESS_START                      36
 110
 111 typedef enum {
 112         RE_OK,
 113         RE_FAIL,
 114         RE_AGAIN
 115 } riscv_error_t;
 116
 117 typedef enum slot {
 118         SLOT0,
 119         SLOT1,
 120         SLOT_LAST,
 121 } slot_t;
 122
 123 /*** Debug Bus registers. ***/
 124
 125 #define DMCONTROL                               0x10
 126 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
 127 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
 128 #define DMCONTROL_BUSERROR              (7<<19)
 129 #define DMCONTROL_SERIAL                (3<<16)
 130 #define DMCONTROL_AUTOINCREMENT (1<<15)
 131 #define DMCONTROL_ACCESS                (7<<12)
 132 #define DMCONTROL_HARTID                (0x3ff<<2)
 133 #define DMCONTROL_NDRESET               (1<<1)
 134 #define DMCONTROL_FULLRESET             1
 135
 136 #define DMINFO                                  0x11
 137 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
 138 #define DMINFO_SERIALCOUNT              (0xf<<21)
 139 #define DMINFO_ACCESS128                (1<<20)
 140 #define DMINFO_ACCESS64                 (1<<19)
 141 #define DMINFO_ACCESS32                 (1<<18)
 142 #define DMINFO_ACCESS16                 (1<<17)
 143 #define DMINFO_ACCESS8                  (1<<16)
 144 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 145 #define DMINFO_AUTHENTICATED    (1<<5)
 146 #define DMINFO_AUTHBUSY                 (1<<4)
 147 #define DMINFO_AUTHTYPE                 (3<<2)
 148 #define DMINFO_VERSION                  3
 149
 150 /*** Info about the core being debugged. ***/
 151
 152 #define DBUS_ADDRESS_UNKNOWN    0xffff
 153
 154 #define MAX_HWBPS                       16
 155 #define DRAM_CACHE_SIZE         16
 156
 157 uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
 158 struct scan_field select_dtmcontrol = {
 159         .in_value = NULL,
 160         .out_value = ir_dtmcontrol
 161 };
 162 uint8_t ir_dbus[1] = {DBUS};
 163 struct scan_field select_dbus = {
 164         .in_value = NULL,
 165         .out_value = ir_dbus
 166 };
 167 uint8_t ir_idcode[1] = {0x1};
 168 struct scan_field select_idcode = {
 169         .in_value = NULL,
 170         .out_value = ir_idcode
 171 };
 172
 173 struct trigger {
 174         uint64_t address;
 175         uint32_t length;
 176         uint64_t mask;
 177         uint64_t value;
 178         bool read, write, execute;
 179         int unique_id;
 180 };
 181
 182 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 183 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 184
 185 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 186 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 187
 188 bool riscv_prefer_sba;
 189
 190 /* In addition to the ones in the standard spec, we'll also expose additional
 191  * CSRs in this list.
 192  * The list is either NULL, or a series of ranges (inclusive), terminated with
 193  * 1,0. */
 194 struct {
 195         uint16_t low, high;
 196 } *expose_csr;
 197
 198 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 199 {
 200         struct scan_field field;
 201         uint8_t in_value[4];
 202         uint8_t out_value[4];
 203
 204         buf_set_u32(out_value, 0, 32, out);
 205
 206         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 207
 208         field.num_bits = 32;
 209         field.out_value = out_value;
 210         field.in_value = in_value;
 211         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 212
 213         /* Always return to dbus. */
 214         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 215
 216         int retval = jtag_execute_queue();
 217         if (retval != ERROR_OK) {
 218                 LOG_ERROR("failed jtag scan: %d", retval);
 219                 return retval;
 220         }
 221
 222         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 223         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 224
 225         return in;
 226 }
 227
 228 static struct target_type *get_target_type(struct target *target)
 229 {
 230         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 231
 232         if (!info) {
 233                 LOG_ERROR("Target has not been initialized");
 234                 return NULL;
 235         }
 236
 237         switch (info->dtm_version) {
 238                 case 0:
 239                         return &riscv011_target;
 240                 case 1:
 241                         return &riscv013_target;
 242                 default:
 243                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 244                         return NULL;
 245         }
 246 }
 247
 248 static int riscv_init_target(struct command_context *cmd_ctx,
 249                 struct target *target)
 250 {
 251         LOG_DEBUG("riscv_init_target()");
 252         target->arch_info = calloc(1, sizeof(riscv_info_t));
 253         if (!target->arch_info)
 254                 return ERROR_FAIL;
 255         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 256         riscv_info_init(target, info);
 257         info->cmd_ctx = cmd_ctx;
 258
 259         select_dtmcontrol.num_bits = target->tap->ir_length;
 260         select_dbus.num_bits = target->tap->ir_length;
 261         select_idcode.num_bits = target->tap->ir_length;
 262
 263         riscv_semihosting_init(target);
 264
 265         return ERROR_OK;
 266 }
 267
 268 static void riscv_deinit_target(struct target *target)
 269 {
 270         LOG_DEBUG("riscv_deinit_target()");
 271         struct target_type *tt = get_target_type(target);
 272         if (tt) {
 273                 tt->deinit_target(target);
 274                 riscv_info_t *info = (riscv_info_t *) target->arch_info;
 275                 free(info);
 276         }
 277         target->arch_info = NULL;
 278 }
 279
 280 static int oldriscv_halt(struct target *target)
 281 {
 282         struct target_type *tt = get_target_type(target);
 283         return tt->halt(target);
 284 }
 285
 286 static void trigger_from_breakpoint(struct trigger *trigger,
 287                 const struct breakpoint *breakpoint)
 288 {
 289         trigger->address = breakpoint->address;
 290         trigger->length = breakpoint->length;
 291         trigger->mask = ~0LL;
 292         trigger->read = false;
 293         trigger->write = false;
 294         trigger->execute = true;
 295         /* unique_id is unique across both breakpoints and watchpoints. */
 296         trigger->unique_id = breakpoint->unique_id;
 297 }
 298
 299 static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
 300                 struct trigger *trigger, uint64_t tdata1)
 301 {
 302         RISCV_INFO(r);
 303
 304         const uint32_t bpcontrol_x = 1<<0;
 305         const uint32_t bpcontrol_w = 1<<1;
 306         const uint32_t bpcontrol_r = 1<<2;
 307         const uint32_t bpcontrol_u = 1<<3;
 308         const uint32_t bpcontrol_s = 1<<4;
 309         const uint32_t bpcontrol_h = 1<<5;
 310         const uint32_t bpcontrol_m = 1<<6;
 311         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 312         const uint32_t bpcontrol_bpaction = 0xff << 11;
 313
 314         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 315                 /* Trigger is already in use, presumably by user code. */
 316                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 317         }
 318
 319         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 320         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 321         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 322         tdata1 = set_field(tdata1, bpcontrol_u,
 323                         !!(r->misa[hartid] & (1 << ('U' - 'A'))));
 324         tdata1 = set_field(tdata1, bpcontrol_s,
 325                         !!(r->misa[hartid] & (1 << ('S' - 'A'))));
 326         tdata1 = set_field(tdata1, bpcontrol_h,
 327                         !!(r->misa[hartid] & (1 << ('H' - 'A'))));
 328         tdata1 |= bpcontrol_m;
 329         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 330         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 331
 332         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 333
 334         riscv_reg_t tdata1_rb;
 335         if (riscv_get_register_on_hart(target, &tdata1_rb, hartid,
 336                                 GDB_REGNO_TDATA1) != ERROR_OK)
 337                 return ERROR_FAIL;
 338         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 339
 340         if (tdata1 != tdata1_rb) {
 341                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 342                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 343                                 tdata1, tdata1_rb);
 344                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 345                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 346         }
 347
 348         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 349
 350         return ERROR_OK;
 351 }
 352
 353 static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
 354                 struct trigger *trigger, uint64_t tdata1)
 355 {
 356         RISCV_INFO(r);
 357
 358         /* tselect is already set */
 359         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 360                 /* Trigger is already in use, presumably by user code. */
 361                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 362         }
 363
 364         /* address/data match trigger */
 365         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 366         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 367                         MCONTROL_ACTION_DEBUG_MODE);
 368         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 369         tdata1 |= MCONTROL_M;
 370         if (r->misa[hartid] & (1 << ('H' - 'A')))
 371                 tdata1 |= MCONTROL_H;
 372         if (r->misa[hartid] & (1 << ('S' - 'A')))
 373                 tdata1 |= MCONTROL_S;
 374         if (r->misa[hartid] & (1 << ('U' - 'A')))
 375                 tdata1 |= MCONTROL_U;
 376
 377         if (trigger->execute)
 378                 tdata1 |= MCONTROL_EXECUTE;
 379         if (trigger->read)
 380                 tdata1 |= MCONTROL_LOAD;
 381         if (trigger->write)
 382                 tdata1 |= MCONTROL_STORE;
 383
 384         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
 385
 386         uint64_t tdata1_rb;
 387         int result = riscv_get_register_on_hart(target, &tdata1_rb, hartid, GDB_REGNO_TDATA1);
 388         if (result != ERROR_OK)
 389                 return result;
 390         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 391
 392         if (tdata1 != tdata1_rb) {
 393                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 394                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 395                                 tdata1, tdata1_rb);
 396                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 397                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 398         }
 399
 400         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
 401
 402         return ERROR_OK;
 403 }
 404
 405 static int add_trigger(struct target *target, struct trigger *trigger)
 406 {
 407         RISCV_INFO(r);
 408
 409         if (riscv_enumerate_triggers(target) != ERROR_OK)
 410                 return ERROR_FAIL;
 411
 412         /* In RTOS mode, we need to set the same trigger in the same slot on every
 413          * hart, to keep up the illusion that each hart is a thread running on the
 414          * same core. */
 415
 416         /* Otherwise, we just set the trigger on the one hart this target deals
 417          * with. */
 418
 419         riscv_reg_t tselect[RISCV_MAX_HARTS];
 420
 421         int first_hart = -1;
 422         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 423                 if (!riscv_hart_enabled(target, hartid))
 424                         continue;
 425                 if (first_hart < 0)
 426                         first_hart = hartid;
 427                 int result = riscv_get_register_on_hart(target, &tselect[hartid],
 428                                 hartid, GDB_REGNO_TSELECT);
 429                 if (result != ERROR_OK)
 430                         return result;
 431         }
 432         assert(first_hart >= 0);
 433
 434         unsigned int i;
 435         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 436                 if (r->trigger_unique_id[i] != -1)
 437                         continue;
 438
 439                 riscv_set_register_on_hart(target, first_hart, GDB_REGNO_TSELECT, i);
 440
 441                 uint64_t tdata1;
 442                 int result = riscv_get_register_on_hart(target, &tdata1, first_hart,
 443                                 GDB_REGNO_TDATA1);
 444                 if (result != ERROR_OK)
 445                         return result;
 446                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 447
 448                 result = ERROR_OK;
 449                 for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 450                         if (!riscv_hart_enabled(target, hartid))
 451                                 continue;
 452                         if (hartid > first_hart)
 453                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 454                         switch (type) {
 455                                 case 1:
 456                                         result = maybe_add_trigger_t1(target, hartid, trigger, tdata1);
 457                                         break;
 458                                 case 2:
 459                                         result = maybe_add_trigger_t2(target, hartid, trigger, tdata1);
 460                                         break;
 461                                 default:
 462                                         LOG_DEBUG("trigger %d has unknown type %d", i, type);
 463                                         continue;
 464                         }
 465
 466                         if (result != ERROR_OK)
 467                                 continue;
 468                 }
 469
 470                 if (result != ERROR_OK)
 471                         continue;
 472
 473                 LOG_DEBUG("Using trigger %d (type %d) for bp %d", i, type,
 474                                 trigger->unique_id);
 475                 r->trigger_unique_id[i] = trigger->unique_id;
 476                 break;
 477         }
 478
 479         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 480                 if (!riscv_hart_enabled(target, hartid))
 481                         continue;
 482                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
 483                                 tselect[hartid]);
 484         }
 485
 486         if (i >= r->trigger_count[first_hart]) {
 487                 LOG_ERROR("Couldn't find an available hardware trigger.");
 488                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 489         }
 490
 491         return ERROR_OK;
 492 }
 493
 494 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 495 {
 496         if (breakpoint->type == BKPT_SOFT) {
 497                 if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
 498                                         breakpoint->orig_instr) != ERROR_OK) {
 499                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 500                                         breakpoint->address);
 501                         return ERROR_FAIL;
 502                 }
 503
 504                 int retval;
 505                 if (breakpoint->length == 4)
 506                         retval = target_write_u32(target, breakpoint->address, ebreak());
 507                 else
 508                         retval = target_write_u16(target, breakpoint->address, ebreak_c());
 509                 if (retval != ERROR_OK) {
 510                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 511                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 512                         return ERROR_FAIL;
 513                 }
 514
 515         } else if (breakpoint->type == BKPT_HARD) {
 516                 struct trigger trigger;
 517                 trigger_from_breakpoint(&trigger, breakpoint);
 518                 int result = add_trigger(target, &trigger);
 519                 if (result != ERROR_OK)
 520                         return result;
 521
 522         } else {
 523                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 524                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 525         }
 526
 527         breakpoint->set = true;
 528
 529         return ERROR_OK;
 530 }
 531
 532 static int remove_trigger(struct target *target, struct trigger *trigger)
 533 {
 534         RISCV_INFO(r);
 535
 536         if (riscv_enumerate_triggers(target) != ERROR_OK)
 537                 return ERROR_FAIL;
 538
 539         int first_hart = -1;
 540         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
 541                 if (!riscv_hart_enabled(target, hartid))
 542                         continue;
 543                 if (first_hart < 0) {
 544                         first_hart = hartid;
 545                         break;
 546                 }
 547         }
 548         assert(first_hart >= 0);
 549
 550         unsigned int i;
 551         for (i = 0; i < r->trigger_count[first_hart]; i++) {
 552                 if (r->trigger_unique_id[i] == trigger->unique_id)
 553                         break;
 554         }
 555         if (i >= r->trigger_count[first_hart]) {
 556                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 557                                 "trigger.");
 558                 return ERROR_FAIL;
 559         }
 560         LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
 561         for (int hartid = first_hart; hartid < riscv_count_harts(target); ++hartid) {
 562                 if (!riscv_hart_enabled(target, hartid))
 563                         continue;
 564                 riscv_reg_t tselect;
 565                 int result = riscv_get_register_on_hart(target, &tselect, hartid, GDB_REGNO_TSELECT);
 566                 if (result != ERROR_OK)
 567                         return result;
 568                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
 569                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
 570                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
 571         }
 572         r->trigger_unique_id[i] = -1;
 573
 574         return ERROR_OK;
 575 }
 576
 577 int riscv_remove_breakpoint(struct target *target,
 578                 struct breakpoint *breakpoint)
 579 {
 580         if (breakpoint->type == BKPT_SOFT) {
 581                 if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
 582                                         breakpoint->orig_instr) != ERROR_OK) {
 583                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 584                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 585                         return ERROR_FAIL;
 586                 }
 587
 588         } else if (breakpoint->type == BKPT_HARD) {
 589                 struct trigger trigger;
 590                 trigger_from_breakpoint(&trigger, breakpoint);
 591                 int result = remove_trigger(target, &trigger);
 592                 if (result != ERROR_OK)
 593                         return result;
 594
 595         } else {
 596                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 597                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 598         }
 599
 600         breakpoint->set = false;
 601
 602         return ERROR_OK;
 603 }
 604
 605 static void trigger_from_watchpoint(struct trigger *trigger,
 606                 const struct watchpoint *watchpoint)
 607 {
 608         trigger->address = watchpoint->address;
 609         trigger->length = watchpoint->length;
 610         trigger->mask = watchpoint->mask;
 611         trigger->value = watchpoint->value;
 612         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 613         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 614         trigger->execute = false;
 615         /* unique_id is unique across both breakpoints and watchpoints. */
 616         trigger->unique_id = watchpoint->unique_id;
 617 }
 618
 619 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 620 {
 621         struct trigger trigger;
 622         trigger_from_watchpoint(&trigger, watchpoint);
 623
 624         int result = add_trigger(target, &trigger);
 625         if (result != ERROR_OK)
 626                 return result;
 627         watchpoint->set = true;
 628
 629         return ERROR_OK;
 630 }
 631
 632 int riscv_remove_watchpoint(struct target *target,
 633                 struct watchpoint *watchpoint)
 634 {
 635         struct trigger trigger;
 636         trigger_from_watchpoint(&trigger, watchpoint);
 637
 638         int result = remove_trigger(target, &trigger);
 639         if (result != ERROR_OK)
 640                 return result;
 641         watchpoint->set = false;
 642
 643         return ERROR_OK;
 644 }
 645
 646 static int oldriscv_step(struct target *target, int current, uint32_t address,
 647                 int handle_breakpoints)
 648 {
 649         struct target_type *tt = get_target_type(target);
 650         return tt->step(target, current, address, handle_breakpoints);
 651 }
 652
 653 static int old_or_new_riscv_step(
 654                 struct target *target,
 655                 int current,
 656                 target_addr_t address,
 657                 int handle_breakpoints
 658 ){
 659         RISCV_INFO(r);
 660         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 661         if (r->is_halted == NULL)
 662                 return oldriscv_step(target, current, address, handle_breakpoints);
 663         else
 664                 return riscv_openocd_step(target, current, address, handle_breakpoints);
 665 }
 666
 667
 668 static int riscv_examine(struct target *target)
 669 {
 670         LOG_DEBUG("riscv_examine()");
 671         if (target_was_examined(target)) {
 672                 LOG_DEBUG("Target was already examined.");
 673                 return ERROR_OK;
 674         }
 675
 676         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
 677
 678         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 679         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
 680         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
 681         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
 682         LOG_DEBUG("  version=0x%x", info->dtm_version);
 683
 684         struct target_type *tt = get_target_type(target);
 685         if (tt == NULL)
 686                 return ERROR_FAIL;
 687
 688         int result = tt->init_target(info->cmd_ctx, target);
 689         if (result != ERROR_OK)
 690                 return result;
 691
 692         return tt->examine(target);
 693 }
 694
 695 static int oldriscv_poll(struct target *target)
 696 {
 697         struct target_type *tt = get_target_type(target);
 698         return tt->poll(target);
 699 }
 700
 701 static int old_or_new_riscv_poll(struct target *target)
 702 {
 703         RISCV_INFO(r);
 704         if (r->is_halted == NULL)
 705                 return oldriscv_poll(target);
 706         else
 707                 return riscv_openocd_poll(target);
 708 }
 709
 710 static int old_or_new_riscv_halt(struct target *target)
 711 {
 712         RISCV_INFO(r);
 713         if (r->is_halted == NULL)
 714                 return oldriscv_halt(target);
 715         else
 716                 return riscv_openocd_halt(target);
 717 }
 718
 719 static int riscv_assert_reset(struct target *target)
 720 {
 721         struct target_type *tt = get_target_type(target);
 722         return tt->assert_reset(target);
 723 }
 724
 725 static int riscv_deassert_reset(struct target *target)
 726 {
 727         LOG_DEBUG("RISCV DEASSERT RESET");
 728         struct target_type *tt = get_target_type(target);
 729         return tt->deassert_reset(target);
 730 }
 731
 732
 733 static int oldriscv_resume(struct target *target, int current, uint32_t address,
 734                 int handle_breakpoints, int debug_execution)
 735 {
 736         struct target_type *tt = get_target_type(target);
 737         return tt->resume(target, current, address, handle_breakpoints,
 738                         debug_execution);
 739 }
 740
 741 static int old_or_new_riscv_resume(
 742                 struct target *target,
 743                 int current,
 744                 target_addr_t address,
 745                 int handle_breakpoints,
 746                 int debug_execution
 747 ){
 748         RISCV_INFO(r);
 749         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
 750         if (r->is_halted == NULL)
 751                 return oldriscv_resume(target, current, address, handle_breakpoints, debug_execution);
 752         else
 753                 return riscv_openocd_resume(target, current, address, handle_breakpoints, debug_execution);
 754 }
 755
 756 static int riscv_select_current_hart(struct target *target)
 757 {
 758         RISCV_INFO(r);
 759         if (r->rtos_hartid != -1 && riscv_rtos_enabled(target))
 760                 return riscv_set_current_hartid(target, r->rtos_hartid);
 761         else
 762                 return riscv_set_current_hartid(target, target->coreid);
 763 }
 764
 765 static int riscv_read_memory(struct target *target, target_addr_t address,
 766                 uint32_t size, uint32_t count, uint8_t *buffer)
 767 {
 768         if (riscv_select_current_hart(target) != ERROR_OK)
 769                 return ERROR_FAIL;
 770         struct target_type *tt = get_target_type(target);
 771         return tt->read_memory(target, address, size, count, buffer);
 772 }
 773
 774 static int riscv_write_memory(struct target *target, target_addr_t address,
 775                 uint32_t size, uint32_t count, const uint8_t *buffer)
 776 {
 777         if (riscv_select_current_hart(target) != ERROR_OK)
 778                 return ERROR_FAIL;
 779         struct target_type *tt = get_target_type(target);
 780         return tt->write_memory(target, address, size, count, buffer);
 781 }
 782
 783 static int riscv_get_gdb_reg_list(struct target *target,
 784                 struct reg **reg_list[], int *reg_list_size,
 785                 enum target_register_class reg_class)
 786 {
 787         RISCV_INFO(r);
 788         LOG_DEBUG("reg_class=%d", reg_class);
 789         LOG_DEBUG("rtos_hartid=%d current_hartid=%d", r->rtos_hartid, r->current_hartid);
 790
 791         if (!target->reg_cache) {
 792                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
 793                 return ERROR_FAIL;
 794         }
 795
 796         if (riscv_select_current_hart(target) != ERROR_OK)
 797                 return ERROR_FAIL;
 798
 799         switch (reg_class) {
 800                 case REG_CLASS_GENERAL:
 801                         *reg_list_size = 32;
 802                         break;
 803                 case REG_CLASS_ALL:
 804                         *reg_list_size = GDB_REGNO_COUNT;
 805                         break;
 806                 default:
 807                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
 808                         return ERROR_FAIL;
 809         }
 810
 811         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
 812         if (!*reg_list)
 813                 return ERROR_FAIL;
 814
 815         for (int i = 0; i < *reg_list_size; i++) {
 816                 assert(!target->reg_cache->reg_list[i].valid ||
 817                                 target->reg_cache->reg_list[i].size > 0);
 818                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
 819         }
 820
 821         return ERROR_OK;
 822 }
 823
 824 static int riscv_arch_state(struct target *target)
 825 {
 826         struct target_type *tt = get_target_type(target);
 827         return tt->arch_state(target);
 828 }
 829
 830 /* Algorithm must end with a software breakpoint instruction. */
 831 static int riscv_run_algorithm(struct target *target, int num_mem_params,
 832                 struct mem_param *mem_params, int num_reg_params,
 833                 struct reg_param *reg_params, target_addr_t entry_point,
 834                 target_addr_t exit_point, int timeout_ms, void *arch_info)
 835 {
 836         riscv_info_t *info = (riscv_info_t *) target->arch_info;
 837
 838         if (num_mem_params > 0) {
 839                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
 840                 return ERROR_FAIL;
 841         }
 842
 843         if (target->state != TARGET_HALTED) {
 844                 LOG_WARNING("target not halted");
 845                 return ERROR_TARGET_NOT_HALTED;
 846         }
 847
 848         /* Save registers */
 849         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
 850         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
 851                 return ERROR_FAIL;
 852         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
 853
 854         uint64_t saved_regs[32];
 855         for (int i = 0; i < num_reg_params; i++) {
 856                 LOG_DEBUG("save %s", reg_params[i].reg_name);
 857                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
 858                 if (!r) {
 859                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
 860                         return ERROR_FAIL;
 861                 }
 862
 863                 if (r->size != reg_params[i].size) {
 864                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
 865                                         reg_params[i].reg_name, r->size, reg_params[i].size);
 866                         return ERROR_FAIL;
 867                 }
 868
 869                 if (r->number > GDB_REGNO_XPR31) {
 870                         LOG_ERROR("Only GPRs can be use as argument registers.");
 871                         return ERROR_FAIL;
 872                 }
 873
 874                 if (r->type->get(r) != ERROR_OK)
 875                         return ERROR_FAIL;
 876                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
 877                 if (r->type->set(r, reg_params[i].value) != ERROR_OK)
 878                         return ERROR_FAIL;
 879         }
 880
 881
 882         /* Disable Interrupts before attempting to run the algorithm. */
 883         uint64_t current_mstatus;
 884         uint8_t mstatus_bytes[8];
 885
 886         LOG_DEBUG("Disabling Interrupts");
 887         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
 888                         "mstatus", 1);
 889         if (!reg_mstatus) {
 890                 LOG_ERROR("Couldn't find mstatus!");
 891                 return ERROR_FAIL;
 892         }
 893
 894         reg_mstatus->type->get(reg_mstatus);
 895         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
 896         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
 897         buf_set_u64(mstatus_bytes, 0, info->xlen[0], set_field(current_mstatus,
 898                                 ie_mask, 0));
 899
 900         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
 901
 902         /* Run algorithm */
 903         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
 904         if (oldriscv_resume(target, 0, entry_point, 0, 0) != ERROR_OK)
 905                 return ERROR_FAIL;
 906
 907         int64_t start = timeval_ms();
 908         while (target->state != TARGET_HALTED) {
 909                 LOG_DEBUG("poll()");
 910                 int64_t now = timeval_ms();
 911                 if (now - start > timeout_ms) {
 912                         LOG_ERROR("Algorithm timed out after %d ms.", timeout_ms);
 913                         LOG_ERROR("  now   = 0x%08x", (uint32_t) now);
 914                         LOG_ERROR("  start = 0x%08x", (uint32_t) start);
 915                         oldriscv_halt(target);
 916                         old_or_new_riscv_poll(target);
 917                         return ERROR_TARGET_TIMEOUT;
 918                 }
 919
 920                 int result = old_or_new_riscv_poll(target);
 921                 if (result != ERROR_OK)
 922                         return result;
 923         }
 924
 925         if (reg_pc->type->get(reg_pc) != ERROR_OK)
 926                 return ERROR_FAIL;
 927         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
 928         if (final_pc != exit_point) {
 929                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
 930                                 TARGET_PRIxADDR, final_pc, exit_point);
 931                 return ERROR_FAIL;
 932         }
 933
 934         /* Restore Interrupts */
 935         LOG_DEBUG("Restoring Interrupts");
 936         buf_set_u64(mstatus_bytes, 0, info->xlen[0], current_mstatus);
 937         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
 938
 939         /* Restore registers */
 940         uint8_t buf[8];
 941         buf_set_u64(buf, 0, info->xlen[0], saved_pc);
 942         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
 943                 return ERROR_FAIL;
 944
 945         for (int i = 0; i < num_reg_params; i++) {
 946                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
 947                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
 948                 buf_set_u64(buf, 0, info->xlen[0], saved_regs[r->number]);
 949                 if (r->type->set(r, buf) != ERROR_OK)
 950                         return ERROR_FAIL;
 951         }
 952
 953         return ERROR_OK;
 954 }
 955
 956 /* Should run code on the target to perform CRC of
 957 memory. Not yet implemented.
 958 */
 959
 960 static int riscv_checksum_memory(struct target *target,
 961                 target_addr_t address, uint32_t count,
 962                 uint32_t *checksum)
 963 {
 964         *checksum = 0xFFFFFFFF;
 965         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 966 }
 967
 968 /*** OpenOCD Helper Functions ***/
 969
 970 enum riscv_poll_hart {
 971         RPH_NO_CHANGE,
 972         RPH_DISCOVERED_HALTED,
 973         RPH_DISCOVERED_RUNNING,
 974         RPH_ERROR
 975 };
 976 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
 977 {
 978         RISCV_INFO(r);
 979         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
 980                 return RPH_ERROR;
 981
 982         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
 983
 984         /* If OpenOCD thinks we're running but this hart is halted then it's time
 985          * to raise an event. */
 986         bool halted = riscv_is_halted(target);
 987         if (target->state != TARGET_HALTED && halted) {
 988                 LOG_DEBUG("  triggered a halt");
 989                 r->on_halt(target);
 990                 return RPH_DISCOVERED_HALTED;
 991         } else if (target->state != TARGET_RUNNING && !halted) {
 992                 LOG_DEBUG("  triggered running");
 993                 target->state = TARGET_RUNNING;
 994                 return RPH_DISCOVERED_RUNNING;
 995         }
 996
 997         return RPH_NO_CHANGE;
 998 }
 999
1000 /*** OpenOCD Interface ***/
1001 int riscv_openocd_poll(struct target *target)
1002 {
1003         LOG_DEBUG("polling all harts");
1004         int halted_hart = -1;
1005         if (riscv_rtos_enabled(target)) {
1006                 /* Check every hart for an event. */
1007                 for (int i = 0; i < riscv_count_harts(target); ++i) {
1008                         enum riscv_poll_hart out = riscv_poll_hart(target, i);
1009                         switch (out) {
1010                         case RPH_NO_CHANGE:
1011                         case RPH_DISCOVERED_RUNNING:
1012                                 continue;
1013                         case RPH_DISCOVERED_HALTED:
1014                                 halted_hart = i;
1015                                 break;
1016                         case RPH_ERROR:
1017                                 return ERROR_FAIL;
1018                         }
1019                 }
1020                 if (halted_hart == -1) {
1021                         LOG_DEBUG("  no harts just halted, target->state=%d", target->state);
1022                         return ERROR_OK;
1023                 }
1024                 LOG_DEBUG("  hart %d halted", halted_hart);
1025
1026                 /* If we're here then at least one hart triggered.  That means
1027                  * we want to go and halt _every_ hart in the system, as that's
1028                  * the invariant we hold here.  Some harts might have already
1029                  * halted (as we're either in single-step mode or they also
1030                  * triggered a breakpoint), so don't attempt to halt those
1031                  * harts. */
1032                 for (int i = 0; i < riscv_count_harts(target); ++i)
1033                         riscv_halt_one_hart(target, i);
1034         } else {
1035                 enum riscv_poll_hart out = riscv_poll_hart(target,
1036                                 riscv_current_hartid(target));
1037                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING)
1038                         return ERROR_OK;
1039                 else if (out == RPH_ERROR)
1040                         return ERROR_FAIL;
1041
1042                 halted_hart = riscv_current_hartid(target);
1043                 LOG_DEBUG("  hart %d halted", halted_hart);
1044         }
1045
1046         target->state = TARGET_HALTED;
1047         switch (riscv_halt_reason(target, halted_hart)) {
1048         case RISCV_HALT_BREAKPOINT:
1049                 target->debug_reason = DBG_REASON_BREAKPOINT;
1050                 break;
1051         case RISCV_HALT_TRIGGER:
1052                 target->debug_reason = DBG_REASON_WATCHPOINT;
1053                 break;
1054         case RISCV_HALT_INTERRUPT:
1055                 target->debug_reason = DBG_REASON_DBGRQ;
1056                 break;
1057         case RISCV_HALT_SINGLESTEP:
1058                 target->debug_reason = DBG_REASON_SINGLESTEP;
1059                 break;
1060         case RISCV_HALT_UNKNOWN:
1061                 target->debug_reason = DBG_REASON_UNDEFINED;
1062                 break;
1063         case RISCV_HALT_ERROR:
1064                 return ERROR_FAIL;
1065         }
1066
1067         if (riscv_rtos_enabled(target)) {
1068                 target->rtos->current_threadid = halted_hart + 1;
1069                 target->rtos->current_thread = halted_hart + 1;
1070         }
1071
1072         target->state = TARGET_HALTED;
1073
1074         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
1075                 int retval;
1076                 if (riscv_semihosting(target, &retval) != 0)
1077                         return retval;
1078         }
1079
1080         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1081         return ERROR_OK;
1082 }
1083
1084 int riscv_openocd_halt(struct target *target)
1085 {
1086         RISCV_INFO(r);
1087
1088         LOG_DEBUG("halting all harts");
1089
1090         int out = riscv_halt_all_harts(target);
1091         if (out != ERROR_OK) {
1092                 LOG_ERROR("Unable to halt all harts");
1093                 return out;
1094         }
1095
1096         register_cache_invalidate(target->reg_cache);
1097         if (riscv_rtos_enabled(target)) {
1098                 target->rtos->current_threadid = r->rtos_hartid + 1;
1099                 target->rtos->current_thread = r->rtos_hartid + 1;
1100         }
1101
1102         target->state = TARGET_HALTED;
1103         target->debug_reason = DBG_REASON_DBGRQ;
1104         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1105         return out;
1106 }
1107
1108 int riscv_openocd_resume(
1109                 struct target *target,
1110                 int current,
1111                 target_addr_t address,
1112                 int handle_breakpoints,
1113                 int debug_execution)
1114 {
1115         LOG_DEBUG("debug_reason=%d", target->debug_reason);
1116
1117         if (!current)
1118                 riscv_set_register(target, GDB_REGNO_PC, address);
1119
1120         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1121                 /* To be able to run off a trigger, disable all the triggers, step, and
1122                  * then resume as usual. */
1123                 struct watchpoint *watchpoint = target->watchpoints;
1124                 bool trigger_temporarily_cleared[RISCV_MAX_HWBPS] = {0};
1125
1126                 int i = 0;
1127                 int result = ERROR_OK;
1128                 while (watchpoint && result == ERROR_OK) {
1129                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set);
1130                         trigger_temporarily_cleared[i] = watchpoint->set;
1131                         if (watchpoint->set)
1132                                 result = riscv_remove_watchpoint(target, watchpoint);
1133                         watchpoint = watchpoint->next;
1134                         i++;
1135                 }
1136
1137                 if (result == ERROR_OK)
1138                         result = riscv_step_rtos_hart(target);
1139
1140                 watchpoint = target->watchpoints;
1141                 i = 0;
1142                 while (watchpoint) {
1143                         LOG_DEBUG("watchpoint %d: cleared=%d", i, trigger_temporarily_cleared[i]);
1144                         if (trigger_temporarily_cleared[i]) {
1145                                 if (result == ERROR_OK)
1146                                         result = riscv_add_watchpoint(target, watchpoint);
1147                                 else
1148                                         riscv_add_watchpoint(target, watchpoint);
1149                         }
1150                         watchpoint = watchpoint->next;
1151                         i++;
1152                 }
1153
1154                 if (result != ERROR_OK)
1155                         return result;
1156         }
1157
1158         int out = riscv_resume_all_harts(target);
1159         if (out != ERROR_OK) {
1160                 LOG_ERROR("unable to resume all harts");
1161                 return out;
1162         }
1163
1164         register_cache_invalidate(target->reg_cache);
1165         target->state = TARGET_RUNNING;
1166         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1167         return out;
1168 }
1169
1170 int riscv_openocd_step(
1171                 struct target *target,
1172                 int current,
1173                 target_addr_t address,
1174                 int handle_breakpoints
1175 ) {
1176         LOG_DEBUG("stepping rtos hart");
1177
1178         if (!current)
1179                 riscv_set_register(target, GDB_REGNO_PC, address);
1180
1181         int out = riscv_step_rtos_hart(target);
1182         if (out != ERROR_OK) {
1183                 LOG_ERROR("unable to step rtos hart");
1184                 return out;
1185         }
1186
1187         register_cache_invalidate(target->reg_cache);
1188         target->state = TARGET_RUNNING;
1189         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1190         target->state = TARGET_HALTED;
1191         target->debug_reason = DBG_REASON_SINGLESTEP;
1192         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1193         return out;
1194 }
1195
1196 /* Command Handlers */
1197 COMMAND_HANDLER(riscv_set_command_timeout_sec)
1198 {
1199         if (CMD_ARGC != 1) {
1200                 LOG_ERROR("Command takes exactly 1 parameter");
1201                 return ERROR_COMMAND_SYNTAX_ERROR;
1202         }
1203         int timeout = atoi(CMD_ARGV[0]);
1204         if (timeout <= 0) {
1205                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1206                 return ERROR_FAIL;
1207         }
1208
1209         riscv_command_timeout_sec = timeout;
1210
1211         return ERROR_OK;
1212 }
1213
1214 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
1215 {
1216         if (CMD_ARGC != 1) {
1217                 LOG_ERROR("Command takes exactly 1 parameter");
1218                 return ERROR_COMMAND_SYNTAX_ERROR;
1219         }
1220         int timeout = atoi(CMD_ARGV[0]);
1221         if (timeout <= 0) {
1222                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
1223                 return ERROR_FAIL;
1224         }
1225
1226         riscv_reset_timeout_sec = timeout;
1227         return ERROR_OK;
1228 }
1229
1230 COMMAND_HANDLER(riscv_set_prefer_sba)
1231 {
1232         if (CMD_ARGC != 1) {
1233                 LOG_ERROR("Command takes exactly 1 parameter");
1234                 return ERROR_COMMAND_SYNTAX_ERROR;
1235         }
1236         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_prefer_sba);
1237         return ERROR_OK;
1238 }
1239
1240 void parse_error(const char *string, char c, unsigned position)
1241 {
1242         char buf[position+2];
1243         for (unsigned i = 0; i < position; i++)
1244                 buf[i] = ' ';
1245         buf[position] = '^';
1246         buf[position + 1] = 0;
1247
1248         LOG_ERROR("Parse error at character %c in:", c);
1249         LOG_ERROR("%s", string);
1250         LOG_ERROR("%s", buf);
1251 }
1252
1253 COMMAND_HANDLER(riscv_set_expose_csrs)
1254 {
1255         if (CMD_ARGC != 1) {
1256                 LOG_ERROR("Command takes exactly 1 parameter");
1257                 return ERROR_COMMAND_SYNTAX_ERROR;
1258         }
1259
1260         for (unsigned pass = 0; pass < 2; pass++) {
1261                 unsigned range = 0;
1262                 unsigned low = 0;
1263                 bool parse_low = true;
1264                 unsigned high = 0;
1265                 for (unsigned i = 0; i == 0 || CMD_ARGV[0][i-1]; i++) {
1266                         char c = CMD_ARGV[0][i];
1267                         if (isspace(c)) {
1268                                 /* Ignore whitespace. */
1269                                 continue;
1270                         }
1271
1272                         if (parse_low) {
1273                                 if (isdigit(c)) {
1274                                         low *= 10;
1275                                         low += c - '0';
1276                                 } else if (c == '-') {
1277                                         parse_low = false;
1278                                 } else if (c == ',' || c == 0) {
1279                                         if (pass == 1) {
1280                                                 expose_csr[range].low = low;
1281                                                 expose_csr[range].high = low;
1282                                         }
1283                                         low = 0;
1284                                         range++;
1285                                 } else {
1286                                         parse_error(CMD_ARGV[0], c, i);
1287                                         return ERROR_COMMAND_SYNTAX_ERROR;
1288                                 }
1289
1290                         } else {
1291                                 if (isdigit(c)) {
1292                                         high *= 10;
1293                                         high += c - '0';
1294                                 } else if (c == ',' || c == 0) {
1295                                         parse_low = true;
1296                                         if (pass == 1) {
1297                                                 expose_csr[range].low = low;
1298                                                 expose_csr[range].high = high;
1299                                         }
1300                                         low = 0;
1301                                         high = 0;
1302                                         range++;
1303                                 } else {
1304                                         parse_error(CMD_ARGV[0], c, i);
1305                                         return ERROR_COMMAND_SYNTAX_ERROR;
1306                                 }
1307                         }
1308                 }
1309
1310                 if (pass == 0) {
1311                         if (expose_csr)
1312                                 free(expose_csr);
1313                         expose_csr = calloc(range + 2, sizeof(*expose_csr));
1314                 } else {
1315                         expose_csr[range].low = 1;
1316                         expose_csr[range].high = 0;
1317                 }
1318         }
1319         return ERROR_OK;
1320 }
1321
1322 COMMAND_HANDLER(riscv_authdata_read)
1323 {
1324         if (CMD_ARGC != 0) {
1325                 LOG_ERROR("Command takes no parameters");
1326                 return ERROR_COMMAND_SYNTAX_ERROR;
1327         }
1328
1329         struct target *target = get_current_target(CMD_CTX);
1330         if (!target) {
1331                 LOG_ERROR("target is NULL!");
1332                 return ERROR_FAIL;
1333         }
1334
1335         RISCV_INFO(r);
1336         if (!r) {
1337                 LOG_ERROR("riscv_info is NULL!");
1338                 return ERROR_FAIL;
1339         }
1340
1341         if (r->authdata_read) {
1342                 uint32_t value;
1343                 if (r->authdata_read(target, &value) != ERROR_OK)
1344                         return ERROR_FAIL;
1345                 command_print(CMD_CTX, "0x%" PRIx32, value);
1346                 return ERROR_OK;
1347         } else {
1348                 LOG_ERROR("authdata_read is not implemented for this target.");
1349                 return ERROR_FAIL;
1350         }
1351 }
1352
1353 COMMAND_HANDLER(riscv_authdata_write)
1354 {
1355         if (CMD_ARGC != 1) {
1356                 LOG_ERROR("Command takes exactly 1 argument");
1357                 return ERROR_COMMAND_SYNTAX_ERROR;
1358         }
1359
1360         struct target *target = get_current_target(CMD_CTX);
1361         RISCV_INFO(r);
1362
1363         uint32_t value;
1364         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
1365
1366         if (r->authdata_write) {
1367                 return r->authdata_write(target, value);
1368         } else {
1369                 LOG_ERROR("authdata_write is not implemented for this target.");
1370                 return ERROR_FAIL;
1371         }
1372 }
1373
1374 COMMAND_HANDLER(riscv_dmi_read)
1375 {
1376         if (CMD_ARGC != 1) {
1377                 LOG_ERROR("Command takes 1 parameter");
1378                 return ERROR_COMMAND_SYNTAX_ERROR;
1379         }
1380
1381         struct target *target = get_current_target(CMD_CTX);
1382         if (!target) {
1383                 LOG_ERROR("target is NULL!");
1384                 return ERROR_FAIL;
1385         }
1386
1387         RISCV_INFO(r);
1388         if (!r) {
1389                 LOG_ERROR("riscv_info is NULL!");
1390                 return ERROR_FAIL;
1391         }
1392
1393         if (r->dmi_read) {
1394                 uint32_t address, value;
1395                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1396                 if (r->dmi_read(target, &value, address) != ERROR_OK)
1397                         return ERROR_FAIL;
1398                 command_print(CMD_CTX, "0x%" PRIx32, value);
1399                 return ERROR_OK;
1400         } else {
1401                 LOG_ERROR("dmi_read is not implemented for this target.");
1402                 return ERROR_FAIL;
1403         }
1404 }
1405
1406
1407 COMMAND_HANDLER(riscv_dmi_write)
1408 {
1409         if (CMD_ARGC != 2) {
1410                 LOG_ERROR("Command takes exactly 2 arguments");
1411                 return ERROR_COMMAND_SYNTAX_ERROR;
1412         }
1413
1414         struct target *target = get_current_target(CMD_CTX);
1415         RISCV_INFO(r);
1416
1417         uint32_t address, value;
1418         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
1419         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1420
1421         if (r->dmi_write) {
1422                 return r->dmi_write(target, address, value);
1423         } else {
1424                 LOG_ERROR("dmi_write is not implemented for this target.");
1425                 return ERROR_FAIL;
1426         }
1427 }
1428
1429 static const struct command_registration riscv_exec_command_handlers[] = {
1430         {
1431                 .name = "set_command_timeout_sec",
1432                 .handler = riscv_set_command_timeout_sec,
1433                 .mode = COMMAND_ANY,
1434                 .usage = "riscv set_command_timeout_sec [sec]",
1435                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
1436         },
1437         {
1438                 .name = "set_reset_timeout_sec",
1439                 .handler = riscv_set_reset_timeout_sec,
1440                 .mode = COMMAND_ANY,
1441                 .usage = "riscv set_reset_timeout_sec [sec]",
1442                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
1443         },
1444         {
1445                 .name = "set_prefer_sba",
1446                 .handler = riscv_set_prefer_sba,
1447                 .mode = COMMAND_ANY,
1448                 .usage = "riscv set_prefer_sba on|off",
1449                 .help = "When on, prefer to use System Bus Access to access memory. "
1450                         "When off, prefer to use the Program Buffer to access memory."
1451         },
1452         {
1453                 .name = "expose_csrs",
1454                 .handler = riscv_set_expose_csrs,
1455                 .mode = COMMAND_ANY,
1456                 .usage = "riscv expose_csrs n0[-m0][,n1[-m1]]...",
1457                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
1458                                 "addition to the standard ones. This must be executed before "
1459                                 "`init`."
1460         },
1461         {
1462                 .name = "authdata_read",
1463                 .handler = riscv_authdata_read,
1464                 .mode = COMMAND_ANY,
1465                 .usage = "riscv authdata_read",
1466                 .help = "Return the 32-bit value read from authdata."
1467         },
1468         {
1469                 .name = "authdata_write",
1470                 .handler = riscv_authdata_write,
1471                 .mode = COMMAND_ANY,
1472                 .usage = "riscv authdata_write value",
1473                 .help = "Write the 32-bit value to authdata."
1474         },
1475         {
1476                 .name = "dmi_read",
1477                 .handler = riscv_dmi_read,
1478                 .mode = COMMAND_ANY,
1479                 .usage = "riscv dmi_read address",
1480                 .help = "Perform a 32-bit DMI read at address, returning the value."
1481         },
1482         {
1483                 .name = "dmi_write",
1484                 .handler = riscv_dmi_write,
1485                 .mode = COMMAND_ANY,
1486                 .usage = "riscv dmi_write address value",
1487                 .help = "Perform a 32-bit DMI write of value at address."
1488         },
1489         COMMAND_REGISTRATION_DONE
1490 };
1491
1492 extern __COMMAND_HANDLER(handle_common_semihosting_command);
1493 extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
1494 extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
1495 extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
1496
1497 /*
1498  * To be noted that RISC-V targets use the same semihosting commands as
1499  * ARM targets.
1500  *
1501  * The main reason is compatibility with existing tools. For example the
1502  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
1503  * configure semihosting, which generate commands like `arm semihosting
1504  * enable`.
1505  * A secondary reason is the fact that the protocol used is exactly the
1506  * one specified by ARM. If RISC-V will ever define its own semihosting
1507  * protocol, then a command like `riscv semihosting enable` will make
1508  * sense, but for now all semihosting commands are prefixed with `arm`.
1509  */
1510 static const struct command_registration arm_exec_command_handlers[] = {
1511         {
1512                 "semihosting",
1513                 .handler = handle_common_semihosting_command,
1514                 .mode = COMMAND_EXEC,
1515                 .usage = "['enable'|'disable']",
1516                 .help = "activate support for semihosting operations",
1517         },
1518         {
1519                 "semihosting_cmdline",
1520                 .handler = handle_common_semihosting_cmdline,
1521                 .mode = COMMAND_EXEC,
1522                 .usage = "arguments",
1523                 .help = "command line arguments to be passed to program",
1524         },
1525         {
1526                 "semihosting_fileio",
1527                 .handler = handle_common_semihosting_fileio_command,
1528                 .mode = COMMAND_EXEC,
1529                 .usage = "['enable'|'disable']",
1530                 .help = "activate support for semihosting fileio operations",
1531         },
1532         {
1533                 "semihosting_resexit",
1534                 .handler = handle_common_semihosting_resumable_exit_command,
1535                 .mode = COMMAND_EXEC,
1536                 .usage = "['enable'|'disable']",
1537                 .help = "activate support for semihosting resumable exit",
1538         },
1539         COMMAND_REGISTRATION_DONE
1540 };
1541
1542 const struct command_registration riscv_command_handlers[] = {
1543         {
1544                 .name = "riscv",
1545                 .mode = COMMAND_ANY,
1546                 .help = "RISC-V Command Group",
1547                 .usage = "",
1548                 .chain = riscv_exec_command_handlers
1549         },
1550         {
1551                 .name = "arm",
1552                 .mode = COMMAND_ANY,
1553                 .help = "ARM Command Group",
1554                 .usage = "",
1555                 .chain = arm_exec_command_handlers
1556         },
1557         COMMAND_REGISTRATION_DONE
1558 };
1559
1560 struct target_type riscv_target = {
1561         .name = "riscv",
1562
1563         .init_target = riscv_init_target,
1564         .deinit_target = riscv_deinit_target,
1565         .examine = riscv_examine,
1566
1567         /* poll current target status */
1568         .poll = old_or_new_riscv_poll,
1569
1570         .halt = old_or_new_riscv_halt,
1571         .resume = old_or_new_riscv_resume,
1572         .step = old_or_new_riscv_step,
1573
1574         .assert_reset = riscv_assert_reset,
1575         .deassert_reset = riscv_deassert_reset,
1576
1577         .read_memory = riscv_read_memory,
1578         .write_memory = riscv_write_memory,
1579
1580         .checksum_memory = riscv_checksum_memory,
1581
1582         .get_gdb_reg_list = riscv_get_gdb_reg_list,
1583
1584         .add_breakpoint = riscv_add_breakpoint,
1585         .remove_breakpoint = riscv_remove_breakpoint,
1586
1587         .add_watchpoint = riscv_add_watchpoint,
1588         .remove_watchpoint = riscv_remove_watchpoint,
1589
1590         .arch_state = riscv_arch_state,
1591
1592         .run_algorithm = riscv_run_algorithm,
1593
1594         .commands = riscv_command_handlers
1595 };
1596
1597 /*** RISC-V Interface ***/
1598
1599 void riscv_info_init(struct target *target, riscv_info_t *r)
1600 {
1601         memset(r, 0, sizeof(*r));
1602         r->dtm_version = 1;
1603         r->registers_initialized = false;
1604         r->current_hartid = target->coreid;
1605
1606         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
1607
1608         for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
1609                 r->xlen[h] = -1;
1610
1611                 for (size_t e = 0; e < RISCV_MAX_REGISTERS; ++e)
1612                         r->valid_saved_registers[h][e] = false;
1613         }
1614 }
1615
1616 int riscv_halt_all_harts(struct target *target)
1617 {
1618         for (int i = 0; i < riscv_count_harts(target); ++i) {
1619                 if (!riscv_hart_enabled(target, i))
1620                         continue;
1621
1622                 riscv_halt_one_hart(target, i);
1623         }
1624
1625         return ERROR_OK;
1626 }
1627
1628 int riscv_halt_one_hart(struct target *target, int hartid)
1629 {
1630         RISCV_INFO(r);
1631         LOG_DEBUG("halting hart %d", hartid);
1632         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1633                 return ERROR_FAIL;
1634         if (riscv_is_halted(target)) {
1635                 LOG_DEBUG("  hart %d requested halt, but was already halted", hartid);
1636                 return ERROR_OK;
1637         }
1638
1639         return r->halt_current_hart(target);
1640 }
1641
1642 int riscv_resume_all_harts(struct target *target)
1643 {
1644         for (int i = 0; i < riscv_count_harts(target); ++i) {
1645                 if (!riscv_hart_enabled(target, i))
1646                         continue;
1647
1648                 riscv_resume_one_hart(target, i);
1649         }
1650
1651         riscv_invalidate_register_cache(target);
1652         return ERROR_OK;
1653 }
1654
1655 int riscv_resume_one_hart(struct target *target, int hartid)
1656 {
1657         RISCV_INFO(r);
1658         LOG_DEBUG("resuming hart %d", hartid);
1659         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1660                 return ERROR_FAIL;
1661         if (!riscv_is_halted(target)) {
1662                 LOG_DEBUG("  hart %d requested resume, but was already resumed", hartid);
1663                 return ERROR_OK;
1664         }
1665
1666         r->on_resume(target);
1667         return r->resume_current_hart(target);
1668 }
1669
1670 int riscv_step_rtos_hart(struct target *target)
1671 {
1672         RISCV_INFO(r);
1673         int hartid = r->current_hartid;
1674         if (riscv_rtos_enabled(target)) {
1675                 hartid = r->rtos_hartid;
1676                 if (hartid == -1) {
1677                         LOG_USER("GDB has asked me to step \"any\" thread, so I'm stepping hart 0.");
1678                         hartid = 0;
1679                 }
1680         }
1681         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1682                 return ERROR_FAIL;
1683         LOG_DEBUG("stepping hart %d", hartid);
1684
1685         if (!riscv_is_halted(target)) {
1686                 LOG_ERROR("Hart isn't halted before single step!");
1687                 return ERROR_FAIL;
1688         }
1689         riscv_invalidate_register_cache(target);
1690         r->on_step(target);
1691         if (r->step_current_hart(target) != ERROR_OK)
1692                 return ERROR_FAIL;
1693         riscv_invalidate_register_cache(target);
1694         r->on_halt(target);
1695         if (!riscv_is_halted(target)) {
1696                 LOG_ERROR("Hart was not halted after single step!");
1697                 return ERROR_FAIL;
1698         }
1699         return ERROR_OK;
1700 }
1701
1702 bool riscv_supports_extension(struct target *target, int hartid, char letter)
1703 {
1704         RISCV_INFO(r);
1705         unsigned num;
1706         if (letter >= 'a' && letter <= 'z')
1707                 num = letter - 'a';
1708         else if (letter >= 'A' && letter <= 'Z')
1709                 num = letter - 'A';
1710         else
1711                 return false;
1712         return r->misa[hartid] & (1 << num);
1713 }
1714
1715 int riscv_xlen(const struct target *target)
1716 {
1717         return riscv_xlen_of_hart(target, riscv_current_hartid(target));
1718 }
1719
1720 int riscv_xlen_of_hart(const struct target *target, int hartid)
1721 {
1722         RISCV_INFO(r);
1723         assert(r->xlen[hartid] != -1);
1724         return r->xlen[hartid];
1725 }
1726
1727 bool riscv_rtos_enabled(const struct target *target)
1728 {
1729         return target->rtos != NULL;
1730 }
1731
1732 int riscv_set_current_hartid(struct target *target, int hartid)
1733 {
1734         RISCV_INFO(r);
1735         if (!r->select_current_hart)
1736                 return ERROR_OK;
1737
1738         int previous_hartid = riscv_current_hartid(target);
1739         r->current_hartid = hartid;
1740         assert(riscv_hart_enabled(target, hartid));
1741         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
1742         if (r->select_current_hart(target) != ERROR_OK)
1743                 return ERROR_FAIL;
1744
1745         /* This might get called during init, in which case we shouldn't be
1746          * setting up the register cache. */
1747         if (!target_was_examined(target))
1748                 return ERROR_OK;
1749
1750         /* Avoid invalidating the register cache all the time. */
1751         if (r->registers_initialized
1752                         && (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
1753                         && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)
1754                         && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
1755                 return ERROR_OK;
1756         } else
1757                 LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
1758
1759         riscv_invalidate_register_cache(target);
1760         return ERROR_OK;
1761 }
1762
1763 void riscv_invalidate_register_cache(struct target *target)
1764 {
1765         RISCV_INFO(r);
1766
1767         register_cache_invalidate(target->reg_cache);
1768         for (size_t i = 0; i < GDB_REGNO_COUNT; ++i) {
1769                 struct reg *reg = &target->reg_cache->reg_list[i];
1770                 reg->valid = false;
1771         }
1772
1773         r->registers_initialized = true;
1774 }
1775
1776 int riscv_current_hartid(const struct target *target)
1777 {
1778         RISCV_INFO(r);
1779         return r->current_hartid;
1780 }
1781
1782 void riscv_set_all_rtos_harts(struct target *target)
1783 {
1784         RISCV_INFO(r);
1785         r->rtos_hartid = -1;
1786 }
1787
1788 void riscv_set_rtos_hartid(struct target *target, int hartid)
1789 {
1790         LOG_DEBUG("setting RTOS hartid %d", hartid);
1791         RISCV_INFO(r);
1792         r->rtos_hartid = hartid;
1793 }
1794
1795 int riscv_count_harts(struct target *target)
1796 {
1797         if (target == NULL)
1798                 return 1;
1799         RISCV_INFO(r);
1800         if (r == NULL)
1801                 return 1;
1802         return r->hart_count;
1803 }
1804
1805 bool riscv_has_register(struct target *target, int hartid, int regid)
1806 {
1807         return 1;
1808 }
1809
1810 /**
1811  * This function is called when the debug user wants to change the value of a
1812  * register. The new value may be cached, and may not be written until the hart
1813  * is resumed. */
1814 int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
1815 {
1816         return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
1817 }
1818
1819 int riscv_set_register_on_hart(struct target *target, int hartid,
1820                 enum gdb_regno regid, uint64_t value)
1821 {
1822         RISCV_INFO(r);
1823         LOG_DEBUG("[%d] %s <- %" PRIx64, hartid, gdb_regno_name(regid), value);
1824         assert(r->set_register);
1825         return r->set_register(target, hartid, regid, value);
1826 }
1827
1828 int riscv_get_register(struct target *target, riscv_reg_t *value,
1829                 enum gdb_regno r)
1830 {
1831         return riscv_get_register_on_hart(target, value,
1832                         riscv_current_hartid(target), r);
1833 }
1834
1835 int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
1836                 int hartid, enum gdb_regno regid)
1837 {
1838         RISCV_INFO(r);
1839         int result = r->get_register(target, value, hartid, regid);
1840         LOG_DEBUG("[%d] %s: %" PRIx64, hartid, gdb_regno_name(regid), *value);
1841         return result;
1842 }
1843
1844 bool riscv_is_halted(struct target *target)
1845 {
1846         RISCV_INFO(r);
1847         assert(r->is_halted);
1848         return r->is_halted(target);
1849 }
1850
1851 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
1852 {
1853         RISCV_INFO(r);
1854         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
1855                 return RISCV_HALT_ERROR;
1856         if (!riscv_is_halted(target)) {
1857                 LOG_ERROR("Hart is not halted!");
1858                 return RISCV_HALT_UNKNOWN;
1859         }
1860         return r->halt_reason(target);
1861 }
1862
1863 size_t riscv_debug_buffer_size(struct target *target)
1864 {
1865         RISCV_INFO(r);
1866         return r->debug_buffer_size[riscv_current_hartid(target)];
1867 }
1868
1869 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
1870 {
1871         RISCV_INFO(r);
1872         r->write_debug_buffer(target, index, insn);
1873         return ERROR_OK;
1874 }
1875
1876 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
1877 {
1878         RISCV_INFO(r);
1879         return r->read_debug_buffer(target, index);
1880 }
1881
1882 int riscv_execute_debug_buffer(struct target *target)
1883 {
1884         RISCV_INFO(r);
1885         return r->execute_debug_buffer(target);
1886 }
1887
1888 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
1889 {
1890         RISCV_INFO(r);
1891         r->fill_dmi_write_u64(target, buf, a, d);
1892 }
1893
1894 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
1895 {
1896         RISCV_INFO(r);
1897         r->fill_dmi_read_u64(target, buf, a);
1898 }
1899
1900 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
1901 {
1902         RISCV_INFO(r);
1903         r->fill_dmi_nop_u64(target, buf);
1904 }
1905
1906 int riscv_dmi_write_u64_bits(struct target *target)
1907 {
1908         RISCV_INFO(r);
1909         return r->dmi_write_u64_bits(target);
1910 }
1911
1912 bool riscv_hart_enabled(struct target *target, int hartid)
1913 {
1914         /* FIXME: Add a hart mask to the RTOS. */
1915         if (riscv_rtos_enabled(target))
1916                 return hartid < riscv_count_harts(target);
1917
1918         return hartid == target->coreid;
1919 }
1920
1921 /**
1922  * Count triggers, and initialize trigger_count for each hart.
1923  * trigger_count is initialized even if this function fails to discover
1924  * something.
1925  * Disable any hardware triggers that have dmode set. We can't have set them
1926  * ourselves. Maybe they're left over from some killed debug session.
1927  * */
1928 int riscv_enumerate_triggers(struct target *target)
1929 {
1930         RISCV_INFO(r);
1931
1932         if (r->triggers_enumerated)
1933                 return ERROR_OK;
1934
1935         r->triggers_enumerated = true;  /* At the very least we tried. */
1936
1937         for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
1938                 if (!riscv_hart_enabled(target, hartid))
1939                         continue;
1940
1941                 riscv_reg_t tselect;
1942                 int result = riscv_get_register_on_hart(target, &tselect, hartid,
1943                                 GDB_REGNO_TSELECT);
1944                 if (result != ERROR_OK)
1945                         return result;
1946
1947                 for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
1948                         r->trigger_count[hartid] = t;
1949
1950                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
1951                         uint64_t tselect_rb;
1952                         result = riscv_get_register_on_hart(target, &tselect_rb, hartid,
1953                                         GDB_REGNO_TSELECT);
1954                         if (result != ERROR_OK)
1955                                 return result;
1956                         /* Mask off the top bit, which is used as tdrmode in old
1957                          * implementations. */
1958                         tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
1959                         if (tselect_rb != t)
1960                                 break;
1961                         uint64_t tdata1;
1962                         result = riscv_get_register_on_hart(target, &tdata1, hartid,
1963                                         GDB_REGNO_TDATA1);
1964                         if (result != ERROR_OK)
1965                                 return result;
1966
1967                         int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
1968                         switch (type) {
1969                                 case 1:
1970                                         /* On these older cores we don't support software using
1971                                          * triggers. */
1972                                         riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
1973                                         break;
1974                                 case 2:
1975                                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
1976                                                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
1977                                         break;
1978                         }
1979                 }
1980
1981                 riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
1982
1983                 LOG_INFO("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
1984         }
1985
1986         return ERROR_OK;
1987 }
1988
1989 const char *gdb_regno_name(enum gdb_regno regno)
1990 {
1991         static char buf[32];
1992
1993         switch (regno) {
1994                 case GDB_REGNO_ZERO:
1995                         return "zero";
1996                 case GDB_REGNO_S0:
1997                         return "s0";
1998                 case GDB_REGNO_S1:
1999                         return "s1";
2000                 case GDB_REGNO_PC:
2001                         return "pc";
2002                 case GDB_REGNO_FPR0:
2003                         return "fpr0";
2004                 case GDB_REGNO_FPR31:
2005                         return "fpr31";
2006                 case GDB_REGNO_CSR0:
2007                         return "csr0";
2008                 case GDB_REGNO_TSELECT:
2009                         return "tselect";
2010                 case GDB_REGNO_TDATA1:
2011                         return "tdata1";
2012                 case GDB_REGNO_TDATA2:
2013                         return "tdata2";
2014                 case GDB_REGNO_MISA:
2015                         return "misa";
2016                 case GDB_REGNO_DPC:
2017                         return "dpc";
2018                 case GDB_REGNO_DCSR:
2019                         return "dcsr";
2020                 case GDB_REGNO_DSCRATCH:
2021                         return "dscratch";
2022                 case GDB_REGNO_MSTATUS:
2023                         return "mstatus";
2024                 case GDB_REGNO_PRIV:
2025                         return "priv";
2026                 default:
2027                         if (regno <= GDB_REGNO_XPR31)
2028                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
2029                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
2030                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
2031                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
2032                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
2033                         else
2034                                 sprintf(buf, "gdb_regno_%d", regno);
2035                         return buf;
2036         }
2037 }
2038
2039 static int register_get(struct reg *reg)
2040 {
2041         struct target *target = (struct target *) reg->arch_info;
2042         uint64_t value;
2043         int result = riscv_get_register(target, &value, reg->number);
2044         if (result != ERROR_OK)
2045                 return result;
2046         buf_set_u64(reg->value, 0, reg->size, value);
2047         return ERROR_OK;
2048 }
2049
2050 static int register_set(struct reg *reg, uint8_t *buf)
2051 {
2052         struct target *target = (struct target *) reg->arch_info;
2053
2054         uint64_t value = buf_get_u64(buf, 0, reg->size);
2055
2056         LOG_DEBUG("write 0x%" PRIx64 " to %s", value, reg->name);
2057         struct reg *r = &target->reg_cache->reg_list[reg->number];
2058         r->valid = true;
2059         memcpy(r->value, buf, (r->size + 7) / 8);
2060
2061         riscv_set_register(target, reg->number, value);
2062         return ERROR_OK;
2063 }
2064
2065 static struct reg_arch_type riscv_reg_arch_type = {
2066         .get = register_get,
2067         .set = register_set
2068 };
2069
2070 struct csr_info {
2071         unsigned number;
2072         const char *name;
2073 };
2074
2075 static int cmp_csr_info(const void *p1, const void *p2)
2076 {
2077         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
2078 }
2079
2080 int riscv_init_registers(struct target *target)
2081 {
2082         RISCV_INFO(info);
2083
2084         if (target->reg_cache) {
2085                 if (target->reg_cache->reg_list)
2086                         free(target->reg_cache->reg_list);
2087                 free(target->reg_cache);
2088         }
2089
2090         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
2091         target->reg_cache->name = "RISC-V Registers";
2092         target->reg_cache->num_regs = GDB_REGNO_COUNT;
2093
2094         target->reg_cache->reg_list = calloc(GDB_REGNO_COUNT, sizeof(struct reg));
2095
2096         const unsigned int max_reg_name_len = 12;
2097         if (info->reg_names)
2098                 free(info->reg_names);
2099         info->reg_names = calloc(1, GDB_REGNO_COUNT * max_reg_name_len);
2100         char *reg_name = info->reg_names;
2101
2102         static struct reg_feature feature_cpu = {
2103                 .name = "org.gnu.gdb.riscv.cpu"
2104         };
2105         static struct reg_feature feature_fpu = {
2106                 .name = "org.gnu.gdb.riscv.fpu"
2107         };
2108         static struct reg_feature feature_csr = {
2109                 .name = "org.gnu.gdb.riscv.csr"
2110         };
2111         static struct reg_feature feature_virtual = {
2112                 .name = "org.gnu.gdb.riscv.virtual"
2113         };
2114
2115         static struct reg_data_type type_ieee_single = {
2116                 .type = REG_TYPE_IEEE_SINGLE,
2117                 .id = "ieee_single"
2118         };
2119         static struct reg_data_type type_ieee_double = {
2120                 .type = REG_TYPE_IEEE_DOUBLE,
2121                 .id = "ieee_double"
2122         };
2123         struct csr_info csr_info[] = {
2124 #define DECLARE_CSR(name, number) { number, #name },
2125 #include "encoding.h"
2126 #undef DECLARE_CSR
2127         };
2128         /* encoding.h does not contain the registers in sorted order. */
2129         qsort(csr_info, DIM(csr_info), sizeof(*csr_info), cmp_csr_info);
2130         unsigned csr_info_index = 0;
2131
2132         /* When gdb request register N, gdb_get_register_packet() assumes that this
2133          * is register at index N in reg_list. So if there are certain registers
2134          * that don't exist, we need to leave holes in the list (or renumber, but
2135          * it would be nice not to have yet another set of numbers to translate
2136          * between). */
2137         for (uint32_t number = 0; number < GDB_REGNO_COUNT; number++) {
2138                 struct reg *r = &target->reg_cache->reg_list[number];
2139                 r->dirty = false;
2140                 r->valid = false;
2141                 r->exist = true;
2142                 r->type = &riscv_reg_arch_type;
2143                 r->arch_info = target;
2144                 r->number = number;
2145                 r->size = riscv_xlen(target);
2146                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
2147                  * target is in theory allowed to change XLEN on us. But I expect a lot
2148                  * of other things to break in that case as well. */
2149                 if (number <= GDB_REGNO_XPR31) {
2150                         r->caller_save = true;
2151                         switch (number) {
2152                                 case GDB_REGNO_ZERO:
2153                                         r->name = "zero";
2154                                         break;
2155                                 case GDB_REGNO_RA:
2156                                         r->name = "ra";
2157                                         break;
2158                                 case GDB_REGNO_SP:
2159                                         r->name = "sp";
2160                                         break;
2161                                 case GDB_REGNO_GP:
2162                                         r->name = "gp";
2163                                         break;
2164                                 case GDB_REGNO_TP:
2165                                         r->name = "tp";
2166                                         break;
2167                                 case GDB_REGNO_T0:
2168                                         r->name = "t0";
2169                                         break;
2170                                 case GDB_REGNO_T1:
2171                                         r->name = "t1";
2172                                         break;
2173                                 case GDB_REGNO_T2:
2174                                         r->name = "t2";
2175                                         break;
2176                                 case GDB_REGNO_FP:
2177                                         r->name = "fp";
2178                                         break;
2179                                 case GDB_REGNO_S1:
2180                                         r->name = "s1";
2181                                         break;
2182                                 case GDB_REGNO_A0:
2183                                         r->name = "a0";
2184                                         break;
2185                                 case GDB_REGNO_A1:
2186                                         r->name = "a1";
2187                                         break;
2188                                 case GDB_REGNO_A2:
2189                                         r->name = "a2";
2190                                         break;
2191                                 case GDB_REGNO_A3:
2192                                         r->name = "a3";
2193                                         break;
2194                                 case GDB_REGNO_A4:
2195                                         r->name = "a4";
2196                                         break;
2197                                 case GDB_REGNO_A5:
2198                                         r->name = "a5";
2199                                         break;
2200                                 case GDB_REGNO_A6:
2201                                         r->name = "a6";
2202                                         break;
2203                                 case GDB_REGNO_A7:
2204                                         r->name = "a7";
2205                                         break;
2206                                 case GDB_REGNO_S2:
2207                                         r->name = "s2";
2208                                         break;
2209                                 case GDB_REGNO_S3:
2210                                         r->name = "s3";
2211                                         break;
2212                                 case GDB_REGNO_S4:
2213                                         r->name = "s4";
2214                                         break;
2215                                 case GDB_REGNO_S5:
2216                                         r->name = "s5";
2217                                         break;
2218                                 case GDB_REGNO_S6:
2219                                         r->name = "s6";
2220                                         break;
2221                                 case GDB_REGNO_S7:
2222                                         r->name = "s7";
2223                                         break;
2224                                 case GDB_REGNO_S8:
2225                                         r->name = "s8";
2226                                         break;
2227                                 case GDB_REGNO_S9:
2228                                         r->name = "s9";
2229                                         break;
2230                                 case GDB_REGNO_S10:
2231                                         r->name = "s10";
2232                                         break;
2233                                 case GDB_REGNO_S11:
2234                                         r->name = "s11";
2235                                         break;
2236                                 case GDB_REGNO_T3:
2237                                         r->name = "t3";
2238                                         break;
2239                                 case GDB_REGNO_T4:
2240                                         r->name = "t4";
2241                                         break;
2242                                 case GDB_REGNO_T5:
2243                                         r->name = "t5";
2244                                         break;
2245                                 case GDB_REGNO_T6:
2246                                         r->name = "t6";
2247                                         break;
2248                         }
2249                         r->group = "general";
2250                         r->feature = &feature_cpu;
2251                 } else if (number == GDB_REGNO_PC) {
2252                         r->caller_save = true;
2253                         sprintf(reg_name, "pc");
2254                         r->group = "general";
2255                         r->feature = &feature_cpu;
2256                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
2257                         r->caller_save = true;
2258                         if (riscv_supports_extension(target, riscv_current_hartid(target),
2259                                                 'D')) {
2260                                 r->reg_data_type = &type_ieee_double;
2261                                 r->size = 64;
2262                         } else if (riscv_supports_extension(target,
2263                                                 riscv_current_hartid(target), 'F')) {
2264                                 r->reg_data_type = &type_ieee_single;
2265                                 r->size = 32;
2266                         } else {
2267                                 r->exist = false;
2268                         }
2269                         switch (number) {
2270                                 case GDB_REGNO_FT0:
2271                                         r->name = "ft0";
2272                                         break;
2273                                 case GDB_REGNO_FT1:
2274                                         r->name = "ft1";
2275                                         break;
2276                                 case GDB_REGNO_FT2:
2277                                         r->name = "ft2";
2278                                         break;
2279                                 case GDB_REGNO_FT3:
2280                                         r->name = "ft3";
2281                                         break;
2282                                 case GDB_REGNO_FT4:
2283                                         r->name = "ft4";
2284                                         break;
2285                                 case GDB_REGNO_FT5:
2286                                         r->name = "ft5";
2287                                         break;
2288                                 case GDB_REGNO_FT6:
2289                                         r->name = "ft6";
2290                                         break;
2291                                 case GDB_REGNO_FT7:
2292                                         r->name = "ft7";
2293                                         break;
2294                                 case GDB_REGNO_FS0:
2295                                         r->name = "fs0";
2296                                         break;
2297                                 case GDB_REGNO_FS1:
2298                                         r->name = "fs1";
2299                                         break;
2300                                 case GDB_REGNO_FA0:
2301                                         r->name = "fa0";
2302                                         break;
2303                                 case GDB_REGNO_FA1:
2304                                         r->name = "fa1";
2305                                         break;
2306                                 case GDB_REGNO_FA2:
2307                                         r->name = "fa2";
2308                                         break;
2309                                 case GDB_REGNO_FA3:
2310                                         r->name = "fa3";
2311                                         break;
2312                                 case GDB_REGNO_FA4:
2313                                         r->name = "fa4";
2314                                         break;
2315                                 case GDB_REGNO_FA5:
2316                                         r->name = "fa5";
2317                                         break;
2318                                 case GDB_REGNO_FA6:
2319                                         r->name = "fa6";
2320                                         break;
2321                                 case GDB_REGNO_FA7:
2322                                         r->name = "fa7";
2323                                         break;
2324                                 case GDB_REGNO_FS2:
2325                                         r->name = "fs2";
2326                                         break;
2327                                 case GDB_REGNO_FS3:
2328                                         r->name = "fs3";
2329                                         break;
2330                                 case GDB_REGNO_FS4:
2331                                         r->name = "fs4";
2332                                         break;
2333                                 case GDB_REGNO_FS5:
2334                                         r->name = "fs5";
2335                                         break;
2336                                 case GDB_REGNO_FS6:
2337                                         r->name = "fs6";
2338                                         break;
2339                                 case GDB_REGNO_FS7:
2340                                         r->name = "fs7";
2341                                         break;
2342                                 case GDB_REGNO_FS8:
2343                                         r->name = "fs8";
2344                                         break;
2345                                 case GDB_REGNO_FS9:
2346                                         r->name = "fs9";
2347                                         break;
2348                                 case GDB_REGNO_FS10:
2349                                         r->name = "fs10";
2350                                         break;
2351                                 case GDB_REGNO_FS11:
2352                                         r->name = "fs11";
2353                                         break;
2354                                 case GDB_REGNO_FT8:
2355                                         r->name = "ft8";
2356                                         break;
2357                                 case GDB_REGNO_FT9:
2358                                         r->name = "ft9";
2359                                         break;
2360                                 case GDB_REGNO_FT10:
2361                                         r->name = "ft10";
2362                                         break;
2363                                 case GDB_REGNO_FT11:
2364                                         r->name = "ft11";
2365                                         break;
2366                         }
2367                         r->group = "float";
2368                         r->feature = &feature_fpu;
2369                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
2370                         r->group = "csr";
2371                         r->feature = &feature_csr;
2372                         unsigned csr_number = number - GDB_REGNO_CSR0;
2373
2374                         while (csr_info[csr_info_index].number < csr_number &&
2375                                         csr_info_index < DIM(csr_info) - 1) {
2376                                 csr_info_index++;
2377                         }
2378                         if (csr_info[csr_info_index].number == csr_number) {
2379                                 r->name = csr_info[csr_info_index].name;
2380                         } else {
2381                                 sprintf(reg_name, "csr%d", csr_number);
2382                                 /* Assume unnamed registers don't exist, unless we have some
2383                                  * configuration that tells us otherwise. That's important
2384                                  * because eg. Eclipse crashes if a target has too many
2385                                  * registers, and apparently has no way of only showing a
2386                                  * subset of registers in any case. */
2387                                 r->exist = false;
2388                         }
2389
2390                         switch (csr_number) {
2391                                 case CSR_FFLAGS:
2392                                 case CSR_FRM:
2393                                 case CSR_FCSR:
2394                                         r->exist = riscv_supports_extension(target,
2395                                                         riscv_current_hartid(target), 'F');
2396                                         r->group = "float";
2397                                         r->feature = &feature_fpu;
2398                                         break;
2399                                 case CSR_SSTATUS:
2400                                 case CSR_STVEC:
2401                                 case CSR_SIP:
2402                                 case CSR_SIE:
2403                                 case CSR_SCOUNTEREN:
2404                                 case CSR_SSCRATCH:
2405                                 case CSR_SEPC:
2406                                 case CSR_SCAUSE:
2407                                 case CSR_STVAL:
2408                                 case CSR_SATP:
2409                                         r->exist = riscv_supports_extension(target,
2410                                                         riscv_current_hartid(target), 'S');
2411                                         break;
2412                                 case CSR_MEDELEG:
2413                                 case CSR_MIDELEG:
2414                                         /* "In systems with only M-mode, or with both M-mode and
2415                                          * U-mode but without U-mode trap support, the medeleg and
2416                                          * mideleg registers should not exist." */
2417                                         r->exist = riscv_supports_extension(target, riscv_current_hartid(target), 'S') ||
2418                                                 riscv_supports_extension(target, riscv_current_hartid(target), 'N');
2419                                         break;
2420
2421                                 case CSR_CYCLEH:
2422                                 case CSR_TIMEH:
2423                                 case CSR_INSTRETH:
2424                                 case CSR_HPMCOUNTER3H:
2425                                 case CSR_HPMCOUNTER4H:
2426                                 case CSR_HPMCOUNTER5H:
2427                                 case CSR_HPMCOUNTER6H:
2428                                 case CSR_HPMCOUNTER7H:
2429                                 case CSR_HPMCOUNTER8H:
2430                                 case CSR_HPMCOUNTER9H:
2431                                 case CSR_HPMCOUNTER10H:
2432                                 case CSR_HPMCOUNTER11H:
2433                                 case CSR_HPMCOUNTER12H:
2434                                 case CSR_HPMCOUNTER13H:
2435                                 case CSR_HPMCOUNTER14H:
2436                                 case CSR_HPMCOUNTER15H:
2437                                 case CSR_HPMCOUNTER16H:
2438                                 case CSR_HPMCOUNTER17H:
2439                                 case CSR_HPMCOUNTER18H:
2440                                 case CSR_HPMCOUNTER19H:
2441                                 case CSR_HPMCOUNTER20H:
2442                                 case CSR_HPMCOUNTER21H:
2443                                 case CSR_HPMCOUNTER22H:
2444                                 case CSR_HPMCOUNTER23H:
2445                                 case CSR_HPMCOUNTER24H:
2446                                 case CSR_HPMCOUNTER25H:
2447                                 case CSR_HPMCOUNTER26H:
2448                                 case CSR_HPMCOUNTER27H:
2449                                 case CSR_HPMCOUNTER28H:
2450                                 case CSR_HPMCOUNTER29H:
2451                                 case CSR_HPMCOUNTER30H:
2452                                 case CSR_HPMCOUNTER31H:
2453                                 case CSR_MCYCLEH:
2454                                 case CSR_MINSTRETH:
2455                                 case CSR_MHPMCOUNTER3H:
2456                                 case CSR_MHPMCOUNTER4H:
2457                                 case CSR_MHPMCOUNTER5H:
2458                                 case CSR_MHPMCOUNTER6H:
2459                                 case CSR_MHPMCOUNTER7H:
2460                                 case CSR_MHPMCOUNTER8H:
2461                                 case CSR_MHPMCOUNTER9H:
2462                                 case CSR_MHPMCOUNTER10H:
2463                                 case CSR_MHPMCOUNTER11H:
2464                                 case CSR_MHPMCOUNTER12H:
2465                                 case CSR_MHPMCOUNTER13H:
2466                                 case CSR_MHPMCOUNTER14H:
2467                                 case CSR_MHPMCOUNTER15H:
2468                                 case CSR_MHPMCOUNTER16H:
2469                                 case CSR_MHPMCOUNTER17H:
2470                                 case CSR_MHPMCOUNTER18H:
2471                                 case CSR_MHPMCOUNTER19H:
2472                                 case CSR_MHPMCOUNTER20H:
2473                                 case CSR_MHPMCOUNTER21H:
2474                                 case CSR_MHPMCOUNTER22H:
2475                                 case CSR_MHPMCOUNTER23H:
2476                                 case CSR_MHPMCOUNTER24H:
2477                                 case CSR_MHPMCOUNTER25H:
2478                                 case CSR_MHPMCOUNTER26H:
2479                                 case CSR_MHPMCOUNTER27H:
2480                                 case CSR_MHPMCOUNTER28H:
2481                                 case CSR_MHPMCOUNTER29H:
2482                                 case CSR_MHPMCOUNTER30H:
2483                                 case CSR_MHPMCOUNTER31H:
2484                                         r->exist = riscv_xlen(target) == 32;
2485                                         break;
2486                         }
2487
2488                         if (!r->exist && expose_csr) {
2489                                 for (unsigned i = 0; expose_csr[i].low <= expose_csr[i].high; i++) {
2490                                         if (csr_number >= expose_csr[i].low && csr_number <= expose_csr[i].high) {
2491                                                 LOG_INFO("Exposing additional CSR %d", csr_number);
2492                                                 r->exist = true;
2493                                                 break;
2494                                         }
2495                                 }
2496                         }
2497
2498                 } else if (number == GDB_REGNO_PRIV) {
2499                         sprintf(reg_name, "priv");
2500                         r->group = "general";
2501                         r->feature = &feature_virtual;
2502                         r->size = 8;
2503                 }
2504                 if (reg_name[0])
2505                         r->name = reg_name;
2506                 reg_name += strlen(reg_name) + 1;
2507                 assert(reg_name < info->reg_names + GDB_REGNO_COUNT * max_reg_name_len);
2508                 r->value = &info->reg_cache_values[number];
2509         }
2510
2511         return ERROR_OK;
2512 }