git.sur5r.net Git - openocd/blob - src/target/xscale.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2009 Michael Schwingen                                  *
   9  *   michael@schwingen.org                                                 *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "breakpoints.h"
  32 #include "xscale.h"
  33 #include "target_type.h"
  34 #include "arm_jtag.h"
  35 #include "arm_simulator.h"
  36 #include "arm_disassembler.h"
  37 #include <helper/time_support.h>
  38 #include "register.h"
  39 #include "image.h"
  40 #include "arm_opcodes.h"
  41 #include "armv4_5.h"
  42
  43 /*
  44  * Important XScale documents available as of October 2009 include:
  45  *
  46  *  Intel XScale® Core Developer’s Manual, January 2004
  47  *              Order Number: 273473-002
  48  *      This has a chapter detailing debug facilities, and punts some
  49  *      details to chip-specific microarchitecture documents.
  50  *
  51  *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  52  *              Document Number: 273539-005
  53  *      Less detailed than the developer's manual, but summarizes those
  54  *      missing details (for most XScales) and gives LOTS of notes about
  55  *      debugger/handler interaction issues.  Presents a simpler reset
  56  *      and load-handler sequence than the arch doc.  (Note, OpenOCD
  57  *      doesn't currently support "Hot-Debug" as defined there.)
  58  *
  59  * Chip-specific microarchitecture documents may also be useful.
  60  */
  61
  62 /* forward declarations */
  63 static int xscale_resume(struct target *, int current,
  64         uint32_t address, int handle_breakpoints, int debug_execution);
  65 static int xscale_debug_entry(struct target *);
  66 static int xscale_restore_banked(struct target *);
  67 static int xscale_get_reg(struct reg *reg);
  68 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
  69 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
  70 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
  71 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
  72 static int xscale_read_trace(struct target *);
  73
  74 /* This XScale "debug handler" is loaded into the processor's
  75  * mini-ICache, which is 2K of code writable only via JTAG.
  76  *
  77  * FIXME  the OpenOCD "bin2char" utility currently doesn't handle
  78  * binary files cleanly.  It's string oriented, and terminates them
  79  * with a NUL character.  Better would be to generate the constants
  80  * and let other code decide names, scoping, and other housekeeping.
  81  */
  82 static  /* unsigned const char xscale_debug_handler[] = ... */
  83 #include "xscale_debug.h"
  84
  85 static char *const xscale_reg_list[] = {
  86         "XSCALE_MAINID",                /* 0 */
  87         "XSCALE_CACHETYPE",
  88         "XSCALE_CTRL",
  89         "XSCALE_AUXCTRL",
  90         "XSCALE_TTB",
  91         "XSCALE_DAC",
  92         "XSCALE_FSR",
  93         "XSCALE_FAR",
  94         "XSCALE_PID",
  95         "XSCALE_CPACCESS",
  96         "XSCALE_IBCR0",                 /* 10 */
  97         "XSCALE_IBCR1",
  98         "XSCALE_DBR0",
  99         "XSCALE_DBR1",
 100         "XSCALE_DBCON",
 101         "XSCALE_TBREG",
 102         "XSCALE_CHKPT0",
 103         "XSCALE_CHKPT1",
 104         "XSCALE_DCSR",
 105         "XSCALE_TX",
 106         "XSCALE_RX",                    /* 20 */
 107         "XSCALE_TXRXCTRL",
 108 };
 109
 110 static const struct xscale_reg xscale_reg_arch_info[] = {
 111         {XSCALE_MAINID, NULL},
 112         {XSCALE_CACHETYPE, NULL},
 113         {XSCALE_CTRL, NULL},
 114         {XSCALE_AUXCTRL, NULL},
 115         {XSCALE_TTB, NULL},
 116         {XSCALE_DAC, NULL},
 117         {XSCALE_FSR, NULL},
 118         {XSCALE_FAR, NULL},
 119         {XSCALE_PID, NULL},
 120         {XSCALE_CPACCESS, NULL},
 121         {XSCALE_IBCR0, NULL},
 122         {XSCALE_IBCR1, NULL},
 123         {XSCALE_DBR0, NULL},
 124         {XSCALE_DBR1, NULL},
 125         {XSCALE_DBCON, NULL},
 126         {XSCALE_TBREG, NULL},
 127         {XSCALE_CHKPT0, NULL},
 128         {XSCALE_CHKPT1, NULL},
 129         {XSCALE_DCSR, NULL},    /* DCSR accessed via JTAG or SW */
 130         {-1, NULL},     /* TX accessed via JTAG */
 131         {-1, NULL},     /* RX accessed via JTAG */
 132         {-1, NULL},     /* TXRXCTRL implicit access via JTAG */
 133 };
 134
 135 /* convenience wrapper to access XScale specific registers */
 136 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 137 {
 138         uint8_t buf[4];
 139
 140         buf_set_u32(buf, 0, 32, value);
 141
 142         return xscale_set_reg(reg, buf);
 143 }
 144
 145 static const char xscale_not[] = "target is not an XScale";
 146
 147 static int xscale_verify_pointer(struct command_context *cmd_ctx,
 148         struct xscale_common *xscale)
 149 {
 150         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
 151                 command_print(cmd_ctx, xscale_not);
 152                 return ERROR_TARGET_INVALID;
 153         }
 154         return ERROR_OK;
 155 }
 156
 157 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 158 {
 159         assert(tap != NULL);
 160
 161         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
 162                 struct scan_field field;
 163                 uint8_t scratch[4];
 164
 165                 memset(&field, 0, sizeof field);
 166                 field.num_bits = tap->ir_length;
 167                 field.out_value = scratch;
 168                 buf_set_u32(scratch, 0, field.num_bits, new_instr);
 169
 170                 jtag_add_ir_scan(tap, &field, end_state);
 171         }
 172
 173         return ERROR_OK;
 174 }
 175
 176 static int xscale_read_dcsr(struct target *target)
 177 {
 178         struct xscale_common *xscale = target_to_xscale(target);
 179         int retval;
 180         struct scan_field fields[3];
 181         uint8_t field0 = 0x0;
 182         uint8_t field0_check_value = 0x2;
 183         uint8_t field0_check_mask = 0x7;
 184         uint8_t field2 = 0x0;
 185         uint8_t field2_check_value = 0x0;
 186         uint8_t field2_check_mask = 0x1;
 187
 188         xscale_jtag_set_instr(target->tap,
 189                 XSCALE_SELDCSR << xscale->xscale_variant,
 190                 TAP_DRPAUSE);
 191
 192         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 193         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 194
 195         memset(&fields, 0, sizeof fields);
 196
 197         fields[0].num_bits = 3;
 198         fields[0].out_value = &field0;
 199         uint8_t tmp;
 200         fields[0].in_value = &tmp;
 201
 202         fields[1].num_bits = 32;
 203         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 204
 205         fields[2].num_bits = 1;
 206         fields[2].out_value = &field2;
 207         uint8_t tmp2;
 208         fields[2].in_value = &tmp2;
 209
 210         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 211
 212         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 213         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 214
 215         retval = jtag_execute_queue();
 216         if (retval != ERROR_OK) {
 217                 LOG_ERROR("JTAG error while reading DCSR");
 218                 return retval;
 219         }
 220
 221         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 222         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 223
 224         /* write the register with the value we just read
 225          * on this second pass, only the first bit of field0 is guaranteed to be 0)
 226          */
 227         field0_check_mask = 0x1;
 228         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 229         fields[1].in_value = NULL;
 230
 231         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 232
 233         /* DANGER!!! this must be here. It will make sure that the arguments
 234          * to jtag_set_check_value() does not go out of scope! */
 235         return jtag_execute_queue();
 236 }
 237
 238
 239 static void xscale_getbuf(jtag_callback_data_t arg)
 240 {
 241         uint8_t *in = (uint8_t *)arg;
 242         *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 243 }
 244
 245 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
 246 {
 247         if (num_words == 0)
 248                 return ERROR_COMMAND_SYNTAX_ERROR;
 249
 250         struct xscale_common *xscale = target_to_xscale(target);
 251         int retval = ERROR_OK;
 252         tap_state_t path[3];
 253         struct scan_field fields[3];
 254         uint8_t *field0 = malloc(num_words * 1);
 255         uint8_t field0_check_value = 0x2;
 256         uint8_t field0_check_mask = 0x6;
 257         uint32_t *field1 = malloc(num_words * 4);
 258         uint8_t field2_check_value = 0x0;
 259         uint8_t field2_check_mask = 0x1;
 260         int words_done = 0;
 261         int words_scheduled = 0;
 262         int i;
 263
 264         path[0] = TAP_DRSELECT;
 265         path[1] = TAP_DRCAPTURE;
 266         path[2] = TAP_DRSHIFT;
 267
 268         memset(&fields, 0, sizeof fields);
 269
 270         fields[0].num_bits = 3;
 271         uint8_t tmp;
 272         fields[0].in_value = &tmp;
 273         fields[0].check_value = &field0_check_value;
 274         fields[0].check_mask = &field0_check_mask;
 275
 276         fields[1].num_bits = 32;
 277
 278         fields[2].num_bits = 1;
 279         uint8_t tmp2;
 280         fields[2].in_value = &tmp2;
 281         fields[2].check_value = &field2_check_value;
 282         fields[2].check_mask = &field2_check_mask;
 283
 284         xscale_jtag_set_instr(target->tap,
 285                 XSCALE_DBGTX << xscale->xscale_variant,
 286                 TAP_IDLE);
 287         jtag_add_runtest(1, TAP_IDLE);  /* ensures that we're in the TAP_IDLE state as the above
 288                                          *could be a no-op */
 289
 290         /* repeat until all words have been collected */
 291         int attempts = 0;
 292         while (words_done < num_words) {
 293                 /* schedule reads */
 294                 words_scheduled = 0;
 295                 for (i = words_done; i < num_words; i++) {
 296                         fields[0].in_value = &field0[i];
 297
 298                         jtag_add_pathmove(3, path);
 299
 300                         fields[1].in_value = (uint8_t *)(field1 + i);
 301
 302                         jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
 303
 304                         jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
 305
 306                         words_scheduled++;
 307                 }
 308
 309                 retval = jtag_execute_queue();
 310                 if (retval != ERROR_OK) {
 311                         LOG_ERROR("JTAG error while receiving data from debug handler");
 312                         break;
 313                 }
 314
 315                 /* examine results */
 316                 for (i = words_done; i < num_words; i++) {
 317                         if (!(field0[i] & 1)) {
 318                                 /* move backwards if necessary */
 319                                 int j;
 320                                 for (j = i; j < num_words - 1; j++) {
 321                                         field0[j] = field0[j + 1];
 322                                         field1[j] = field1[j + 1];
 323                                 }
 324                                 words_scheduled--;
 325                         }
 326                 }
 327                 if (words_scheduled == 0) {
 328                         if (attempts++ == 1000) {
 329                                 LOG_ERROR(
 330                                         "Failed to receiving data from debug handler after 1000 attempts");
 331                                 retval = ERROR_TARGET_TIMEOUT;
 332                                 break;
 333                         }
 334                 }
 335
 336                 words_done += words_scheduled;
 337         }
 338
 339         for (i = 0; i < num_words; i++)
 340                 *(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32);
 341
 342         free(field1);
 343
 344         return retval;
 345 }
 346
 347 static int xscale_read_tx(struct target *target, int consume)
 348 {
 349         struct xscale_common *xscale = target_to_xscale(target);
 350         tap_state_t path[3];
 351         tap_state_t noconsume_path[6];
 352         int retval;
 353         struct timeval timeout, now;
 354         struct scan_field fields[3];
 355         uint8_t field0_in = 0x0;
 356         uint8_t field0_check_value = 0x2;
 357         uint8_t field0_check_mask = 0x6;
 358         uint8_t field2_check_value = 0x0;
 359         uint8_t field2_check_mask = 0x1;
 360
 361         xscale_jtag_set_instr(target->tap,
 362                 XSCALE_DBGTX << xscale->xscale_variant,
 363                 TAP_IDLE);
 364
 365         path[0] = TAP_DRSELECT;
 366         path[1] = TAP_DRCAPTURE;
 367         path[2] = TAP_DRSHIFT;
 368
 369         noconsume_path[0] = TAP_DRSELECT;
 370         noconsume_path[1] = TAP_DRCAPTURE;
 371         noconsume_path[2] = TAP_DREXIT1;
 372         noconsume_path[3] = TAP_DRPAUSE;
 373         noconsume_path[4] = TAP_DREXIT2;
 374         noconsume_path[5] = TAP_DRSHIFT;
 375
 376         memset(&fields, 0, sizeof fields);
 377
 378         fields[0].num_bits = 3;
 379         fields[0].in_value = &field0_in;
 380
 381         fields[1].num_bits = 32;
 382         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 383
 384         fields[2].num_bits = 1;
 385         uint8_t tmp;
 386         fields[2].in_value = &tmp;
 387
 388         gettimeofday(&timeout, NULL);
 389         timeval_add_time(&timeout, 1, 0);
 390
 391         for (;; ) {
 392                 /* if we want to consume the register content (i.e. clear TX_READY),
 393                  * we have to go straight from Capture-DR to Shift-DR
 394                  * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
 395                 */
 396                 if (consume)
 397                         jtag_add_pathmove(3, path);
 398                 else
 399                         jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
 400
 401                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 402
 403                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 404                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 405
 406                 retval = jtag_execute_queue();
 407                 if (retval != ERROR_OK) {
 408                         LOG_ERROR("JTAG error while reading TX");
 409                         return ERROR_TARGET_TIMEOUT;
 410                 }
 411
 412                 gettimeofday(&now, NULL);
 413                 if ((now.tv_sec > timeout.tv_sec) ||
 414                         ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
 415                         LOG_ERROR("time out reading TX register");
 416                         return ERROR_TARGET_TIMEOUT;
 417                 }
 418                 if (!((!(field0_in & 1)) && consume))
 419                         goto done;
 420                 if (debug_level >= 3) {
 421                         LOG_DEBUG("waiting 100ms");
 422                         alive_sleep(100);       /* avoid flooding the logs */
 423                 } else
 424                         keep_alive();
 425         }
 426 done:
 427
 428         if (!(field0_in & 1))
 429                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 430
 431         return ERROR_OK;
 432 }
 433
 434 static int xscale_write_rx(struct target *target)
 435 {
 436         struct xscale_common *xscale = target_to_xscale(target);
 437         int retval;
 438         struct timeval timeout, now;
 439         struct scan_field fields[3];
 440         uint8_t field0_out = 0x0;
 441         uint8_t field0_in = 0x0;
 442         uint8_t field0_check_value = 0x2;
 443         uint8_t field0_check_mask = 0x6;
 444         uint8_t field2 = 0x0;
 445         uint8_t field2_check_value = 0x0;
 446         uint8_t field2_check_mask = 0x1;
 447
 448         xscale_jtag_set_instr(target->tap,
 449                 XSCALE_DBGRX << xscale->xscale_variant,
 450                 TAP_IDLE);
 451
 452         memset(&fields, 0, sizeof fields);
 453
 454         fields[0].num_bits = 3;
 455         fields[0].out_value = &field0_out;
 456         fields[0].in_value = &field0_in;
 457
 458         fields[1].num_bits = 32;
 459         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 460
 461         fields[2].num_bits = 1;
 462         fields[2].out_value = &field2;
 463         uint8_t tmp;
 464         fields[2].in_value = &tmp;
 465
 466         gettimeofday(&timeout, NULL);
 467         timeval_add_time(&timeout, 1, 0);
 468
 469         /* poll until rx_read is low */
 470         LOG_DEBUG("polling RX");
 471         for (;;) {
 472                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 473
 474                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 475                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 476
 477                 retval = jtag_execute_queue();
 478                 if (retval != ERROR_OK) {
 479                         LOG_ERROR("JTAG error while writing RX");
 480                         return retval;
 481                 }
 482
 483                 gettimeofday(&now, NULL);
 484                 if ((now.tv_sec > timeout.tv_sec) ||
 485                         ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
 486                         LOG_ERROR("time out writing RX register");
 487                         return ERROR_TARGET_TIMEOUT;
 488                 }
 489                 if (!(field0_in & 1))
 490                         goto done;
 491                 if (debug_level >= 3) {
 492                         LOG_DEBUG("waiting 100ms");
 493                         alive_sleep(100);       /* avoid flooding the logs */
 494                 } else
 495                         keep_alive();
 496         }
 497 done:
 498
 499         /* set rx_valid */
 500         field2 = 0x1;
 501         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 502
 503         retval = jtag_execute_queue();
 504         if (retval != ERROR_OK) {
 505                 LOG_ERROR("JTAG error while writing RX");
 506                 return retval;
 507         }
 508
 509         return ERROR_OK;
 510 }
 511
 512 /* send count elements of size byte to the debug handler */
 513 static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
 514 {
 515         struct xscale_common *xscale = target_to_xscale(target);
 516         uint32_t t[3];
 517         int bits[3];
 518         int retval;
 519         int done_count = 0;
 520
 521         xscale_jtag_set_instr(target->tap,
 522                 XSCALE_DBGRX << xscale->xscale_variant,
 523                 TAP_IDLE);
 524
 525         bits[0] = 3;
 526         t[0] = 0;
 527         bits[1] = 32;
 528         t[2] = 1;
 529         bits[2] = 1;
 530         int endianness = target->endianness;
 531         while (done_count++ < count) {
 532                 switch (size) {
 533                         case 4:
 534                                 if (endianness == TARGET_LITTLE_ENDIAN)
 535                                         t[1] = le_to_h_u32(buffer);
 536                                 else
 537                                         t[1] = be_to_h_u32(buffer);
 538                                 break;
 539                         case 2:
 540                                 if (endianness == TARGET_LITTLE_ENDIAN)
 541                                         t[1] = le_to_h_u16(buffer);
 542                                 else
 543                                         t[1] = be_to_h_u16(buffer);
 544                                 break;
 545                         case 1:
 546                                 t[1] = buffer[0];
 547                                 break;
 548                         default:
 549                                 LOG_ERROR("BUG: size neither 4, 2 nor 1");
 550                                 return ERROR_COMMAND_SYNTAX_ERROR;
 551                 }
 552                 jtag_add_dr_out(target->tap,
 553                         3,
 554                         bits,
 555                         t,
 556                         TAP_IDLE);
 557                 buffer += size;
 558         }
 559
 560         retval = jtag_execute_queue();
 561         if (retval != ERROR_OK) {
 562                 LOG_ERROR("JTAG error while sending data to debug handler");
 563                 return retval;
 564         }
 565
 566         return ERROR_OK;
 567 }
 568
 569 static int xscale_send_u32(struct target *target, uint32_t value)
 570 {
 571         struct xscale_common *xscale = target_to_xscale(target);
 572
 573         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
 574         return xscale_write_rx(target);
 575 }
 576
 577 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
 578 {
 579         struct xscale_common *xscale = target_to_xscale(target);
 580         int retval;
 581         struct scan_field fields[3];
 582         uint8_t field0 = 0x0;
 583         uint8_t field0_check_value = 0x2;
 584         uint8_t field0_check_mask = 0x7;
 585         uint8_t field2 = 0x0;
 586         uint8_t field2_check_value = 0x0;
 587         uint8_t field2_check_mask = 0x1;
 588
 589         if (hold_rst != -1)
 590                 xscale->hold_rst = hold_rst;
 591
 592         if (ext_dbg_brk != -1)
 593                 xscale->external_debug_break = ext_dbg_brk;
 594
 595         xscale_jtag_set_instr(target->tap,
 596                 XSCALE_SELDCSR << xscale->xscale_variant,
 597                 TAP_IDLE);
 598
 599         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 600         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 601
 602         memset(&fields, 0, sizeof fields);
 603
 604         fields[0].num_bits = 3;
 605         fields[0].out_value = &field0;
 606         uint8_t tmp;
 607         fields[0].in_value = &tmp;
 608
 609         fields[1].num_bits = 32;
 610         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 611
 612         fields[2].num_bits = 1;
 613         fields[2].out_value = &field2;
 614         uint8_t tmp2;
 615         fields[2].in_value = &tmp2;
 616
 617         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 618
 619         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 620         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 621
 622         retval = jtag_execute_queue();
 623         if (retval != ERROR_OK) {
 624                 LOG_ERROR("JTAG error while writing DCSR");
 625                 return retval;
 626         }
 627
 628         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 629         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 630
 631         return ERROR_OK;
 632 }
 633
 634 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
 635 static unsigned int parity(unsigned int v)
 636 {
 637         /* unsigned int ov = v; */
 638         v ^= v >> 16;
 639         v ^= v >> 8;
 640         v ^= v >> 4;
 641         v &= 0xf;
 642         /* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
 643         return (0x6996 >> v) & 1;
 644 }
 645
 646 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
 647 {
 648         struct xscale_common *xscale = target_to_xscale(target);
 649         uint8_t packet[4];
 650         uint8_t cmd;
 651         int word;
 652         struct scan_field fields[2];
 653
 654         LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 655
 656         /* LDIC into IR */
 657         xscale_jtag_set_instr(target->tap,
 658                 XSCALE_LDIC << xscale->xscale_variant,
 659                 TAP_IDLE);
 660
 661         /* CMD is b011 to load a cacheline into the Mini ICache.
 662          * Loading into the main ICache is deprecated, and unused.
 663          * It's followed by three zero bits, and 27 address bits.
 664          */
 665         buf_set_u32(&cmd, 0, 6, 0x3);
 666
 667         /* virtual address of desired cache line */
 668         buf_set_u32(packet, 0, 27, va >> 5);
 669
 670         memset(&fields, 0, sizeof fields);
 671
 672         fields[0].num_bits = 6;
 673         fields[0].out_value = &cmd;
 674
 675         fields[1].num_bits = 27;
 676         fields[1].out_value = packet;
 677
 678         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 679
 680         /* rest of packet is a cacheline: 8 instructions, with parity */
 681         fields[0].num_bits = 32;
 682         fields[0].out_value = packet;
 683
 684         fields[1].num_bits = 1;
 685         fields[1].out_value = &cmd;
 686
 687         for (word = 0; word < 8; word++) {
 688                 buf_set_u32(packet, 0, 32, buffer[word]);
 689
 690                 uint32_t value;
 691                 memcpy(&value, packet, sizeof(uint32_t));
 692                 cmd = parity(value);
 693
 694                 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 695         }
 696
 697         return jtag_execute_queue();
 698 }
 699
 700 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 701 {
 702         struct xscale_common *xscale = target_to_xscale(target);
 703         uint8_t packet[4];
 704         uint8_t cmd;
 705         struct scan_field fields[2];
 706
 707         xscale_jtag_set_instr(target->tap,
 708                 XSCALE_LDIC << xscale->xscale_variant,
 709                 TAP_IDLE);
 710
 711         /* CMD for invalidate IC line b000, bits [6:4] b000 */
 712         buf_set_u32(&cmd, 0, 6, 0x0);
 713
 714         /* virtual address of desired cache line */
 715         buf_set_u32(packet, 0, 27, va >> 5);
 716
 717         memset(&fields, 0, sizeof fields);
 718
 719         fields[0].num_bits = 6;
 720         fields[0].out_value = &cmd;
 721
 722         fields[1].num_bits = 27;
 723         fields[1].out_value = packet;
 724
 725         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 726
 727         return ERROR_OK;
 728 }
 729
 730 static int xscale_update_vectors(struct target *target)
 731 {
 732         struct xscale_common *xscale = target_to_xscale(target);
 733         int i;
 734         int retval;
 735
 736         uint32_t low_reset_branch, high_reset_branch;
 737
 738         for (i = 1; i < 8; i++) {
 739                 /* if there's a static vector specified for this exception, override */
 740                 if (xscale->static_high_vectors_set & (1 << i))
 741                         xscale->high_vectors[i] = xscale->static_high_vectors[i];
 742                 else {
 743                         retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
 744                         if (retval == ERROR_TARGET_TIMEOUT)
 745                                 return retval;
 746                         if (retval != ERROR_OK) {
 747                                 /* Some of these reads will fail as part of normal execution */
 748                                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 749                         }
 750                 }
 751         }
 752
 753         for (i = 1; i < 8; i++) {
 754                 if (xscale->static_low_vectors_set & (1 << i))
 755                         xscale->low_vectors[i] = xscale->static_low_vectors[i];
 756                 else {
 757                         retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
 758                         if (retval == ERROR_TARGET_TIMEOUT)
 759                                 return retval;
 760                         if (retval != ERROR_OK) {
 761                                 /* Some of these reads will fail as part of normal execution */
 762                                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 763                         }
 764                 }
 765         }
 766
 767         /* calculate branches to debug handler */
 768         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
 769         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
 770
 771         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
 772         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
 773
 774         /* invalidate and load exception vectors in mini i-cache */
 775         xscale_invalidate_ic_line(target, 0x0);
 776         xscale_invalidate_ic_line(target, 0xffff0000);
 777
 778         xscale_load_ic(target, 0x0, xscale->low_vectors);
 779         xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 780
 781         return ERROR_OK;
 782 }
 783
 784 static int xscale_arch_state(struct target *target)
 785 {
 786         struct xscale_common *xscale = target_to_xscale(target);
 787         struct arm *arm = &xscale->arm;
 788
 789         static const char *state[] = {
 790                 "disabled", "enabled"
 791         };
 792
 793         static const char *arch_dbg_reason[] = {
 794                 "", "\n(processor reset)", "\n(trace buffer full)"
 795         };
 796
 797         if (arm->common_magic != ARM_COMMON_MAGIC) {
 798                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 799                 return ERROR_COMMAND_SYNTAX_ERROR;
 800         }
 801
 802         arm_arch_state(target);
 803         LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 804                 state[xscale->armv4_5_mmu.mmu_enabled],
 805                 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 806                 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
 807                 arch_dbg_reason[xscale->arch_debug_reason]);
 808
 809         return ERROR_OK;
 810 }
 811
 812 static int xscale_poll(struct target *target)
 813 {
 814         int retval = ERROR_OK;
 815
 816         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) {
 817                 enum target_state previous_state = target->state;
 818                 retval = xscale_read_tx(target, 0);
 819                 if (retval == ERROR_OK) {
 820
 821                         /* there's data to read from the tx register, we entered debug state */
 822                         target->state = TARGET_HALTED;
 823
 824                         /* process debug entry, fetching current mode regs */
 825                         retval = xscale_debug_entry(target);
 826                 } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 827                         LOG_USER("error while polling TX register, reset CPU");
 828                         /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
 829                         target->state = TARGET_HALTED;
 830                 }
 831
 832                 /* debug_entry could have overwritten target state (i.e. immediate resume)
 833                  * don't signal event handlers in that case
 834                  */
 835                 if (target->state != TARGET_HALTED)
 836                         return ERROR_OK;
 837
 838                 /* if target was running, signal that we halted
 839                  * otherwise we reentered from debug execution */
 840                 if (previous_state == TARGET_RUNNING)
 841                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 842                 else
 843                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 844         }
 845
 846         return retval;
 847 }
 848
 849 static int xscale_debug_entry(struct target *target)
 850 {
 851         struct xscale_common *xscale = target_to_xscale(target);
 852         struct arm *arm = &xscale->arm;
 853         uint32_t pc;
 854         uint32_t buffer[10];
 855         unsigned i;
 856         int retval;
 857         uint32_t moe;
 858
 859         /* clear external dbg break (will be written on next DCSR read) */
 860         xscale->external_debug_break = 0;
 861         retval = xscale_read_dcsr(target);
 862         if (retval != ERROR_OK)
 863                 return retval;
 864
 865         /* get r0, pc, r1 to r7 and cpsr */
 866         retval = xscale_receive(target, buffer, 10);
 867         if (retval != ERROR_OK)
 868                 return retval;
 869
 870         /* move r0 from buffer to register cache */
 871         buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
 872         arm->core_cache->reg_list[0].dirty = 1;
 873         arm->core_cache->reg_list[0].valid = 1;
 874         LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 875
 876         /* move pc from buffer to register cache */
 877         buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
 878         arm->pc->dirty = 1;
 879         arm->pc->valid = 1;
 880         LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 881
 882         /* move data from buffer to register cache */
 883         for (i = 1; i <= 7; i++) {
 884                 buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
 885                 arm->core_cache->reg_list[i].dirty = 1;
 886                 arm->core_cache->reg_list[i].valid = 1;
 887                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 888         }
 889
 890         arm_set_cpsr(arm, buffer[9]);
 891         LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 892
 893         if (!is_arm_mode(arm->core_mode)) {
 894                 target->state = TARGET_UNKNOWN;
 895                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
 896                 return ERROR_TARGET_FAILURE;
 897         }
 898         LOG_DEBUG("target entered debug state in %s mode",
 899                 arm_mode_name(arm->core_mode));
 900
 901         /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
 902         if (arm->spsr) {
 903                 xscale_receive(target, buffer, 8);
 904                 buf_set_u32(arm->spsr->value, 0, 32, buffer[7]);
 905                 arm->spsr->dirty = false;
 906                 arm->spsr->valid = true;
 907         } else {
 908                 /* r8 to r14, but no spsr */
 909                 xscale_receive(target, buffer, 7);
 910         }
 911
 912         /* move data from buffer to right banked register in cache */
 913         for (i = 8; i <= 14; i++) {
 914                 struct reg *r = arm_reg_current(arm, i);
 915
 916                 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
 917                 r->dirty = false;
 918                 r->valid = true;
 919         }
 920
 921         /* mark xscale regs invalid to ensure they are retrieved from the
 922          * debug handler if requested  */
 923         for (i = 0; i < xscale->reg_cache->num_regs; i++)
 924                 xscale->reg_cache->reg_list[i].valid = 0;
 925
 926         /* examine debug reason */
 927         xscale_read_dcsr(target);
 928         moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
 929
 930         /* stored PC (for calculating fixup) */
 931         pc = buf_get_u32(arm->pc->value, 0, 32);
 932
 933         switch (moe) {
 934                 case 0x0:       /* Processor reset */
 935                         target->debug_reason = DBG_REASON_DBGRQ;
 936                         xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
 937                         pc -= 4;
 938                         break;
 939                 case 0x1:       /* Instruction breakpoint hit */
 940                         target->debug_reason = DBG_REASON_BREAKPOINT;
 941                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 942                         pc -= 4;
 943                         break;
 944                 case 0x2:       /* Data breakpoint hit */
 945                         target->debug_reason = DBG_REASON_WATCHPOINT;
 946                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 947                         pc -= 4;
 948                         break;
 949                 case 0x3:       /* BKPT instruction executed */
 950                         target->debug_reason = DBG_REASON_BREAKPOINT;
 951                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 952                         pc -= 4;
 953                         break;
 954                 case 0x4:       /* Ext. debug event */
 955                         target->debug_reason = DBG_REASON_DBGRQ;
 956                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 957                         pc -= 4;
 958                         break;
 959                 case 0x5:       /* Vector trap occured */
 960                         target->debug_reason = DBG_REASON_BREAKPOINT;
 961                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 962                         pc -= 4;
 963                         break;
 964                 case 0x6:       /* Trace buffer full break */
 965                         target->debug_reason = DBG_REASON_DBGRQ;
 966                         xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
 967                         pc -= 4;
 968                         break;
 969                 case 0x7:       /* Reserved (may flag Hot-Debug support) */
 970                 default:
 971                         LOG_ERROR("Method of Entry is 'Reserved'");
 972                         exit(-1);
 973                         break;
 974         }
 975
 976         /* apply PC fixup */
 977         buf_set_u32(arm->pc->value, 0, 32, pc);
 978
 979         /* on the first debug entry, identify cache type */
 980         if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) {
 981                 uint32_t cache_type_reg;
 982
 983                 /* read cp15 cache type register */
 984                 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
 985                 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value,
 986                                 0,
 987                                 32);
 988
 989                 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
 990         }
 991
 992         /* examine MMU and Cache settings
 993          * read cp15 control register */
 994         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
 995         xscale->cp15_control_reg =
 996                 buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 997         xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
 998         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 999                 (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1000         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
1001                 (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1002
1003         /* tracing enabled, read collected trace data */
1004         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1005                 xscale_read_trace(target);
1006
1007                 /* Resume if entered debug due to buffer fill and we're still collecting
1008                  * trace data.  Note that a debug exception due to trace buffer full
1009                  * can only happen in fill mode. */
1010                 if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) {
1011                         if (--xscale->trace.fill_counter > 0)
1012                                 xscale_resume(target, 1, 0x0, 1, 0);
1013                 } else  /* entered debug for other reason; reset counter */
1014                         xscale->trace.fill_counter = 0;
1015         }
1016
1017         return ERROR_OK;
1018 }
1019
1020 static int xscale_halt(struct target *target)
1021 {
1022         struct xscale_common *xscale = target_to_xscale(target);
1023
1024         LOG_DEBUG("target->state: %s",
1025                 target_state_name(target));
1026
1027         if (target->state == TARGET_HALTED) {
1028                 LOG_DEBUG("target was already halted");
1029                 return ERROR_OK;
1030         } else if (target->state == TARGET_UNKNOWN) {
1031                 /* this must not happen for a xscale target */
1032                 LOG_ERROR("target was in unknown state when halt was requested");
1033                 return ERROR_TARGET_INVALID;
1034         } else if (target->state == TARGET_RESET)
1035                 LOG_DEBUG("target->state == TARGET_RESET");
1036         else {
1037                 /* assert external dbg break */
1038                 xscale->external_debug_break = 1;
1039                 xscale_read_dcsr(target);
1040
1041                 target->debug_reason = DBG_REASON_DBGRQ;
1042         }
1043
1044         return ERROR_OK;
1045 }
1046
1047 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1048 {
1049         struct xscale_common *xscale = target_to_xscale(target);
1050         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1051         int retval;
1052
1053         if (xscale->ibcr0_used) {
1054                 struct breakpoint *ibcr0_bp =
1055                         breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1056
1057                 if (ibcr0_bp)
1058                         xscale_unset_breakpoint(target, ibcr0_bp);
1059                 else {
1060                         LOG_ERROR(
1061                                 "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1062                         exit(-1);
1063                 }
1064         }
1065
1066         retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1067         if (retval != ERROR_OK)
1068                 return retval;
1069
1070         return ERROR_OK;
1071 }
1072
1073 static int xscale_disable_single_step(struct target *target)
1074 {
1075         struct xscale_common *xscale = target_to_xscale(target);
1076         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1077         int retval;
1078
1079         retval = xscale_set_reg_u32(ibcr0, 0x0);
1080         if (retval != ERROR_OK)
1081                 return retval;
1082
1083         return ERROR_OK;
1084 }
1085
1086 static void xscale_enable_watchpoints(struct target *target)
1087 {
1088         struct watchpoint *watchpoint = target->watchpoints;
1089
1090         while (watchpoint) {
1091                 if (watchpoint->set == 0)
1092                         xscale_set_watchpoint(target, watchpoint);
1093                 watchpoint = watchpoint->next;
1094         }
1095 }
1096
1097 static void xscale_enable_breakpoints(struct target *target)
1098 {
1099         struct breakpoint *breakpoint = target->breakpoints;
1100
1101         /* set any pending breakpoints */
1102         while (breakpoint) {
1103                 if (breakpoint->set == 0)
1104                         xscale_set_breakpoint(target, breakpoint);
1105                 breakpoint = breakpoint->next;
1106         }
1107 }
1108
1109 static void xscale_free_trace_data(struct xscale_common *xscale)
1110 {
1111         struct xscale_trace_data *td = xscale->trace.data;
1112         while (td) {
1113                 struct xscale_trace_data *next_td = td->next;
1114                 if (td->entries)
1115                         free(td->entries);
1116                 free(td);
1117                 td = next_td;
1118         }
1119         xscale->trace.data = NULL;
1120 }
1121
1122 static int xscale_resume(struct target *target, int current,
1123         uint32_t address, int handle_breakpoints, int debug_execution)
1124 {
1125         struct xscale_common *xscale = target_to_xscale(target);
1126         struct arm *arm = &xscale->arm;
1127         uint32_t current_pc;
1128         int retval;
1129         int i;
1130
1131         LOG_DEBUG("-");
1132
1133         if (target->state != TARGET_HALTED) {
1134                 LOG_WARNING("target not halted");
1135                 return ERROR_TARGET_NOT_HALTED;
1136         }
1137
1138         if (!debug_execution)
1139                 target_free_all_working_areas(target);
1140
1141         /* update vector tables */
1142         retval = xscale_update_vectors(target);
1143         if (retval != ERROR_OK)
1144                 return retval;
1145
1146         /* current = 1: continue on current pc, otherwise continue at <address> */
1147         if (!current)
1148                 buf_set_u32(arm->pc->value, 0, 32, address);
1149
1150         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1151
1152         /* if we're at the reset vector, we have to simulate the branch */
1153         if (current_pc == 0x0) {
1154                 arm_simulate_step(target, NULL);
1155                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1156         }
1157
1158         /* the front-end may request us not to handle breakpoints */
1159         if (handle_breakpoints) {
1160                 struct breakpoint *breakpoint;
1161                 breakpoint = breakpoint_find(target,
1162                                 buf_get_u32(arm->pc->value, 0, 32));
1163                 if (breakpoint != NULL) {
1164                         uint32_t next_pc;
1165                         enum trace_mode saved_trace_mode;
1166
1167                         /* there's a breakpoint at the current PC, we have to step over it */
1168                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1169                         xscale_unset_breakpoint(target, breakpoint);
1170
1171                         /* calculate PC of next instruction */
1172                         retval = arm_simulate_step(target, &next_pc);
1173                         if (retval != ERROR_OK) {
1174                                 uint32_t current_opcode;
1175                                 target_read_u32(target, current_pc, &current_opcode);
1176                                 LOG_ERROR(
1177                                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1178                                         current_opcode);
1179                         }
1180
1181                         LOG_DEBUG("enable single-step");
1182                         xscale_enable_single_step(target, next_pc);
1183
1184                         /* restore banked registers */
1185                         retval = xscale_restore_banked(target);
1186                         if (retval != ERROR_OK)
1187                                 return retval;
1188
1189                         /* send resume request */
1190                         xscale_send_u32(target, 0x30);
1191
1192                         /* send CPSR */
1193                         xscale_send_u32(target,
1194                                 buf_get_u32(arm->cpsr->value, 0, 32));
1195                         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1196                                 buf_get_u32(arm->cpsr->value, 0, 32));
1197
1198                         for (i = 7; i >= 0; i--) {
1199                                 /* send register */
1200                                 xscale_send_u32(target,
1201                                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1202                                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1203                                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1204                         }
1205
1206                         /* send PC */
1207                         xscale_send_u32(target,
1208                                 buf_get_u32(arm->pc->value, 0, 32));
1209                         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1210                                 buf_get_u32(arm->pc->value, 0, 32));
1211
1212                         /* disable trace data collection in xscale_debug_entry() */
1213                         saved_trace_mode = xscale->trace.mode;
1214                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1215
1216                         /* wait for and process debug entry */
1217                         xscale_debug_entry(target);
1218
1219                         /* re-enable trace buffer, if enabled previously */
1220                         xscale->trace.mode = saved_trace_mode;
1221
1222                         LOG_DEBUG("disable single-step");
1223                         xscale_disable_single_step(target);
1224
1225                         LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1226                         xscale_set_breakpoint(target, breakpoint);
1227                 }
1228         }
1229
1230         /* enable any pending breakpoints and watchpoints */
1231         xscale_enable_breakpoints(target);
1232         xscale_enable_watchpoints(target);
1233
1234         /* restore banked registers */
1235         retval = xscale_restore_banked(target);
1236         if (retval != ERROR_OK)
1237                 return retval;
1238
1239         /* send resume request (command 0x30 or 0x31)
1240          * clean the trace buffer if it is to be enabled (0x62) */
1241         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1242                 if (xscale->trace.mode == XSCALE_TRACE_FILL) {
1243                         /* If trace enabled in fill mode and starting collection of new set
1244                              * of buffers, initialize buffer counter and free previous buffers */
1245                         if (xscale->trace.fill_counter == 0) {
1246                                 xscale->trace.fill_counter = xscale->trace.buffer_fill;
1247                                 xscale_free_trace_data(xscale);
1248                         }
1249                 } else  /* wrap mode; free previous buffer */
1250                         xscale_free_trace_data(xscale);
1251
1252                 xscale_send_u32(target, 0x62);
1253                 xscale_send_u32(target, 0x31);
1254         } else
1255                 xscale_send_u32(target, 0x30);
1256
1257         /* send CPSR */
1258         xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32));
1259         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1260                 buf_get_u32(arm->cpsr->value, 0, 32));
1261
1262         for (i = 7; i >= 0; i--) {
1263                 /* send register */
1264                 xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1265                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1266                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1267         }
1268
1269         /* send PC */
1270         xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32));
1271         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1272                 buf_get_u32(arm->pc->value, 0, 32));
1273
1274         target->debug_reason = DBG_REASON_NOTHALTED;
1275
1276         if (!debug_execution) {
1277                 /* registers are now invalid */
1278                 register_cache_invalidate(arm->core_cache);
1279                 target->state = TARGET_RUNNING;
1280                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1281         } else {
1282                 target->state = TARGET_DEBUG_RUNNING;
1283                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1284         }
1285
1286         LOG_DEBUG("target resumed");
1287
1288         return ERROR_OK;
1289 }
1290
1291 static int xscale_step_inner(struct target *target, int current,
1292         uint32_t address, int handle_breakpoints)
1293 {
1294         struct xscale_common *xscale = target_to_xscale(target);
1295         struct arm *arm = &xscale->arm;
1296         uint32_t next_pc;
1297         int retval;
1298         int i;
1299
1300         target->debug_reason = DBG_REASON_SINGLESTEP;
1301
1302         /* calculate PC of next instruction */
1303         retval = arm_simulate_step(target, &next_pc);
1304         if (retval != ERROR_OK) {
1305                 uint32_t current_opcode, current_pc;
1306                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1307
1308                 target_read_u32(target, current_pc, &current_opcode);
1309                 LOG_ERROR(
1310                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1311                         current_opcode);
1312                 return retval;
1313         }
1314
1315         LOG_DEBUG("enable single-step");
1316         retval = xscale_enable_single_step(target, next_pc);
1317         if (retval != ERROR_OK)
1318                 return retval;
1319
1320         /* restore banked registers */
1321         retval = xscale_restore_banked(target);
1322         if (retval != ERROR_OK)
1323                 return retval;
1324
1325         /* send resume request (command 0x30 or 0x31)
1326          * clean the trace buffer if it is to be enabled (0x62) */
1327         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1328                 retval = xscale_send_u32(target, 0x62);
1329                 if (retval != ERROR_OK)
1330                         return retval;
1331                 retval = xscale_send_u32(target, 0x31);
1332                 if (retval != ERROR_OK)
1333                         return retval;
1334         } else {
1335                 retval = xscale_send_u32(target, 0x30);
1336                 if (retval != ERROR_OK)
1337                         return retval;
1338         }
1339
1340         /* send CPSR */
1341         retval = xscale_send_u32(target,
1342                         buf_get_u32(arm->cpsr->value, 0, 32));
1343         if (retval != ERROR_OK)
1344                 return retval;
1345         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1346                 buf_get_u32(arm->cpsr->value, 0, 32));
1347
1348         for (i = 7; i >= 0; i--) {
1349                 /* send register */
1350                 retval = xscale_send_u32(target,
1351                                 buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1352                 if (retval != ERROR_OK)
1353                         return retval;
1354                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
1355                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1356         }
1357
1358         /* send PC */
1359         retval = xscale_send_u32(target,
1360                         buf_get_u32(arm->pc->value, 0, 32));
1361         if (retval != ERROR_OK)
1362                 return retval;
1363         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1364                 buf_get_u32(arm->pc->value, 0, 32));
1365
1366         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1367
1368         /* registers are now invalid */
1369         register_cache_invalidate(arm->core_cache);
1370
1371         /* wait for and process debug entry */
1372         retval = xscale_debug_entry(target);
1373         if (retval != ERROR_OK)
1374                 return retval;
1375
1376         LOG_DEBUG("disable single-step");
1377         retval = xscale_disable_single_step(target);
1378         if (retval != ERROR_OK)
1379                 return retval;
1380
1381         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1382
1383         return ERROR_OK;
1384 }
1385
1386 static int xscale_step(struct target *target, int current,
1387         uint32_t address, int handle_breakpoints)
1388 {
1389         struct arm *arm = target_to_arm(target);
1390         struct breakpoint *breakpoint = NULL;
1391
1392         uint32_t current_pc;
1393         int retval;
1394
1395         if (target->state != TARGET_HALTED) {
1396                 LOG_WARNING("target not halted");
1397                 return ERROR_TARGET_NOT_HALTED;
1398         }
1399
1400         /* current = 1: continue on current pc, otherwise continue at <address> */
1401         if (!current)
1402                 buf_set_u32(arm->pc->value, 0, 32, address);
1403
1404         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1405
1406         /* if we're at the reset vector, we have to simulate the step */
1407         if (current_pc == 0x0) {
1408                 retval = arm_simulate_step(target, NULL);
1409                 if (retval != ERROR_OK)
1410                         return retval;
1411                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1412                 LOG_DEBUG("current pc %" PRIx32, current_pc);
1413
1414                 target->debug_reason = DBG_REASON_SINGLESTEP;
1415                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1416
1417                 return ERROR_OK;
1418         }
1419
1420         /* the front-end may request us not to handle breakpoints */
1421         if (handle_breakpoints)
1422                 breakpoint = breakpoint_find(target,
1423                                 buf_get_u32(arm->pc->value, 0, 32));
1424         if (breakpoint != NULL) {
1425                 retval = xscale_unset_breakpoint(target, breakpoint);
1426                 if (retval != ERROR_OK)
1427                         return retval;
1428         }
1429
1430         retval = xscale_step_inner(target, current, address, handle_breakpoints);
1431         if (retval != ERROR_OK)
1432                 return retval;
1433
1434         if (breakpoint)
1435                 xscale_set_breakpoint(target, breakpoint);
1436
1437         LOG_DEBUG("target stepped");
1438
1439         return ERROR_OK;
1440
1441 }
1442
1443 static int xscale_assert_reset(struct target *target)
1444 {
1445         struct xscale_common *xscale = target_to_xscale(target);
1446
1447         LOG_DEBUG("target->state: %s",
1448                 target_state_name(target));
1449
1450         /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1451          * end up in T-L-R, which would reset JTAG
1452          */
1453         xscale_jtag_set_instr(target->tap,
1454                 XSCALE_SELDCSR << xscale->xscale_variant,
1455                 TAP_IDLE);
1456
1457         /* set Hold reset, Halt mode and Trap Reset */
1458         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1459         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1460         xscale_write_dcsr(target, 1, 0);
1461
1462         /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1463         xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1464         jtag_execute_queue();
1465
1466         /* assert reset */
1467         jtag_add_reset(0, 1);
1468
1469         /* sleep 1ms, to be sure we fulfill any requirements */
1470         jtag_add_sleep(1000);
1471         jtag_execute_queue();
1472
1473         target->state = TARGET_RESET;
1474
1475         if (target->reset_halt) {
1476                 int retval = target_halt(target);
1477                 if (retval != ERROR_OK)
1478                         return retval;
1479         }
1480
1481         return ERROR_OK;
1482 }
1483
1484 static int xscale_deassert_reset(struct target *target)
1485 {
1486         struct xscale_common *xscale = target_to_xscale(target);
1487         struct breakpoint *breakpoint = target->breakpoints;
1488
1489         LOG_DEBUG("-");
1490
1491         xscale->ibcr_available = 2;
1492         xscale->ibcr0_used = 0;
1493         xscale->ibcr1_used = 0;
1494
1495         xscale->dbr_available = 2;
1496         xscale->dbr0_used = 0;
1497         xscale->dbr1_used = 0;
1498
1499         /* mark all hardware breakpoints as unset */
1500         while (breakpoint) {
1501                 if (breakpoint->type == BKPT_HARD)
1502                         breakpoint->set = 0;
1503                 breakpoint = breakpoint->next;
1504         }
1505
1506         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1507         xscale_free_trace_data(xscale);
1508
1509         register_cache_invalidate(xscale->arm.core_cache);
1510
1511         /* FIXME mark hardware watchpoints got unset too.  Also,
1512          * at least some of the XScale registers are invalid...
1513          */
1514
1515         /*
1516          * REVISIT:  *assumes* we had a SRST+TRST reset so the mini-icache
1517          * contents got invalidated.  Safer to force that, so writing new
1518          * contents can't ever fail..
1519          */
1520         {
1521                 uint32_t address;
1522                 unsigned buf_cnt;
1523                 const uint8_t *buffer = xscale_debug_handler;
1524                 int retval;
1525
1526                 /* release SRST */
1527                 jtag_add_reset(0, 0);
1528
1529                 /* wait 300ms; 150 and 100ms were not enough */
1530                 jtag_add_sleep(300*1000);
1531
1532                 jtag_add_runtest(2030, TAP_IDLE);
1533                 jtag_execute_queue();
1534
1535                 /* set Hold reset, Halt mode and Trap Reset */
1536                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1537                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1538                 xscale_write_dcsr(target, 1, 0);
1539
1540                 /* Load the debug handler into the mini-icache.  Since
1541                  * it's using halt mode (not monitor mode), it runs in
1542                  * "Special Debug State" for access to registers, memory,
1543                  * coprocessors, trace data, etc.
1544                  */
1545                 address = xscale->handler_address;
1546                 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1547                         binary_size > 0;
1548                         binary_size -= buf_cnt, buffer += buf_cnt) {
1549                         uint32_t cache_line[8];
1550                         unsigned i;
1551
1552                         buf_cnt = binary_size;
1553                         if (buf_cnt > 32)
1554                                 buf_cnt = 32;
1555
1556                         for (i = 0; i < buf_cnt; i += 4) {
1557                                 /* convert LE buffer to host-endian uint32_t */
1558                                 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1559                         }
1560
1561                         for (; i < 32; i += 4)
1562                                 cache_line[i / 4] = 0xe1a08008;
1563
1564                         /* only load addresses other than the reset vectors */
1565                         if ((address % 0x400) != 0x0) {
1566                                 retval = xscale_load_ic(target, address,
1567                                                 cache_line);
1568                                 if (retval != ERROR_OK)
1569                                         return retval;
1570                         }
1571
1572                         address += buf_cnt;
1573                 }
1574                 ;
1575
1576                 retval = xscale_load_ic(target, 0x0,
1577                                 xscale->low_vectors);
1578                 if (retval != ERROR_OK)
1579                         return retval;
1580                 retval = xscale_load_ic(target, 0xffff0000,
1581                                 xscale->high_vectors);
1582                 if (retval != ERROR_OK)
1583                         return retval;
1584
1585                 jtag_add_runtest(30, TAP_IDLE);
1586
1587                 jtag_add_sleep(100000);
1588
1589                 /* set Hold reset, Halt mode and Trap Reset */
1590                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1591                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1592                 xscale_write_dcsr(target, 1, 0);
1593
1594                 /* clear Hold reset to let the target run (should enter debug handler) */
1595                 xscale_write_dcsr(target, 0, 1);
1596                 target->state = TARGET_RUNNING;
1597
1598                 if (!target->reset_halt) {
1599                         jtag_add_sleep(10000);
1600
1601                         /* we should have entered debug now */
1602                         xscale_debug_entry(target);
1603                         target->state = TARGET_HALTED;
1604
1605                         /* resume the target */
1606                         xscale_resume(target, 1, 0x0, 1, 0);
1607                 }
1608         }
1609
1610         return ERROR_OK;
1611 }
1612
1613 static int xscale_read_core_reg(struct target *target, struct reg *r,
1614         int num, enum arm_mode mode)
1615 {
1616         /** \todo add debug handler support for core register reads */
1617         LOG_ERROR("not implemented");
1618         return ERROR_OK;
1619 }
1620
1621 static int xscale_write_core_reg(struct target *target, struct reg *r,
1622         int num, enum arm_mode mode, uint32_t value)
1623 {
1624         /** \todo add debug handler support for core register writes */
1625         LOG_ERROR("not implemented");
1626         return ERROR_OK;
1627 }
1628
1629 static int xscale_full_context(struct target *target)
1630 {
1631         struct arm *arm = target_to_arm(target);
1632
1633         uint32_t *buffer;
1634
1635         int i, j;
1636
1637         LOG_DEBUG("-");
1638
1639         if (target->state != TARGET_HALTED) {
1640                 LOG_WARNING("target not halted");
1641                 return ERROR_TARGET_NOT_HALTED;
1642         }
1643
1644         buffer = malloc(4 * 8);
1645
1646         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1647          * we can't enter User mode on an XScale (unpredictable),
1648          * but User shares registers with SYS
1649          */
1650         for (i = 1; i < 7; i++) {
1651                 enum arm_mode mode = armv4_5_number_to_mode(i);
1652                 bool valid = true;
1653                 struct reg *r;
1654
1655                 if (mode == ARM_MODE_USR)
1656                         continue;
1657
1658                 /* check if there are invalid registers in the current mode
1659                  */
1660                 for (j = 0; valid && j <= 16; j++) {
1661                         if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
1662                                 mode, j).valid)
1663                                 valid = false;
1664                 }
1665                 if (valid)
1666                         continue;
1667
1668                 /* request banked registers */
1669                 xscale_send_u32(target, 0x0);
1670
1671                 /* send CPSR for desired bank mode */
1672                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1673
1674                 /* get banked registers:  r8 to r14; and SPSR
1675                  * except in USR/SYS mode
1676                  */
1677                 if (mode != ARM_MODE_SYS) {
1678                         /* SPSR */
1679                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1680                                         mode, 16);
1681
1682                         xscale_receive(target, buffer, 8);
1683
1684                         buf_set_u32(r->value, 0, 32, buffer[7]);
1685                         r->dirty = false;
1686                         r->valid = true;
1687                 } else
1688                         xscale_receive(target, buffer, 7);
1689
1690                 /* move data from buffer to register cache */
1691                 for (j = 8; j <= 14; j++) {
1692                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1693                                         mode, j);
1694
1695                         buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1696                         r->dirty = false;
1697                         r->valid = true;
1698                 }
1699         }
1700
1701         free(buffer);
1702
1703         return ERROR_OK;
1704 }
1705
1706 static int xscale_restore_banked(struct target *target)
1707 {
1708         struct arm *arm = target_to_arm(target);
1709
1710         int i, j;
1711
1712         if (target->state != TARGET_HALTED) {
1713                 LOG_WARNING("target not halted");
1714                 return ERROR_TARGET_NOT_HALTED;
1715         }
1716
1717         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1718          * and check if any banked registers need to be written.  Ignore
1719          * USR mode (number 0) in favor of SYS; we can't enter User mode on
1720          * an XScale (unpredictable), but they share all registers.
1721          */
1722         for (i = 1; i < 7; i++) {
1723                 enum arm_mode mode = armv4_5_number_to_mode(i);
1724                 struct reg *r;
1725
1726                 if (mode == ARM_MODE_USR)
1727                         continue;
1728
1729                 /* check if there are dirty registers in this mode */
1730                 for (j = 8; j <= 14; j++) {
1731                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1732                                 mode, j).dirty)
1733                                 goto dirty;
1734                 }
1735
1736                 /* if not USR/SYS, check if the SPSR needs to be written */
1737                 if (mode != ARM_MODE_SYS) {
1738                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1739                                 mode, 16).dirty)
1740                                 goto dirty;
1741                 }
1742
1743                 /* there's nothing to flush for this mode */
1744                 continue;
1745
1746 dirty:
1747                 /* command 0x1:  "send banked registers" */
1748                 xscale_send_u32(target, 0x1);
1749
1750                 /* send CPSR for desired mode */
1751                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1752
1753                 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1754                  * but this protocol doesn't understand that nuance.
1755                  */
1756                 for (j = 8; j <= 14; j++) {
1757                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1758                                         mode, j);
1759                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1760                         r->dirty = false;
1761                 }
1762
1763                 /* send spsr if not in USR/SYS mode */
1764                 if (mode != ARM_MODE_SYS) {
1765                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1766                                         mode, 16);
1767                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1768                         r->dirty = false;
1769                 }
1770         }
1771
1772         return ERROR_OK;
1773 }
1774
1775 static int xscale_read_memory(struct target *target, uint32_t address,
1776         uint32_t size, uint32_t count, uint8_t *buffer)
1777 {
1778         struct xscale_common *xscale = target_to_xscale(target);
1779         uint32_t *buf32;
1780         uint32_t i;
1781         int retval;
1782
1783         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1784                 address,
1785                 size,
1786                 count);
1787
1788         if (target->state != TARGET_HALTED) {
1789                 LOG_WARNING("target not halted");
1790                 return ERROR_TARGET_NOT_HALTED;
1791         }
1792
1793         /* sanitize arguments */
1794         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1795                 return ERROR_COMMAND_SYNTAX_ERROR;
1796
1797         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1798                 return ERROR_TARGET_UNALIGNED_ACCESS;
1799
1800         /* send memory read request (command 0x1n, n: access size) */
1801         retval = xscale_send_u32(target, 0x10 | size);
1802         if (retval != ERROR_OK)
1803                 return retval;
1804
1805         /* send base address for read request */
1806         retval = xscale_send_u32(target, address);
1807         if (retval != ERROR_OK)
1808                 return retval;
1809
1810         /* send number of requested data words */
1811         retval = xscale_send_u32(target, count);
1812         if (retval != ERROR_OK)
1813                 return retval;
1814
1815         /* receive data from target (count times 32-bit words in host endianness) */
1816         buf32 = malloc(4 * count);
1817         retval = xscale_receive(target, buf32, count);
1818         if (retval != ERROR_OK)
1819                 return retval;
1820
1821         /* extract data from host-endian buffer into byte stream */
1822         for (i = 0; i < count; i++) {
1823                 switch (size) {
1824                         case 4:
1825                                 target_buffer_set_u32(target, buffer, buf32[i]);
1826                                 buffer += 4;
1827                                 break;
1828                         case 2:
1829                                 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1830                                 buffer += 2;
1831                                 break;
1832                         case 1:
1833                                 *buffer++ = buf32[i] & 0xff;
1834                                 break;
1835                         default:
1836                                 LOG_ERROR("invalid read size");
1837                                 return ERROR_COMMAND_SYNTAX_ERROR;
1838                 }
1839         }
1840
1841         free(buf32);
1842
1843         /* examine DCSR, to see if Sticky Abort (SA) got set */
1844         retval = xscale_read_dcsr(target);
1845         if (retval != ERROR_OK)
1846                 return retval;
1847         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1848                 /* clear SA bit */
1849                 retval = xscale_send_u32(target, 0x60);
1850                 if (retval != ERROR_OK)
1851                         return retval;
1852
1853                 return ERROR_TARGET_DATA_ABORT;
1854         }
1855
1856         return ERROR_OK;
1857 }
1858
1859 static int xscale_read_phys_memory(struct target *target, uint32_t address,
1860         uint32_t size, uint32_t count, uint8_t *buffer)
1861 {
1862         struct xscale_common *xscale = target_to_xscale(target);
1863
1864         /* with MMU inactive, there are only physical addresses */
1865         if (!xscale->armv4_5_mmu.mmu_enabled)
1866                 return xscale_read_memory(target, address, size, count, buffer);
1867
1868         /** \todo: provide a non-stub implementation of this routine. */
1869         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1870                 target_name(target), __func__);
1871         return ERROR_FAIL;
1872 }
1873
1874 static int xscale_write_memory(struct target *target, uint32_t address,
1875         uint32_t size, uint32_t count, const uint8_t *buffer)
1876 {
1877         struct xscale_common *xscale = target_to_xscale(target);
1878         int retval;
1879
1880         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1881                 address,
1882                 size,
1883                 count);
1884
1885         if (target->state != TARGET_HALTED) {
1886                 LOG_WARNING("target not halted");
1887                 return ERROR_TARGET_NOT_HALTED;
1888         }
1889
1890         /* sanitize arguments */
1891         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1892                 return ERROR_COMMAND_SYNTAX_ERROR;
1893
1894         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1895                 return ERROR_TARGET_UNALIGNED_ACCESS;
1896
1897         /* send memory write request (command 0x2n, n: access size) */
1898         retval = xscale_send_u32(target, 0x20 | size);
1899         if (retval != ERROR_OK)
1900                 return retval;
1901
1902         /* send base address for read request */
1903         retval = xscale_send_u32(target, address);
1904         if (retval != ERROR_OK)
1905                 return retval;
1906
1907         /* send number of requested data words to be written*/
1908         retval = xscale_send_u32(target, count);
1909         if (retval != ERROR_OK)
1910                 return retval;
1911
1912         /* extract data from host-endian buffer into byte stream */
1913 #if 0
1914         for (i = 0; i < count; i++) {
1915                 switch (size) {
1916                         case 4:
1917                                 value = target_buffer_get_u32(target, buffer);
1918                                 xscale_send_u32(target, value);
1919                                 buffer += 4;
1920                                 break;
1921                         case 2:
1922                                 value = target_buffer_get_u16(target, buffer);
1923                                 xscale_send_u32(target, value);
1924                                 buffer += 2;
1925                                 break;
1926                         case 1:
1927                                 value = *buffer;
1928                                 xscale_send_u32(target, value);
1929                                 buffer += 1;
1930                                 break;
1931                         default:
1932                                 LOG_ERROR("should never get here");
1933                                 exit(-1);
1934                 }
1935         }
1936 #endif
1937         retval = xscale_send(target, buffer, count, size);
1938         if (retval != ERROR_OK)
1939                 return retval;
1940
1941         /* examine DCSR, to see if Sticky Abort (SA) got set */
1942         retval = xscale_read_dcsr(target);
1943         if (retval != ERROR_OK)
1944                 return retval;
1945         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1946                 /* clear SA bit */
1947                 retval = xscale_send_u32(target, 0x60);
1948                 if (retval != ERROR_OK)
1949                         return retval;
1950
1951                 LOG_ERROR("data abort writing memory");
1952                 return ERROR_TARGET_DATA_ABORT;
1953         }
1954
1955         return ERROR_OK;
1956 }
1957
1958 static int xscale_write_phys_memory(struct target *target, uint32_t address,
1959         uint32_t size, uint32_t count, const uint8_t *buffer)
1960 {
1961         struct xscale_common *xscale = target_to_xscale(target);
1962
1963         /* with MMU inactive, there are only physical addresses */
1964         if (!xscale->armv4_5_mmu.mmu_enabled)
1965                 return xscale_write_memory(target, address, size, count, buffer);
1966
1967         /** \todo: provide a non-stub implementation of this routine. */
1968         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1969                 target_name(target), __func__);
1970         return ERROR_FAIL;
1971 }
1972
1973 static int xscale_get_ttb(struct target *target, uint32_t *result)
1974 {
1975         struct xscale_common *xscale = target_to_xscale(target);
1976         uint32_t ttb;
1977         int retval;
1978
1979         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
1980         if (retval != ERROR_OK)
1981                 return retval;
1982         ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
1983
1984         *result = ttb;
1985
1986         return ERROR_OK;
1987 }
1988
1989 static int xscale_disable_mmu_caches(struct target *target, int mmu,
1990         int d_u_cache, int i_cache)
1991 {
1992         struct xscale_common *xscale = target_to_xscale(target);
1993         uint32_t cp15_control;
1994         int retval;
1995
1996         /* read cp15 control register */
1997         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1998         if (retval != ERROR_OK)
1999                 return retval;
2000         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2001
2002         if (mmu)
2003                 cp15_control &= ~0x1U;
2004
2005         if (d_u_cache) {
2006                 /* clean DCache */
2007                 retval = xscale_send_u32(target, 0x50);
2008                 if (retval != ERROR_OK)
2009                         return retval;
2010                 retval = xscale_send_u32(target, xscale->cache_clean_address);
2011                 if (retval != ERROR_OK)
2012                         return retval;
2013
2014                 /* invalidate DCache */
2015                 retval = xscale_send_u32(target, 0x51);
2016                 if (retval != ERROR_OK)
2017                         return retval;
2018
2019                 cp15_control &= ~0x4U;
2020         }
2021
2022         if (i_cache) {
2023                 /* invalidate ICache */
2024                 retval = xscale_send_u32(target, 0x52);
2025                 if (retval != ERROR_OK)
2026                         return retval;
2027                 cp15_control &= ~0x1000U;
2028         }
2029
2030         /* write new cp15 control register */
2031         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2032         if (retval != ERROR_OK)
2033                 return retval;
2034
2035         /* execute cpwait to ensure outstanding operations complete */
2036         retval = xscale_send_u32(target, 0x53);
2037         return retval;
2038 }
2039
2040 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2041         int d_u_cache, int i_cache)
2042 {
2043         struct xscale_common *xscale = target_to_xscale(target);
2044         uint32_t cp15_control;
2045         int retval;
2046
2047         /* read cp15 control register */
2048         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2049         if (retval != ERROR_OK)
2050                 return retval;
2051         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2052
2053         if (mmu)
2054                 cp15_control |= 0x1U;
2055
2056         if (d_u_cache)
2057                 cp15_control |= 0x4U;
2058
2059         if (i_cache)
2060                 cp15_control |= 0x1000U;
2061
2062         /* write new cp15 control register */
2063         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2064         if (retval != ERROR_OK)
2065                 return retval;
2066
2067         /* execute cpwait to ensure outstanding operations complete */
2068         retval = xscale_send_u32(target, 0x53);
2069         return retval;
2070 }
2071
2072 static int xscale_set_breakpoint(struct target *target,
2073         struct breakpoint *breakpoint)
2074 {
2075         int retval;
2076         struct xscale_common *xscale = target_to_xscale(target);
2077
2078         if (target->state != TARGET_HALTED) {
2079                 LOG_WARNING("target not halted");
2080                 return ERROR_TARGET_NOT_HALTED;
2081         }
2082
2083         if (breakpoint->set) {
2084                 LOG_WARNING("breakpoint already set");
2085                 return ERROR_OK;
2086         }
2087
2088         if (breakpoint->type == BKPT_HARD) {
2089                 uint32_t value = breakpoint->address | 1;
2090                 if (!xscale->ibcr0_used) {
2091                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2092                         xscale->ibcr0_used = 1;
2093                         breakpoint->set = 1;    /* breakpoint set on first breakpoint register */
2094                 } else if (!xscale->ibcr1_used) {
2095                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2096                         xscale->ibcr1_used = 1;
2097                         breakpoint->set = 2;    /* breakpoint set on second breakpoint register */
2098                 } else {/* bug: availability previously verified in xscale_add_breakpoint() */
2099                         LOG_ERROR("BUG: no hardware comparator available");
2100                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2101                 }
2102         } else if (breakpoint->type == BKPT_SOFT) {
2103                 if (breakpoint->length == 4) {
2104                         /* keep the original instruction in target endianness */
2105                         retval = target_read_memory(target, breakpoint->address, 4, 1,
2106                                         breakpoint->orig_instr);
2107                         if (retval != ERROR_OK)
2108                                 return retval;
2109                         /* write the bkpt instruction in target endianness
2110                          *(arm7_9->arm_bkpt is host endian) */
2111                         retval = target_write_u32(target, breakpoint->address,
2112                                         xscale->arm_bkpt);
2113                         if (retval != ERROR_OK)
2114                                 return retval;
2115                 } else {
2116                         /* keep the original instruction in target endianness */
2117                         retval = target_read_memory(target, breakpoint->address, 2, 1,
2118                                         breakpoint->orig_instr);
2119                         if (retval != ERROR_OK)
2120                                 return retval;
2121                         /* write the bkpt instruction in target endianness
2122                          *(arm7_9->arm_bkpt is host endian) */
2123                         retval = target_write_u16(target, breakpoint->address,
2124                                         xscale->thumb_bkpt);
2125                         if (retval != ERROR_OK)
2126                                 return retval;
2127                 }
2128                 breakpoint->set = 1;
2129
2130                 xscale_send_u32(target, 0x50);  /* clean dcache */
2131                 xscale_send_u32(target, xscale->cache_clean_address);
2132                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2133                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2134         }
2135
2136         return ERROR_OK;
2137 }
2138
2139 static int xscale_add_breakpoint(struct target *target,
2140         struct breakpoint *breakpoint)
2141 {
2142         struct xscale_common *xscale = target_to_xscale(target);
2143
2144         if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) {
2145                 LOG_ERROR("no breakpoint unit available for hardware breakpoint");
2146                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2147         }
2148
2149         if ((breakpoint->length != 2) && (breakpoint->length != 4)) {
2150                 LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2151                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2152         }
2153
2154         if (breakpoint->type == BKPT_HARD)
2155                 xscale->ibcr_available--;
2156
2157         return xscale_set_breakpoint(target, breakpoint);
2158 }
2159
2160 static int xscale_unset_breakpoint(struct target *target,
2161         struct breakpoint *breakpoint)
2162 {
2163         int retval;
2164         struct xscale_common *xscale = target_to_xscale(target);
2165
2166         if (target->state != TARGET_HALTED) {
2167                 LOG_WARNING("target not halted");
2168                 return ERROR_TARGET_NOT_HALTED;
2169         }
2170
2171         if (!breakpoint->set) {
2172                 LOG_WARNING("breakpoint not set");
2173                 return ERROR_OK;
2174         }
2175
2176         if (breakpoint->type == BKPT_HARD) {
2177                 if (breakpoint->set == 1) {
2178                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2179                         xscale->ibcr0_used = 0;
2180                 } else if (breakpoint->set == 2) {
2181                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2182                         xscale->ibcr1_used = 0;
2183                 }
2184                 breakpoint->set = 0;
2185         } else {
2186                 /* restore original instruction (kept in target endianness) */
2187                 if (breakpoint->length == 4) {
2188                         retval = target_write_memory(target, breakpoint->address, 4, 1,
2189                                         breakpoint->orig_instr);
2190                         if (retval != ERROR_OK)
2191                                 return retval;
2192                 } else {
2193                         retval = target_write_memory(target, breakpoint->address, 2, 1,
2194                                         breakpoint->orig_instr);
2195                         if (retval != ERROR_OK)
2196                                 return retval;
2197                 }
2198                 breakpoint->set = 0;
2199
2200                 xscale_send_u32(target, 0x50);  /* clean dcache */
2201                 xscale_send_u32(target, xscale->cache_clean_address);
2202                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2203                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2204         }
2205
2206         return ERROR_OK;
2207 }
2208
2209 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2210 {
2211         struct xscale_common *xscale = target_to_xscale(target);
2212
2213         if (target->state != TARGET_HALTED) {
2214                 LOG_ERROR("target not halted");
2215                 return ERROR_TARGET_NOT_HALTED;
2216         }
2217
2218         if (breakpoint->set)
2219                 xscale_unset_breakpoint(target, breakpoint);
2220
2221         if (breakpoint->type == BKPT_HARD)
2222                 xscale->ibcr_available++;
2223
2224         return ERROR_OK;
2225 }
2226
2227 static int xscale_set_watchpoint(struct target *target,
2228         struct watchpoint *watchpoint)
2229 {
2230         struct xscale_common *xscale = target_to_xscale(target);
2231         uint32_t enable = 0;
2232         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2233         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2234
2235         if (target->state != TARGET_HALTED) {
2236                 LOG_ERROR("target not halted");
2237                 return ERROR_TARGET_NOT_HALTED;
2238         }
2239
2240         switch (watchpoint->rw) {
2241                 case WPT_READ:
2242                         enable = 0x3;
2243                         break;
2244                 case WPT_ACCESS:
2245                         enable = 0x2;
2246                         break;
2247                 case WPT_WRITE:
2248                         enable = 0x1;
2249                         break;
2250                 default:
2251                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2252         }
2253
2254         /* For watchpoint across more than one word, both DBR registers must
2255            be enlisted, with the second used as a mask. */
2256         if (watchpoint->length > 4) {
2257                 if (xscale->dbr0_used || xscale->dbr1_used) {
2258                         LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2259                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2260                 }
2261
2262                 /* Write mask value to DBR1, based on the length argument.
2263                  * Address bits ignored by the comparator are those set in mask. */
2264                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2265                         watchpoint->length - 1);
2266                 xscale->dbr1_used = 1;
2267                 enable |= 0x100;                /* DBCON[M] */
2268         }
2269
2270         if (!xscale->dbr0_used) {
2271                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2272                 dbcon_value |= enable;
2273                 xscale_set_reg_u32(dbcon, dbcon_value);
2274                 watchpoint->set = 1;
2275                 xscale->dbr0_used = 1;
2276         } else if (!xscale->dbr1_used) {
2277                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2278                 dbcon_value |= enable << 2;
2279                 xscale_set_reg_u32(dbcon, dbcon_value);
2280                 watchpoint->set = 2;
2281                 xscale->dbr1_used = 1;
2282         } else {
2283                 LOG_ERROR("BUG: no hardware comparator available");
2284                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2285         }
2286
2287         return ERROR_OK;
2288 }
2289
2290 static int xscale_add_watchpoint(struct target *target,
2291         struct watchpoint *watchpoint)
2292 {
2293         struct xscale_common *xscale = target_to_xscale(target);
2294
2295         if (xscale->dbr_available < 1) {
2296                 LOG_ERROR("no more watchpoint registers available");
2297                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2298         }
2299
2300         if (watchpoint->value)
2301                 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2302
2303         /* check that length is a power of two */
2304         for (uint32_t len = watchpoint->length; len != 1; len /= 2) {
2305                 if (len % 2) {
2306                         LOG_ERROR("xscale requires that watchpoint length is a power of two");
2307                         return ERROR_COMMAND_ARGUMENT_INVALID;
2308                 }
2309         }
2310
2311         if (watchpoint->length == 4) {  /* single word watchpoint */
2312                 xscale->dbr_available--;/* one DBR reg used */
2313                 return ERROR_OK;
2314         }
2315
2316         /* watchpoints across multiple words require both DBR registers */
2317         if (xscale->dbr_available < 2) {
2318                 LOG_ERROR("insufficient watchpoint registers available");
2319                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2320         }
2321
2322         if (watchpoint->length > watchpoint->address) {
2323                 LOG_ERROR("xscale does not support watchpoints with length "
2324                         "greater than address");
2325                 return ERROR_COMMAND_ARGUMENT_INVALID;
2326         }
2327
2328         xscale->dbr_available = 0;
2329         return ERROR_OK;
2330 }
2331
2332 static int xscale_unset_watchpoint(struct target *target,
2333         struct watchpoint *watchpoint)
2334 {
2335         struct xscale_common *xscale = target_to_xscale(target);
2336         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2337         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2338
2339         if (target->state != TARGET_HALTED) {
2340                 LOG_WARNING("target not halted");
2341                 return ERROR_TARGET_NOT_HALTED;
2342         }
2343
2344         if (!watchpoint->set) {
2345                 LOG_WARNING("breakpoint not set");
2346                 return ERROR_OK;
2347         }
2348
2349         if (watchpoint->set == 1) {
2350                 if (watchpoint->length > 4) {
2351                         dbcon_value &= ~0x103;  /* clear DBCON[M] as well */
2352                         xscale->dbr1_used = 0;  /* DBR1 was used for mask */
2353                 } else
2354                         dbcon_value &= ~0x3;
2355
2356                 xscale_set_reg_u32(dbcon, dbcon_value);
2357                 xscale->dbr0_used = 0;
2358         } else if (watchpoint->set == 2) {
2359                 dbcon_value &= ~0xc;
2360                 xscale_set_reg_u32(dbcon, dbcon_value);
2361                 xscale->dbr1_used = 0;
2362         }
2363         watchpoint->set = 0;
2364
2365         return ERROR_OK;
2366 }
2367
2368 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2369 {
2370         struct xscale_common *xscale = target_to_xscale(target);
2371
2372         if (target->state != TARGET_HALTED) {
2373                 LOG_ERROR("target not halted");
2374                 return ERROR_TARGET_NOT_HALTED;
2375         }
2376
2377         if (watchpoint->set)
2378                 xscale_unset_watchpoint(target, watchpoint);
2379
2380         if (watchpoint->length > 4)
2381                 xscale->dbr_available++;/* both DBR regs now available */
2382
2383         xscale->dbr_available++;
2384
2385         return ERROR_OK;
2386 }
2387
2388 static int xscale_get_reg(struct reg *reg)
2389 {
2390         struct xscale_reg *arch_info = reg->arch_info;
2391         struct target *target = arch_info->target;
2392         struct xscale_common *xscale = target_to_xscale(target);
2393
2394         /* DCSR, TX and RX are accessible via JTAG */
2395         if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2396                 return xscale_read_dcsr(arch_info->target);
2397         else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2398                 /* 1 = consume register content */
2399                 return xscale_read_tx(arch_info->target, 1);
2400         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2401                 /* can't read from RX register (host -> debug handler) */
2402                 return ERROR_OK;
2403         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2404                 /* can't (explicitly) read from TXRXCTRL register */
2405                 return ERROR_OK;
2406         } else {/* Other DBG registers have to be transfered by the debug handler
2407                  * send CP read request (command 0x40) */
2408                 xscale_send_u32(target, 0x40);
2409
2410                 /* send CP register number */
2411                 xscale_send_u32(target, arch_info->dbg_handler_number);
2412
2413                 /* read register value */
2414                 xscale_read_tx(target, 1);
2415                 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2416
2417                 reg->dirty = 0;
2418                 reg->valid = 1;
2419         }
2420
2421         return ERROR_OK;
2422 }
2423
2424 static int xscale_set_reg(struct reg *reg, uint8_t *buf)
2425 {
2426         struct xscale_reg *arch_info = reg->arch_info;
2427         struct target *target = arch_info->target;
2428         struct xscale_common *xscale = target_to_xscale(target);
2429         uint32_t value = buf_get_u32(buf, 0, 32);
2430
2431         /* DCSR, TX and RX are accessible via JTAG */
2432         if (strcmp(reg->name, "XSCALE_DCSR") == 0) {
2433                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2434                 return xscale_write_dcsr(arch_info->target, -1, -1);
2435         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2436                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2437                 return xscale_write_rx(arch_info->target);
2438         } else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2439                 /* can't write to TX register (debug-handler -> host) */
2440                 return ERROR_OK;
2441         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2442                 /* can't (explicitly) write to TXRXCTRL register */
2443                 return ERROR_OK;
2444         } else {/* Other DBG registers have to be transfered by the debug handler
2445                  * send CP write request (command 0x41) */
2446                 xscale_send_u32(target, 0x41);
2447
2448                 /* send CP register number */
2449                 xscale_send_u32(target, arch_info->dbg_handler_number);
2450
2451                 /* send CP register value */
2452                 xscale_send_u32(target, value);
2453                 buf_set_u32(reg->value, 0, 32, value);
2454         }
2455
2456         return ERROR_OK;
2457 }
2458
2459 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2460 {
2461         struct xscale_common *xscale = target_to_xscale(target);
2462         struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2463         struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2464
2465         /* send CP write request (command 0x41) */
2466         xscale_send_u32(target, 0x41);
2467
2468         /* send CP register number */
2469         xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2470
2471         /* send CP register value */
2472         xscale_send_u32(target, value);
2473         buf_set_u32(dcsr->value, 0, 32, value);
2474
2475         return ERROR_OK;
2476 }
2477
2478 static int xscale_read_trace(struct target *target)
2479 {
2480         struct xscale_common *xscale = target_to_xscale(target);
2481         struct arm *arm = &xscale->arm;
2482         struct xscale_trace_data **trace_data_p;
2483
2484         /* 258 words from debug handler
2485          * 256 trace buffer entries
2486          * 2 checkpoint addresses
2487          */
2488         uint32_t trace_buffer[258];
2489         int is_address[256];
2490         int i, j;
2491         unsigned int num_checkpoints = 0;
2492
2493         if (target->state != TARGET_HALTED) {
2494                 LOG_WARNING("target must be stopped to read trace data");
2495                 return ERROR_TARGET_NOT_HALTED;
2496         }
2497
2498         /* send read trace buffer command (command 0x61) */
2499         xscale_send_u32(target, 0x61);
2500
2501         /* receive trace buffer content */
2502         xscale_receive(target, trace_buffer, 258);
2503
2504         /* parse buffer backwards to identify address entries */
2505         for (i = 255; i >= 0; i--) {
2506                 /* also count number of checkpointed entries */
2507                 if ((trace_buffer[i] & 0xe0) == 0xc0)
2508                         num_checkpoints++;
2509
2510                 is_address[i] = 0;
2511                 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2512                         ((trace_buffer[i] & 0xf0) == 0xd0)) {
2513                         if (i > 0)
2514                                 is_address[--i] = 1;
2515                         if (i > 0)
2516                                 is_address[--i] = 1;
2517                         if (i > 0)
2518                                 is_address[--i] = 1;
2519                         if (i > 0)
2520                                 is_address[--i] = 1;
2521                 }
2522         }
2523
2524
2525         /* search first non-zero entry that is not part of an address */
2526         for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2527                 ;
2528
2529         if (j == 256) {
2530                 LOG_DEBUG("no trace data collected");
2531                 return ERROR_XSCALE_NO_TRACE_DATA;
2532         }
2533
2534         /* account for possible partial address at buffer start (wrap mode only) */
2535         if (is_address[0]) {    /* first entry is address; complete set of 4? */
2536                 i = 1;
2537                 while (i < 4)
2538                         if (!is_address[i++])
2539                                 break;
2540                 if (i < 4)
2541                         j += i;         /* partial address; can't use it */
2542         }
2543
2544         /* if first valid entry is indirect branch, can't use that either (no address) */
2545         if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2546                 j++;
2547
2548         /* walk linked list to terminating entry */
2549         for (trace_data_p = &xscale->trace.data; *trace_data_p;
2550                 trace_data_p = &(*trace_data_p)->next)
2551                 ;
2552
2553         *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2554         (*trace_data_p)->next = NULL;
2555         (*trace_data_p)->chkpt0 = trace_buffer[256];
2556         (*trace_data_p)->chkpt1 = trace_buffer[257];
2557         (*trace_data_p)->last_instruction = buf_get_u32(arm->pc->value, 0, 32);
2558         (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2559         (*trace_data_p)->depth = 256 - j;
2560         (*trace_data_p)->num_checkpoints = num_checkpoints;
2561
2562         for (i = j; i < 256; i++) {
2563                 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2564                 if (is_address[i])
2565                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2566                 else
2567                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2568         }
2569
2570         return ERROR_OK;
2571 }
2572
2573 static int xscale_read_instruction(struct target *target, uint32_t pc,
2574         struct arm_instruction *instruction)
2575 {
2576         struct xscale_common *const xscale = target_to_xscale(target);
2577         int i;
2578         int section = -1;
2579         size_t size_read;
2580         uint32_t opcode;
2581         int retval;
2582
2583         if (!xscale->trace.image)
2584                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2585
2586         /* search for the section the current instruction belongs to */
2587         for (i = 0; i < xscale->trace.image->num_sections; i++) {
2588                 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2589                         (xscale->trace.image->sections[i].base_address +
2590                         xscale->trace.image->sections[i].size > pc)) {
2591                         section = i;
2592                         break;
2593                 }
2594         }
2595
2596         if (section == -1) {
2597                 /* current instruction couldn't be found in the image */
2598                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2599         }
2600
2601         if (xscale->trace.core_state == ARM_STATE_ARM) {
2602                 uint8_t buf[4];
2603                 retval = image_read_section(xscale->trace.image, section,
2604                                 pc - xscale->trace.image->sections[section].base_address,
2605                                 4, buf, &size_read);
2606                 if (retval != ERROR_OK) {
2607                         LOG_ERROR("error while reading instruction");
2608                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2609                 }
2610                 opcode = target_buffer_get_u32(target, buf);
2611                 arm_evaluate_opcode(opcode, pc, instruction);
2612         } else if (xscale->trace.core_state == ARM_STATE_THUMB) {
2613                 uint8_t buf[2];
2614                 retval = image_read_section(xscale->trace.image, section,
2615                                 pc - xscale->trace.image->sections[section].base_address,
2616                                 2, buf, &size_read);
2617                 if (retval != ERROR_OK) {
2618                         LOG_ERROR("error while reading instruction");
2619                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2620                 }
2621                 opcode = target_buffer_get_u16(target, buf);
2622                 thumb_evaluate_opcode(opcode, pc, instruction);
2623         } else {
2624                 LOG_ERROR("BUG: unknown core state encountered");
2625                 exit(-1);
2626         }
2627
2628         return ERROR_OK;
2629 }
2630
2631 /* Extract address encoded into trace data.
2632  * Write result to address referenced by argument 'target', or 0 if incomplete.  */
2633 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2634         int i, uint32_t *target)
2635 {
2636         /* if there are less than four entries prior to the indirect branch message
2637          * we can't extract the address */
2638         if (i < 4)
2639                 *target = 0;
2640         else {
2641                 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2642                         (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2643         }
2644 }
2645
2646 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2647         struct arm_instruction *instruction,
2648         struct command_context *cmd_ctx)
2649 {
2650         int retval = xscale_read_instruction(target, pc, instruction);
2651         if (retval == ERROR_OK)
2652                 command_print(cmd_ctx, "%s", instruction->text);
2653         else
2654                 command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2655 }
2656
2657 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2658 {
2659         struct xscale_common *xscale = target_to_xscale(target);
2660         struct xscale_trace_data *trace_data = xscale->trace.data;
2661         int i, retval;
2662         uint32_t breakpoint_pc;
2663         struct arm_instruction instruction;
2664         uint32_t current_pc = 0;/* initialized when address determined */
2665
2666         if (!xscale->trace.image)
2667                 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2668
2669         /* loop for each trace buffer that was loaded from target */
2670         while (trace_data) {
2671                 int chkpt = 0;  /* incremented as checkpointed entries found */
2672                 int j;
2673
2674                 /* FIXME: set this to correct mode when trace buffer is first enabled */
2675                 xscale->trace.core_state = ARM_STATE_ARM;
2676
2677                 /* loop for each entry in this trace buffer */
2678                 for (i = 0; i < trace_data->depth; i++) {
2679                         int exception = 0;
2680                         uint32_t chkpt_reg = 0x0;
2681                         uint32_t branch_target = 0;
2682                         int count;
2683
2684                         /* trace entry type is upper nybble of 'message byte' */
2685                         int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2686
2687                         /* Target addresses of indirect branches are written into buffer
2688                          * before the message byte representing the branch. Skip past it */
2689                         if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2690                                 continue;
2691
2692                         switch (trace_msg_type) {
2693                                 case 0: /* Exceptions */
2694                                 case 1:
2695                                 case 2:
2696                                 case 3:
2697                                 case 4:
2698                                 case 5:
2699                                 case 6:
2700                                 case 7:
2701                                         exception = (trace_data->entries[i].data & 0x70) >> 4;
2702
2703                                         /* FIXME: vector table may be at ffff0000 */
2704                                         branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2705                                         break;
2706
2707                                 case 8: /* Direct Branch */
2708                                         break;
2709
2710                                 case 9: /* Indirect Branch */
2711                                         xscale_branch_address(trace_data, i, &branch_target);
2712                                         break;
2713
2714                                 case 13:        /* Checkpointed Indirect Branch */
2715                                         xscale_branch_address(trace_data, i, &branch_target);
2716                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2717                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2718                                                                                  *oldest */
2719                                         else
2720                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2721                                                                                  *newest */
2722
2723                                         chkpt++;
2724                                         break;
2725
2726                                 case 12:        /* Checkpointed Direct Branch */
2727                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2728                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2729                                                                                  *oldest */
2730                                         else
2731                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2732                                                                                  *newest */
2733
2734                                         /* if no current_pc, checkpoint will be starting point */
2735                                         if (current_pc == 0)
2736                                                 branch_target = chkpt_reg;
2737
2738                                         chkpt++;
2739                                         break;
2740
2741                                 case 15:/* Roll-over */
2742                                         break;
2743
2744                                 default:/* Reserved */
2745                                         LOG_WARNING("trace is suspect: invalid trace message byte");
2746                                         continue;
2747
2748                         }
2749
2750                         /* If we don't have the current_pc yet, but we did get the branch target
2751                          * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2752                          * then we can start displaying instructions at the next iteration, with
2753                          * branch_target as the starting point.
2754                          */
2755                         if (current_pc == 0) {
2756                                 current_pc = branch_target;     /* remains 0 unless branch_target *obtained */
2757                                 continue;
2758                         }
2759
2760                         /* We have current_pc.  Read and display the instructions from the image.
2761                          * First, display count instructions (lower nybble of message byte). */
2762                         count = trace_data->entries[i].data & 0x0f;
2763                         for (j = 0; j < count; j++) {
2764                                 xscale_display_instruction(target, current_pc, &instruction,
2765                                         cmd_ctx);
2766                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2767                         }
2768
2769                         /* An additional instruction is implicitly added to count for
2770                          * rollover and some exceptions: undef, swi, prefetch abort. */
2771                         if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
2772                                 xscale_display_instruction(target, current_pc, &instruction,
2773                                         cmd_ctx);
2774                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2775                         }
2776
2777                         if (trace_msg_type == 15)       /* rollover */
2778                                 continue;
2779
2780                         if (exception) {
2781                                 command_print(cmd_ctx, "--- exception %i ---", exception);
2782                                 continue;
2783                         }
2784
2785                         /* not exception or rollover; next instruction is a branch and is
2786                          * not included in the count */
2787                         xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2788
2789                         /* for direct branches, extract branch destination from instruction */
2790                         if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
2791                                 retval = xscale_read_instruction(target, current_pc, &instruction);
2792                                 if (retval == ERROR_OK)
2793                                         current_pc = instruction.info.b_bl_bx_blx.target_address;
2794                                 else
2795                                         current_pc = 0; /* branch destination unknown */
2796
2797                                 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2798                                 if (trace_msg_type == 12) {
2799                                         if (current_pc == 0)
2800                                                 current_pc = chkpt_reg;
2801                                         else if (current_pc != chkpt_reg)       /* sanity check */
2802                                                 LOG_WARNING("trace is suspect: checkpoint register "
2803                                                         "inconsistent with adddress from image");
2804                                 }
2805
2806                                 if (current_pc == 0)
2807                                         command_print(cmd_ctx, "address unknown");
2808
2809                                 continue;
2810                         }
2811
2812                         /* indirect branch; the branch destination was read from trace buffer */
2813                         if ((trace_msg_type == 9) || (trace_msg_type == 13)) {
2814                                 current_pc = branch_target;
2815
2816                                 /* sanity check (checkpoint reg is redundant) */
2817                                 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2818                                         LOG_WARNING("trace is suspect: checkpoint register "
2819                                                 "inconsistent with address from trace buffer");
2820                         }
2821
2822                 }       /* END: for (i = 0; i < trace_data->depth; i++) */
2823
2824                 breakpoint_pc = trace_data->last_instruction;   /* used below */
2825                 trace_data = trace_data->next;
2826
2827         }       /* END: while (trace_data) */
2828
2829         /* Finally... display all instructions up to the value of the pc when the
2830          * debug break occurred (saved when trace data was collected from target).
2831          * This is necessary because the trace only records execution branches and 16
2832          * consecutive instructions (rollovers), so last few typically missed.
2833          */
2834         if (current_pc == 0)
2835                 return ERROR_OK;/* current_pc was never found */
2836
2837         /* how many instructions remaining? */
2838         int gap_count = (breakpoint_pc - current_pc) /
2839                 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2840
2841         /* should never be negative or over 16, but verify */
2842         if (gap_count < 0 || gap_count > 16) {
2843                 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2844                 return ERROR_OK;/* bail; large number or negative value no good */
2845         }
2846
2847         /* display remaining instructions */
2848         for (i = 0; i < gap_count; i++) {
2849                 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2850                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2851         }
2852
2853         return ERROR_OK;
2854 }
2855
2856 static const struct reg_arch_type xscale_reg_type = {
2857         .get = xscale_get_reg,
2858         .set = xscale_set_reg,
2859 };
2860
2861 static void xscale_build_reg_cache(struct target *target)
2862 {
2863         struct xscale_common *xscale = target_to_xscale(target);
2864         struct arm *arm = &xscale->arm;
2865         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2866         struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2867         int i;
2868         int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2869
2870         (*cache_p) = arm_build_reg_cache(target, arm);
2871
2872         (*cache_p)->next = malloc(sizeof(struct reg_cache));
2873         cache_p = &(*cache_p)->next;
2874
2875         /* fill in values for the xscale reg cache */
2876         (*cache_p)->name = "XScale registers";
2877         (*cache_p)->next = NULL;
2878         (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
2879         (*cache_p)->num_regs = num_regs;
2880
2881         for (i = 0; i < num_regs; i++) {
2882                 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2883                 (*cache_p)->reg_list[i].value = calloc(4, 1);
2884                 (*cache_p)->reg_list[i].dirty = 0;
2885                 (*cache_p)->reg_list[i].valid = 0;
2886                 (*cache_p)->reg_list[i].size = 32;
2887                 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2888                 (*cache_p)->reg_list[i].type = &xscale_reg_type;
2889                 arch_info[i] = xscale_reg_arch_info[i];
2890                 arch_info[i].target = target;
2891         }
2892
2893         xscale->reg_cache = (*cache_p);
2894 }
2895
2896 static int xscale_init_target(struct command_context *cmd_ctx,
2897         struct target *target)
2898 {
2899         xscale_build_reg_cache(target);
2900         return ERROR_OK;
2901 }
2902
2903 static int xscale_init_arch_info(struct target *target,
2904         struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
2905 {
2906         struct arm *arm;
2907         uint32_t high_reset_branch, low_reset_branch;
2908         int i;
2909
2910         arm = &xscale->arm;
2911
2912         /* store architecture specfic data */
2913         xscale->common_magic = XSCALE_COMMON_MAGIC;
2914
2915         /* we don't really *need* a variant param ... */
2916         if (variant) {
2917                 int ir_length = 0;
2918
2919                 if (strcmp(variant, "pxa250") == 0
2920                         || strcmp(variant, "pxa255") == 0
2921                         || strcmp(variant, "pxa26x") == 0)
2922                         ir_length = 5;
2923                 else if (strcmp(variant, "pxa27x") == 0
2924                         || strcmp(variant, "ixp42x") == 0
2925                         || strcmp(variant, "ixp45x") == 0
2926                         || strcmp(variant, "ixp46x") == 0)
2927                         ir_length = 7;
2928                 else if (strcmp(variant, "pxa3xx") == 0)
2929                         ir_length = 11;
2930                 else
2931                         LOG_WARNING("%s: unrecognized variant %s",
2932                                 tap->dotted_name, variant);
2933
2934                 if (ir_length && ir_length != tap->ir_length) {
2935                         LOG_WARNING("%s: IR length for %s is %d; fixing",
2936                                 tap->dotted_name, variant, ir_length);
2937                         tap->ir_length = ir_length;
2938                 }
2939         }
2940
2941         /* PXA3xx shifts the JTAG instructions */
2942         if (tap->ir_length == 11)
2943                 xscale->xscale_variant = XSCALE_PXA3XX;
2944         else
2945                 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
2946
2947         /* the debug handler isn't installed (and thus not running) at this time */
2948         xscale->handler_address = 0xfe000800;
2949
2950         /* clear the vectors we keep locally for reference */
2951         memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
2952         memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
2953
2954         /* no user-specified vectors have been configured yet */
2955         xscale->static_low_vectors_set = 0x0;
2956         xscale->static_high_vectors_set = 0x0;
2957
2958         /* calculate branches to debug handler */
2959         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
2960         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2961
2962         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
2963         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
2964
2965         for (i = 1; i <= 7; i++) {
2966                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2967                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2968         }
2969
2970         /* 64kB aligned region used for DCache cleaning */
2971         xscale->cache_clean_address = 0xfffe0000;
2972
2973         xscale->hold_rst = 0;
2974         xscale->external_debug_break = 0;
2975
2976         xscale->ibcr_available = 2;
2977         xscale->ibcr0_used = 0;
2978         xscale->ibcr1_used = 0;
2979
2980         xscale->dbr_available = 2;
2981         xscale->dbr0_used = 0;
2982         xscale->dbr1_used = 0;
2983
2984         LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
2985                 target_name(target));
2986
2987         xscale->arm_bkpt = ARMV5_BKPT(0x0);
2988         xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
2989
2990         xscale->vector_catch = 0x1;
2991
2992         xscale->trace.data = NULL;
2993         xscale->trace.image = NULL;
2994         xscale->trace.mode = XSCALE_TRACE_DISABLED;
2995         xscale->trace.buffer_fill = 0;
2996         xscale->trace.fill_counter = 0;
2997
2998         /* prepare ARMv4/5 specific information */
2999         arm->arch_info = xscale;
3000         arm->core_type = ARM_MODE_ANY;
3001         arm->read_core_reg = xscale_read_core_reg;
3002         arm->write_core_reg = xscale_write_core_reg;
3003         arm->full_context = xscale_full_context;
3004
3005         arm_init_arch_info(target, arm);
3006
3007         xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3008         xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3009         xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3010         xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3011         xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3012         xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3013         xscale->armv4_5_mmu.has_tiny_pages = 1;
3014         xscale->armv4_5_mmu.mmu_enabled = 0;
3015
3016         return ERROR_OK;
3017 }
3018
3019 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3020 {
3021         struct xscale_common *xscale;
3022
3023         if (sizeof xscale_debug_handler - 1 > 0x800) {
3024                 LOG_ERROR("debug_handler.bin: larger than 2kb");
3025                 return ERROR_FAIL;
3026         }
3027
3028         xscale = calloc(1, sizeof(*xscale));
3029         if (!xscale)
3030                 return ERROR_FAIL;
3031
3032         return xscale_init_arch_info(target, xscale, target->tap,
3033                         target->variant);
3034 }
3035
3036 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3037 {
3038         struct target *target = NULL;
3039         struct xscale_common *xscale;
3040         int retval;
3041         uint32_t handler_address;
3042
3043         if (CMD_ARGC < 2)
3044                 return ERROR_COMMAND_SYNTAX_ERROR;
3045
3046         target = get_target(CMD_ARGV[0]);
3047         if (target == NULL) {
3048                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3049                 return ERROR_FAIL;
3050         }
3051
3052         xscale = target_to_xscale(target);
3053         retval = xscale_verify_pointer(CMD_CTX, xscale);
3054         if (retval != ERROR_OK)
3055                 return retval;
3056
3057         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3058
3059         if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3060                 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3061                 xscale->handler_address = handler_address;
3062         else {
3063                 LOG_ERROR(
3064                         "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3065                 return ERROR_FAIL;
3066         }
3067
3068         return ERROR_OK;
3069 }
3070
3071 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3072 {
3073         struct target *target = NULL;
3074         struct xscale_common *xscale;
3075         int retval;
3076         uint32_t cache_clean_address;
3077
3078         if (CMD_ARGC < 2)
3079                 return ERROR_COMMAND_SYNTAX_ERROR;
3080
3081         target = get_target(CMD_ARGV[0]);
3082         if (target == NULL) {
3083                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3084                 return ERROR_FAIL;
3085         }
3086         xscale = target_to_xscale(target);
3087         retval = xscale_verify_pointer(CMD_CTX, xscale);
3088         if (retval != ERROR_OK)
3089                 return retval;
3090
3091         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3092
3093         if (cache_clean_address & 0xffff)
3094                 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3095         else
3096                 xscale->cache_clean_address = cache_clean_address;
3097
3098         return ERROR_OK;
3099 }
3100
3101 COMMAND_HANDLER(xscale_handle_cache_info_command)
3102 {
3103         struct target *target = get_current_target(CMD_CTX);
3104         struct xscale_common *xscale = target_to_xscale(target);
3105         int retval;
3106
3107         retval = xscale_verify_pointer(CMD_CTX, xscale);
3108         if (retval != ERROR_OK)
3109                 return retval;
3110
3111         return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
3112 }
3113
3114 static int xscale_virt2phys(struct target *target,
3115         uint32_t virtual, uint32_t *physical)
3116 {
3117         struct xscale_common *xscale = target_to_xscale(target);
3118         uint32_t cb;
3119
3120         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3121                 LOG_ERROR(xscale_not);
3122                 return ERROR_TARGET_INVALID;
3123         }
3124
3125         uint32_t ret;
3126         int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3127                         virtual, &cb, &ret);
3128         if (retval != ERROR_OK)
3129                 return retval;
3130         *physical = ret;
3131         return ERROR_OK;
3132 }
3133
3134 static int xscale_mmu(struct target *target, int *enabled)
3135 {
3136         struct xscale_common *xscale = target_to_xscale(target);
3137
3138         if (target->state != TARGET_HALTED) {
3139                 LOG_ERROR("Target not halted");
3140                 return ERROR_TARGET_INVALID;
3141         }
3142         *enabled = xscale->armv4_5_mmu.mmu_enabled;
3143         return ERROR_OK;
3144 }
3145
3146 COMMAND_HANDLER(xscale_handle_mmu_command)
3147 {
3148         struct target *target = get_current_target(CMD_CTX);
3149         struct xscale_common *xscale = target_to_xscale(target);
3150         int retval;
3151
3152         retval = xscale_verify_pointer(CMD_CTX, xscale);
3153         if (retval != ERROR_OK)
3154                 return retval;
3155
3156         if (target->state != TARGET_HALTED) {
3157                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3158                 return ERROR_OK;
3159         }
3160
3161         if (CMD_ARGC >= 1) {
3162                 bool enable;
3163                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3164                 if (enable)
3165                         xscale_enable_mmu_caches(target, 1, 0, 0);
3166                 else
3167                         xscale_disable_mmu_caches(target, 1, 0, 0);
3168                 xscale->armv4_5_mmu.mmu_enabled = enable;
3169         }
3170
3171         command_print(CMD_CTX, "mmu %s",
3172                 (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3173
3174         return ERROR_OK;
3175 }
3176
3177 COMMAND_HANDLER(xscale_handle_idcache_command)
3178 {
3179         struct target *target = get_current_target(CMD_CTX);
3180         struct xscale_common *xscale = target_to_xscale(target);
3181
3182         int retval = xscale_verify_pointer(CMD_CTX, xscale);
3183         if (retval != ERROR_OK)
3184                 return retval;
3185
3186         if (target->state != TARGET_HALTED) {
3187                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3188                 return ERROR_OK;
3189         }
3190
3191         bool icache = false;
3192         if (strcmp(CMD_NAME, "icache") == 0)
3193                 icache = true;
3194         if (CMD_ARGC >= 1) {
3195                 bool enable;
3196                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3197                 if (icache) {
3198                         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3199                         if (enable)
3200                                 xscale_enable_mmu_caches(target, 0, 0, 1);
3201                         else
3202                                 xscale_disable_mmu_caches(target, 0, 0, 1);
3203                 } else {
3204                         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3205                         if (enable)
3206                                 xscale_enable_mmu_caches(target, 0, 1, 0);
3207                         else
3208                                 xscale_disable_mmu_caches(target, 0, 1, 0);
3209                 }
3210         }
3211
3212         bool enabled = icache ?
3213                 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3214                 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3215         const char *msg = enabled ? "enabled" : "disabled";
3216         command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
3217
3218         return ERROR_OK;
3219 }
3220
3221 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3222 {
3223         struct target *target = get_current_target(CMD_CTX);
3224         struct xscale_common *xscale = target_to_xscale(target);
3225         int retval;
3226
3227         retval = xscale_verify_pointer(CMD_CTX, xscale);
3228         if (retval != ERROR_OK)
3229                 return retval;
3230
3231         if (CMD_ARGC < 1)
3232                 return ERROR_COMMAND_SYNTAX_ERROR;
3233         else {
3234                 COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch);
3235                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value,
3236                         16,
3237                         8,
3238                         xscale->vector_catch);
3239                 xscale_write_dcsr(target, -1, -1);
3240         }
3241
3242         command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3243
3244         return ERROR_OK;
3245 }
3246
3247
3248 COMMAND_HANDLER(xscale_handle_vector_table_command)
3249 {
3250         struct target *target = get_current_target(CMD_CTX);
3251         struct xscale_common *xscale = target_to_xscale(target);
3252         int err = 0;
3253         int retval;
3254
3255         retval = xscale_verify_pointer(CMD_CTX, xscale);
3256         if (retval != ERROR_OK)
3257                 return retval;
3258
3259         if (CMD_ARGC == 0) {    /* print current settings */
3260                 int idx;
3261
3262                 command_print(CMD_CTX, "active user-set static vectors:");
3263                 for (idx = 1; idx < 8; idx++)
3264                         if (xscale->static_low_vectors_set & (1 << idx))
3265                                 command_print(CMD_CTX,
3266                                         "low  %d: 0x%" PRIx32,
3267                                         idx,
3268                                         xscale->static_low_vectors[idx]);
3269                 for (idx = 1; idx < 8; idx++)
3270                         if (xscale->static_high_vectors_set & (1 << idx))
3271                                 command_print(CMD_CTX,
3272                                         "high %d: 0x%" PRIx32,
3273                                         idx,
3274                                         xscale->static_high_vectors[idx]);
3275                 return ERROR_OK;
3276         }
3277
3278         if (CMD_ARGC != 3)
3279                 err = 1;
3280         else {
3281                 int idx;
3282                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3283                 uint32_t vec;
3284                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3285
3286                 if (idx < 1 || idx >= 8)
3287                         err = 1;
3288
3289                 if (!err && strcmp(CMD_ARGV[0], "low") == 0) {
3290                         xscale->static_low_vectors_set |= (1<<idx);
3291                         xscale->static_low_vectors[idx] = vec;
3292                 } else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) {
3293                         xscale->static_high_vectors_set |= (1<<idx);
3294                         xscale->static_high_vectors[idx] = vec;
3295                 } else
3296                         err = 1;
3297         }
3298
3299         if (err)
3300                 return ERROR_COMMAND_SYNTAX_ERROR;
3301
3302         return ERROR_OK;
3303 }
3304
3305
3306 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3307 {
3308         struct target *target = get_current_target(CMD_CTX);
3309         struct xscale_common *xscale = target_to_xscale(target);
3310         uint32_t dcsr_value;
3311         int retval;
3312
3313         retval = xscale_verify_pointer(CMD_CTX, xscale);
3314         if (retval != ERROR_OK)
3315                 return retval;
3316
3317         if (target->state != TARGET_HALTED) {
3318                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3319                 return ERROR_OK;
3320         }
3321
3322         if (CMD_ARGC >= 1) {
3323                 if (strcmp("enable", CMD_ARGV[0]) == 0)
3324                         xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */
3325                 else if (strcmp("disable", CMD_ARGV[0]) == 0)
3326                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3327                 else
3328                         return ERROR_COMMAND_SYNTAX_ERROR;
3329         }
3330
3331         if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3332                 if (strcmp("fill", CMD_ARGV[1]) == 0) {
3333                         int buffcount = 1;              /* default */
3334                         if (CMD_ARGC >= 3)
3335                                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount);
3336                         if (buffcount < 1) {            /* invalid */
3337                                 command_print(CMD_CTX, "fill buffer count must be > 0");
3338                                 xscale->trace.mode = XSCALE_TRACE_DISABLED;
3339                                 return ERROR_COMMAND_SYNTAX_ERROR;
3340                         }
3341                         xscale->trace.buffer_fill = buffcount;
3342                         xscale->trace.mode = XSCALE_TRACE_FILL;
3343                 } else if (strcmp("wrap", CMD_ARGV[1]) == 0)
3344                         xscale->trace.mode = XSCALE_TRACE_WRAP;
3345                 else {
3346                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3347                         return ERROR_COMMAND_SYNTAX_ERROR;
3348                 }
3349         }
3350
3351         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3352                 char fill_string[12];
3353                 sprintf(fill_string, "fill %" PRId32, xscale->trace.buffer_fill);
3354                 command_print(CMD_CTX, "trace buffer enabled (%s)",
3355                         (xscale->trace.mode == XSCALE_TRACE_FILL)
3356                         ? fill_string : "wrap");
3357         } else
3358                 command_print(CMD_CTX, "trace buffer disabled");
3359
3360         dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3361         if (xscale->trace.mode == XSCALE_TRACE_FILL)
3362                 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3363         else
3364                 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3365
3366         return ERROR_OK;
3367 }
3368
3369 COMMAND_HANDLER(xscale_handle_trace_image_command)
3370 {
3371         struct target *target = get_current_target(CMD_CTX);
3372         struct xscale_common *xscale = target_to_xscale(target);
3373         int retval;
3374
3375         if (CMD_ARGC < 1)
3376                 return ERROR_COMMAND_SYNTAX_ERROR;
3377
3378         retval = xscale_verify_pointer(CMD_CTX, xscale);
3379         if (retval != ERROR_OK)
3380                 return retval;
3381
3382         if (xscale->trace.image) {
3383                 image_close(xscale->trace.image);
3384                 free(xscale->trace.image);
3385                 command_print(CMD_CTX, "previously loaded image found and closed");
3386         }
3387
3388         xscale->trace.image = malloc(sizeof(struct image));
3389         xscale->trace.image->base_address_set = 0;
3390         xscale->trace.image->start_address_set = 0;
3391
3392         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3393         if (CMD_ARGC >= 2) {
3394                 xscale->trace.image->base_address_set = 1;
3395                 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3396         } else
3397                 xscale->trace.image->base_address_set = 0;
3398
3399         if (image_open(xscale->trace.image, CMD_ARGV[0],
3400                 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
3401                 free(xscale->trace.image);
3402                 xscale->trace.image = NULL;
3403                 return ERROR_OK;
3404         }
3405
3406         return ERROR_OK;
3407 }
3408
3409 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3410 {
3411         struct target *target = get_current_target(CMD_CTX);
3412         struct xscale_common *xscale = target_to_xscale(target);
3413         struct xscale_trace_data *trace_data;
3414         struct fileio file;
3415         int retval;
3416
3417         retval = xscale_verify_pointer(CMD_CTX, xscale);
3418         if (retval != ERROR_OK)
3419                 return retval;
3420
3421         if (target->state != TARGET_HALTED) {
3422                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3423                 return ERROR_OK;
3424         }
3425
3426         if (CMD_ARGC < 1)
3427                 return ERROR_COMMAND_SYNTAX_ERROR;
3428
3429         trace_data = xscale->trace.data;
3430
3431         if (!trace_data) {
3432                 command_print(CMD_CTX, "no trace data collected");
3433                 return ERROR_OK;
3434         }
3435
3436         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3437                 return ERROR_OK;
3438
3439         while (trace_data) {
3440                 int i;
3441
3442                 fileio_write_u32(&file, trace_data->chkpt0);
3443                 fileio_write_u32(&file, trace_data->chkpt1);
3444                 fileio_write_u32(&file, trace_data->last_instruction);
3445                 fileio_write_u32(&file, trace_data->depth);
3446
3447                 for (i = 0; i < trace_data->depth; i++)
3448                         fileio_write_u32(&file, trace_data->entries[i].data |
3449                                 ((trace_data->entries[i].type & 0xffff) << 16));
3450
3451                 trace_data = trace_data->next;
3452         }
3453
3454         fileio_close(&file);
3455
3456         return ERROR_OK;
3457 }
3458
3459 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3460 {
3461         struct target *target = get_current_target(CMD_CTX);
3462         struct xscale_common *xscale = target_to_xscale(target);
3463         int retval;
3464
3465         retval = xscale_verify_pointer(CMD_CTX, xscale);
3466         if (retval != ERROR_OK)
3467                 return retval;
3468
3469         xscale_analyze_trace(target, CMD_CTX);
3470
3471         return ERROR_OK;
3472 }
3473
3474 COMMAND_HANDLER(xscale_handle_cp15)
3475 {
3476         struct target *target = get_current_target(CMD_CTX);
3477         struct xscale_common *xscale = target_to_xscale(target);
3478         int retval;
3479
3480         retval = xscale_verify_pointer(CMD_CTX, xscale);
3481         if (retval != ERROR_OK)
3482                 return retval;
3483
3484         if (target->state != TARGET_HALTED) {
3485                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3486                 return ERROR_OK;
3487         }
3488         uint32_t reg_no = 0;
3489         struct reg *reg = NULL;
3490         if (CMD_ARGC > 0) {
3491                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3492                 /*translate from xscale cp15 register no to openocd register*/
3493                 switch (reg_no) {
3494                         case 0:
3495                                 reg_no = XSCALE_MAINID;
3496                                 break;
3497                         case 1:
3498                                 reg_no = XSCALE_CTRL;
3499                                 break;
3500                         case 2:
3501                                 reg_no = XSCALE_TTB;
3502                                 break;
3503                         case 3:
3504                                 reg_no = XSCALE_DAC;
3505                                 break;
3506                         case 5:
3507                                 reg_no = XSCALE_FSR;
3508                                 break;
3509                         case 6:
3510                                 reg_no = XSCALE_FAR;
3511                                 break;
3512                         case 13:
3513                                 reg_no = XSCALE_PID;
3514                                 break;
3515                         case 15:
3516                                 reg_no = XSCALE_CPACCESS;
3517                                 break;
3518                         default:
3519                                 command_print(CMD_CTX, "invalid register number");
3520                                 return ERROR_COMMAND_SYNTAX_ERROR;
3521                 }
3522                 reg = &xscale->reg_cache->reg_list[reg_no];
3523
3524         }
3525         if (CMD_ARGC == 1) {
3526                 uint32_t value;
3527
3528                 /* read cp15 control register */
3529                 xscale_get_reg(reg);
3530                 value = buf_get_u32(reg->value, 0, 32);
3531                 command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
3532                         value);
3533         } else if (CMD_ARGC == 2) {
3534                 uint32_t value;
3535                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3536
3537                 /* send CP write request (command 0x41) */
3538                 xscale_send_u32(target, 0x41);
3539
3540                 /* send CP register number */
3541                 xscale_send_u32(target, reg_no);
3542
3543                 /* send CP register value */
3544                 xscale_send_u32(target, value);
3545
3546                 /* execute cpwait to ensure outstanding operations complete */
3547                 xscale_send_u32(target, 0x53);
3548         } else
3549                 return ERROR_COMMAND_SYNTAX_ERROR;
3550
3551         return ERROR_OK;
3552 }
3553
3554 static const struct command_registration xscale_exec_command_handlers[] = {
3555         {
3556                 .name = "cache_info",
3557                 .handler = xscale_handle_cache_info_command,
3558                 .mode = COMMAND_EXEC,
3559                 .help = "display information about CPU caches",
3560         },
3561         {
3562                 .name = "mmu",
3563                 .handler = xscale_handle_mmu_command,
3564                 .mode = COMMAND_EXEC,
3565                 .help = "enable or disable the MMU",
3566                 .usage = "['enable'|'disable']",
3567         },
3568         {
3569                 .name = "icache",
3570                 .handler = xscale_handle_idcache_command,
3571                 .mode = COMMAND_EXEC,
3572                 .help = "display ICache state, optionally enabling or "
3573                         "disabling it",
3574                 .usage = "['enable'|'disable']",
3575         },
3576         {
3577                 .name = "dcache",
3578                 .handler = xscale_handle_idcache_command,
3579                 .mode = COMMAND_EXEC,
3580                 .help = "display DCache state, optionally enabling or "
3581                         "disabling it",
3582                 .usage = "['enable'|'disable']",
3583         },
3584         {
3585                 .name = "vector_catch",
3586                 .handler = xscale_handle_vector_catch_command,
3587                 .mode = COMMAND_EXEC,
3588                 .help = "set or display 8-bit mask of vectors "
3589                         "that should trigger debug entry",
3590                 .usage = "[mask]",
3591         },
3592         {
3593                 .name = "vector_table",
3594                 .handler = xscale_handle_vector_table_command,
3595                 .mode = COMMAND_EXEC,
3596                 .help = "set vector table entry in mini-ICache, "
3597                         "or display current tables",
3598                 .usage = "[('high'|'low') index code]",
3599         },
3600         {
3601                 .name = "trace_buffer",
3602                 .handler = xscale_handle_trace_buffer_command,
3603                 .mode = COMMAND_EXEC,
3604                 .help = "display trace buffer status, enable or disable "
3605                         "tracing, and optionally reconfigure trace mode",
3606                 .usage = "['enable'|'disable' ['fill' [number]|'wrap']]",
3607         },
3608         {
3609                 .name = "dump_trace",
3610                 .handler = xscale_handle_dump_trace_command,
3611                 .mode = COMMAND_EXEC,
3612                 .help = "dump content of trace buffer to file",
3613                 .usage = "filename",
3614         },
3615         {
3616                 .name = "analyze_trace",
3617                 .handler = xscale_handle_analyze_trace_buffer_command,
3618                 .mode = COMMAND_EXEC,
3619                 .help = "analyze content of trace buffer",
3620                 .usage = "",
3621         },
3622         {
3623                 .name = "trace_image",
3624                 .handler = xscale_handle_trace_image_command,
3625                 .mode = COMMAND_EXEC,
3626                 .help = "load image from file to address (default 0)",
3627                 .usage = "filename [offset [filetype]]",
3628         },
3629         {
3630                 .name = "cp15",
3631                 .handler = xscale_handle_cp15,
3632                 .mode = COMMAND_EXEC,
3633                 .help = "Read or write coprocessor 15 register.",
3634                 .usage = "register [value]",
3635         },
3636         COMMAND_REGISTRATION_DONE
3637 };
3638 static const struct command_registration xscale_any_command_handlers[] = {
3639         {
3640                 .name = "debug_handler",
3641                 .handler = xscale_handle_debug_handler_command,
3642                 .mode = COMMAND_ANY,
3643                 .help = "Change address used for debug handler.",
3644                 .usage = "<target> <address>",
3645         },
3646         {
3647                 .name = "cache_clean_address",
3648                 .handler = xscale_handle_cache_clean_address_command,
3649                 .mode = COMMAND_ANY,
3650                 .help = "Change address used for cleaning data cache.",
3651                 .usage = "address",
3652         },
3653         {
3654                 .chain = xscale_exec_command_handlers,
3655         },
3656         COMMAND_REGISTRATION_DONE
3657 };
3658 static const struct command_registration xscale_command_handlers[] = {
3659         {
3660                 .chain = arm_command_handlers,
3661         },
3662         {
3663                 .name = "xscale",
3664                 .mode = COMMAND_ANY,
3665                 .help = "xscale command group",
3666                 .usage = "",
3667                 .chain = xscale_any_command_handlers,
3668         },
3669         COMMAND_REGISTRATION_DONE
3670 };
3671
3672 struct target_type xscale_target = {
3673         .name = "xscale",
3674
3675         .poll = xscale_poll,
3676         .arch_state = xscale_arch_state,
3677
3678         .target_request_data = NULL,
3679
3680         .halt = xscale_halt,
3681         .resume = xscale_resume,
3682         .step = xscale_step,
3683
3684         .assert_reset = xscale_assert_reset,
3685         .deassert_reset = xscale_deassert_reset,
3686         .soft_reset_halt = NULL,
3687
3688         /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3689         .get_gdb_reg_list = arm_get_gdb_reg_list,
3690
3691         .read_memory = xscale_read_memory,
3692         .read_phys_memory = xscale_read_phys_memory,
3693         .write_memory = xscale_write_memory,
3694         .write_phys_memory = xscale_write_phys_memory,
3695
3696         .checksum_memory = arm_checksum_memory,
3697         .blank_check_memory = arm_blank_check_memory,
3698
3699         .run_algorithm = armv4_5_run_algorithm,
3700
3701         .add_breakpoint = xscale_add_breakpoint,
3702         .remove_breakpoint = xscale_remove_breakpoint,
3703         .add_watchpoint = xscale_add_watchpoint,
3704         .remove_watchpoint = xscale_remove_watchpoint,
3705
3706         .commands = xscale_command_handlers,
3707         .target_create = xscale_target_create,
3708         .init_target = xscale_init_target,
3709
3710         .virt2phys = xscale_virt2phys,
3711         .mmu = xscale_mmu
3712 };