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2015-12-29	Matthias Welwarsky	cortex_a: add 'dacrfixup' to cortex-a command group Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-12-29	Matthias Welwarsky	AM335x: allow simultaneous debugging of A8 and M3 cores Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-12-29	Matthias Welwarsky	arm_debug: optimize DP and AP reads over JTAG Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-12-29	Matthias Welwarsky	cortex_a: select APB-AP as the default AP Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-12-01	Matthias Welwarsky	cortex_a: fix fast-mode memory reads Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	cortex_a: replace cortex_a_check_address function Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	cortex_a: rework mmu manipulation Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	cortex_a: force cache and tlb bypass when cpu is in... Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: fix-up dcache clean and flush functions inner... Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	cortex_a: Update instruction cache after setting a... Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: correctly handle invalidation of inner data... Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: fix debug messages regarding cache on/off state Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: rework automatic flush-on-write handling Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: add d-cache virtual address range flush function Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: remove indirection for cache info handler Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: fix handling of inner caches Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: remove special l2x flush-all and cache-info... Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-30	Matthias Welwarsky	armv7a: rename l2_cache to outer_cache Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-05	Matthias Welwarsky	armv7a: correct calculation of ttbr0_mask Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-05	Matthias Welwarsky	armv7a: re-read ttb information if ttbcr changes Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-04	Matthias Welwarsky	Revert "board: don't hardcode interface for ti_beaglebone" Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree
2015-11-03	Matthias Welwarsky	board: don't hardcode interface for ti_beaglebone Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>	commit \| commitdiff \| tree

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