git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32429i-eval-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/memory/stm32-sdram.h>
   8 /{
   9         clocks {
  10                 u-boot,dm-pre-reloc;
  11         };
  12
  13         aliases {
  14                 /* Aliases for gpios so as to use sequence */
  15                 gpio0 = &gpioa;
  16                 gpio1 = &gpiob;
  17                 gpio2 = &gpioc;
  18                 gpio3 = &gpiod;
  19                 gpio4 = &gpioe;
  20                 gpio5 = &gpiof;
  21                 gpio6 = &gpiog;
  22                 gpio7 = &gpioh;
  23                 gpio8 = &gpioi;
  24                 gpio9 = &gpioj;
  25                 gpio10 = &gpiok;
  26         };
  27
  28         soc {
  29                 u-boot,dm-pre-reloc;
  30                 pin-controller {
  31                         u-boot,dm-pre-reloc;
  32                 };
  33
  34                 fmc: fmc@A0000000 {
  35                         compatible = "st,stm32-fmc";
  36                         reg = <0xA0000000 0x1000>;
  37                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
  38                         st,syscfg = <&syscfg>;
  39                         pinctrl-0 = <&fmc_pins_d32>;
  40                         pinctrl-names = "default";
  41                         st,mem_remap = <4>;
  42                         u-boot,dm-pre-reloc;
  43
  44                         /*
  45                          * Memory configuration from sdram
  46                          * MICRON MT48LC4M32B2B5-7
  47                          */
  48                         bank0: bank@0 {
  49                                st,sdram-control = /bits/ 8 <NO_COL_9
  50                                                             NO_ROW_12
  51                                                             MWIDTH_32
  52                                                             BANKS_4
  53                                                             CAS_3
  54                                                             SDCLK_2
  55                                                             RD_BURST_EN
  56                                                             RD_PIPE_DL_0>;
  57                                st,sdram-timing = /bits/ 8 <TMRD_2
  58                                                            TXSR_6
  59                                                            TRAS_4
  60                                                            TRC_6
  61                                                            TWR_2
  62                                                            TRP_2
  63                                                            TRCD_2>;
  64                                st,sdram-refcount = < 2812 >;
  65                        };
  66                 };
  67         };
  68 };
  69
  70 &clk_hse {
  71         u-boot,dm-pre-reloc;
  72 };
  73
  74 &clk_lse {
  75         u-boot,dm-pre-reloc;
  76 };
  77
  78 &clk_i2s_ckin {
  79         u-boot,dm-pre-reloc;
  80 };
  81
  82 &pwrcfg {
  83         u-boot,dm-pre-reloc;
  84 };
  85
  86 &syscfg {
  87         u-boot,dm-pre-reloc;
  88 };
  89
  90 &rcc {
  91         u-boot,dm-pre-reloc;
  92 };
  93
  94 &gpioa {
  95         compatible = "st,stm32-gpio";
  96         u-boot,dm-pre-reloc;
  97 };
  98
  99 &gpiob {
 100         compatible = "st,stm32-gpio";
 101         u-boot,dm-pre-reloc;
 102 };
 103
 104 &gpioc {
 105         compatible = "st,stm32-gpio";
 106         u-boot,dm-pre-reloc;
 107 };
 108
 109 &gpiod {
 110         compatible = "st,stm32-gpio";
 111         u-boot,dm-pre-reloc;
 112 };
 113
 114 &gpioe {
 115         compatible = "st,stm32-gpio";
 116         u-boot,dm-pre-reloc;
 117 };
 118
 119 &gpiof {
 120         compatible = "st,stm32-gpio";
 121         u-boot,dm-pre-reloc;
 122 };
 123
 124 &gpiog {
 125         compatible = "st,stm32-gpio";
 126         u-boot,dm-pre-reloc;
 127 };
 128
 129 &gpioh {
 130         compatible = "st,stm32-gpio";
 131         u-boot,dm-pre-reloc;
 132 };
 133
 134 &gpioi {
 135         compatible = "st,stm32-gpio";
 136         u-boot,dm-pre-reloc;
 137 };
 138
 139 &gpioj {
 140         compatible = "st,stm32-gpio";
 141         u-boot,dm-pre-reloc;
 142 };
 143
 144 &gpiok {
 145         compatible = "st,stm32-gpio";
 146         u-boot,dm-pre-reloc;
 147 };
 148
 149 &pinctrl {
 150         usart1_pins_a: usart1@0 {
 151                 u-boot,dm-pre-reloc;
 152                 pins1 {
 153                         u-boot,dm-pre-reloc;
 154                 };
 155                 pins2 {
 156                         u-boot,dm-pre-reloc;
 157                 };
 158         };
 159
 160         fmc_pins_d32: fmc_d32@0 {
 161                 u-boot,dm-pre-reloc;
 162                 pins
 163                 {
 164                         pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
 165                                  <STM32_PINMUX('I', 9, AF12)>, /* D30 */
 166                                  <STM32_PINMUX('I', 7, AF12)>, /* D29 */
 167                                  <STM32_PINMUX('I', 6, AF12)>, /* D28 */
 168                                  <STM32_PINMUX('I', 3, AF12)>, /* D27 */
 169                                  <STM32_PINMUX('I', 2, AF12)>, /* D26 */
 170                                  <STM32_PINMUX('I', 1, AF12)>, /* D25 */
 171                                  <STM32_PINMUX('I', 0, AF12)>, /* D24 */
 172                                  <STM32_PINMUX('H',15, AF12)>, /* D23 */
 173                                  <STM32_PINMUX('H',14, AF12)>, /* D22 */
 174                                  <STM32_PINMUX('H',13, AF12)>, /* D21 */
 175                                  <STM32_PINMUX('H',12, AF12)>, /* D20 */
 176                                  <STM32_PINMUX('H',11, AF12)>, /* D19 */
 177                                  <STM32_PINMUX('H',10, AF12)>, /* D18 */
 178                                  <STM32_PINMUX('H', 9, AF12)>, /* D17 */
 179                                  <STM32_PINMUX('H', 8, AF12)>, /* D16 */
 180
 181                                  <STM32_PINMUX('D',10, AF12)>, /* D15 */
 182                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 183                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 184                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 185                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 186                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 187                                  <STM32_PINMUX('E',12, AF12)>, /* D09 */
 188                                  <STM32_PINMUX('E',11, AF12)>, /* D08 */
 189                                  <STM32_PINMUX('E',10, AF12)>, /* D07 */
 190                                  <STM32_PINMUX('E', 9, AF12)>, /* D06 */
 191                                  <STM32_PINMUX('E', 8, AF12)>, /* D05 */
 192                                  <STM32_PINMUX('E', 7, AF12)>, /* D04 */
 193                                  <STM32_PINMUX('D', 1, AF12)>, /* D03 */
 194                                  <STM32_PINMUX('D', 0, AF12)>, /* D02 */
 195                                  <STM32_PINMUX('D',15, AF12)>, /* D01 */
 196                                  <STM32_PINMUX('D',14, AF12)>, /* D00 */
 197
 198                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 199                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 200                                  <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
 201                                  <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
 202
 203                                  <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
 204                                  <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
 205                                  <STM32_PINMUX('G', 3, AF12)>, /* A13 */
 206                                  <STM32_PINMUX('G', 2, AF12)>, /* A12 */
 207                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 208                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 209                                  <STM32_PINMUX('F',15, AF12)>, /* A09 */
 210                                  <STM32_PINMUX('F',14, AF12)>, /* A08 */
 211                                  <STM32_PINMUX('F',13, AF12)>, /* A07 */
 212                                  <STM32_PINMUX('F',12, AF12)>, /* A06 */
 213                                  <STM32_PINMUX('F', 5, AF12)>, /* A05 */
 214                                  <STM32_PINMUX('F', 4, AF12)>, /* A04 */
 215                                  <STM32_PINMUX('F', 3, AF12)>, /* A03 */
 216                                  <STM32_PINMUX('F', 2, AF12)>, /* A02 */
 217                                  <STM32_PINMUX('F', 1, AF12)>, /* A01 */
 218                                  <STM32_PINMUX('F', 0, AF12)>, /* A00 */
 219
 220                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 221                                  <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
 222                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 223                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 224                                  <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
 225                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 226                         slew-rate = <2>;
 227                         u-boot,dm-pre-reloc;
 228                 };
 229         };
 230 };