git.sur5r.net Git - u-boot/blob - arch/arm/dts/stm32f429-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/memory/stm32-sdram.h>
   8 /{
   9         clocks {
  10                 u-boot,dm-pre-reloc;
  11         };
  12
  13         aliases {
  14                 /* Aliases for gpios so as to use sequence */
  15                 gpio0 = &gpioa;
  16                 gpio1 = &gpiob;
  17                 gpio2 = &gpioc;
  18                 gpio3 = &gpiod;
  19                 gpio4 = &gpioe;
  20                 gpio5 = &gpiof;
  21                 gpio6 = &gpiog;
  22                 gpio7 = &gpioh;
  23                 gpio8 = &gpioi;
  24                 gpio9 = &gpioj;
  25                 gpio10 = &gpiok;
  26         };
  27
  28         soc {
  29                 u-boot,dm-pre-reloc;
  30                 pin-controller {
  31                         u-boot,dm-pre-reloc;
  32                 };
  33
  34                 fmc: fmc@A0000000 {
  35                         compatible = "st,stm32-fmc";
  36                         reg = <0xA0000000 0x1000>;
  37                         clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
  38                         pinctrl-0 = <&fmc_pins>;
  39                         pinctrl-names = "default";
  40                         u-boot,dm-pre-reloc;
  41
  42                         /*
  43                          * Memory configuration from sdram datasheet
  44                          * IS42S16400J
  45                          */
  46                         bank1: bank@1 {
  47                                st,sdram-control = /bits/ 8 <NO_COL_8
  48                                                             NO_ROW_12
  49                                                             MWIDTH_16
  50                                                             BANKS_4
  51                                                             CAS_3
  52                                                             SDCLK_2
  53                                                             RD_BURST_EN
  54                                                             RD_PIPE_DL_0>;
  55                                st,sdram-timing = /bits/ 8 <TMRD_3
  56                                                            TXSR_7
  57                                                            TRAS_4
  58                                                            TRC_6
  59                                                            TWR_2
  60                                                            TRP_2 TRCD_2>;
  61                                st,sdram-refcount = < 1386 >;
  62                        };
  63                 };
  64         };
  65 };
  66
  67 &clk_hse {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &clk_lse {
  72         u-boot,dm-pre-reloc;
  73 };
  74
  75 &clk_i2s_ckin {
  76         u-boot,dm-pre-reloc;
  77 };
  78
  79 &pwrcfg {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &rcc {
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &gpioa {
  88         compatible = "st,stm32-gpio";
  89         u-boot,dm-pre-reloc;
  90 };
  91
  92 &gpiob {
  93         compatible = "st,stm32-gpio";
  94         u-boot,dm-pre-reloc;
  95 };
  96
  97 &gpioc {
  98         compatible = "st,stm32-gpio";
  99         u-boot,dm-pre-reloc;
 100 };
 101
 102 &gpiod {
 103         compatible = "st,stm32-gpio";
 104         u-boot,dm-pre-reloc;
 105 };
 106
 107 &gpioe {
 108         compatible = "st,stm32-gpio";
 109         u-boot,dm-pre-reloc;
 110 };
 111
 112 &gpiof {
 113         compatible = "st,stm32-gpio";
 114         u-boot,dm-pre-reloc;
 115 };
 116
 117 &gpiog {
 118         compatible = "st,stm32-gpio";
 119         u-boot,dm-pre-reloc;
 120 };
 121
 122 &gpioh {
 123         compatible = "st,stm32-gpio";
 124         u-boot,dm-pre-reloc;
 125 };
 126
 127 &gpioi {
 128         compatible = "st,stm32-gpio";
 129         u-boot,dm-pre-reloc;
 130 };
 131
 132 &gpioj {
 133         compatible = "st,stm32-gpio";
 134         u-boot,dm-pre-reloc;
 135 };
 136
 137 &gpiok {
 138         compatible = "st,stm32-gpio";
 139         u-boot,dm-pre-reloc;
 140 };
 141
 142 &pinctrl {
 143         usart1_pins_a: usart1@0 {
 144                 u-boot,dm-pre-reloc;
 145                 pins1 {
 146                         u-boot,dm-pre-reloc;
 147                 };
 148                 pins2 {
 149                         u-boot,dm-pre-reloc;
 150                 };
 151         };
 152
 153         fmc_pins: fmc@0 {
 154                 u-boot,dm-pre-reloc;
 155                 pins
 156                 {
 157                         pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
 158                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
 159                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
 160                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 161                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 162                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 163                                  <STM32_PINMUX('E',12, AF12)>, /* D09 */
 164                                  <STM32_PINMUX('E',11, AF12)>, /* D08 */
 165                                  <STM32_PINMUX('E',10, AF12)>, /* D07 */
 166                                  <STM32_PINMUX('E', 9, AF12)>, /* D06 */
 167                                  <STM32_PINMUX('E', 8, AF12)>, /* D05 */
 168                                  <STM32_PINMUX('E', 7, AF12)>, /* D04 */
 169                                  <STM32_PINMUX('D', 1, AF12)>, /* D03 */
 170                                  <STM32_PINMUX('D', 0, AF12)>, /* D02 */
 171                                  <STM32_PINMUX('D',15, AF12)>, /* D01 */
 172                                  <STM32_PINMUX('D',14, AF12)>, /* D00 */
 173
 174                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 175                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 176
 177                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 178                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 179
 180                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 181                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 182                                  <STM32_PINMUX('F',15, AF12)>, /* A09 */
 183                                  <STM32_PINMUX('F',14, AF12)>, /* A08 */
 184                                  <STM32_PINMUX('F',13, AF12)>, /* A07 */
 185                                  <STM32_PINMUX('F',12, AF12)>, /* A06 */
 186                                  <STM32_PINMUX('F', 5, AF12)>, /* A05 */
 187                                  <STM32_PINMUX('F', 4, AF12)>, /* A04 */
 188                                  <STM32_PINMUX('F', 3, AF12)>, /* A03 */
 189                                  <STM32_PINMUX('F', 2, AF12)>, /* A02 */
 190                                  <STM32_PINMUX('F', 1, AF12)>, /* A01 */
 191                                  <STM32_PINMUX('F', 0, AF12)>, /* A00 */
 192
 193                                  <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
 194                                  <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
 195                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 196                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 197                                  <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
 198                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
 199                         slew-rate = <2>;
 200                         u-boot,dm-pre-reloc;
 201                 };
 202         };
 203 };