git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp-zcu102-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU102 RevA
   4  *
   5  * (C) Copyright 2015 - 2018, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU102 RevA";
  21         compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 gpio0 = &gpio;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 mmc0 = &sdhci1;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51                 autorepeat;
  52                 sw19 {
  53                         label = "sw19";
  54                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  55                         linux,code = <KEY_DOWN>;
  56                         gpio-key,wakeup;
  57                         autorepeat;
  58                 };
  59         };
  60
  61         leds {
  62                 compatible = "gpio-leds";
  63                 heartbeat_led {
  64                         label = "heartbeat";
  65                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "heartbeat";
  67                 };
  68         };
  69 };
  70
  71 &can1 {
  72         status = "okay";
  73         pinctrl-names = "default";
  74         pinctrl-0 = <&pinctrl_can1_default>;
  75 };
  76
  77 &dcc {
  78         status = "okay";
  79 };
  80
  81 &fpd_dma_chan1 {
  82         status = "okay";
  83 };
  84
  85 &fpd_dma_chan2 {
  86         status = "okay";
  87 };
  88
  89 &fpd_dma_chan3 {
  90         status = "okay";
  91 };
  92
  93 &fpd_dma_chan4 {
  94         status = "okay";
  95 };
  96
  97 &fpd_dma_chan5 {
  98         status = "okay";
  99 };
 100
 101 &fpd_dma_chan6 {
 102         status = "okay";
 103 };
 104
 105 &fpd_dma_chan7 {
 106         status = "okay";
 107 };
 108
 109 &fpd_dma_chan8 {
 110         status = "okay";
 111 };
 112
 113 &gem3 {
 114         status = "okay";
 115         phy-handle = <&phy0>;
 116         phy-mode = "rgmii-id";
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gem3_default>;
 119         phy0: phy@21 {
 120                 reg = <21>;
 121                 ti,rx-internal-delay = <0x8>;
 122                 ti,tx-internal-delay = <0xa>;
 123                 ti,fifo-depth = <0x1>;
 124         };
 125 };
 126
 127 &gpio {
 128         status = "okay";
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_gpio_default>;
 131 };
 132
 133 &gpu {
 134         status = "okay";
 135 };
 136
 137 &i2c0 {
 138         status = "okay";
 139         clock-frequency = <400000>;
 140         pinctrl-names = "default", "gpio";
 141         pinctrl-0 = <&pinctrl_i2c0_default>;
 142         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 143         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 144         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 145
 146         tca6416_u97: gpio@20 {
 147                 compatible = "ti,tca6416";
 148                 reg = <0x20>;
 149                 gpio-controller;
 150                 #gpio-cells = <2>;
 151                 /*
 152                  * IRQ not connected
 153                  * Lines:
 154                  * 0 - PS_GTR_LAN_SEL0
 155                  * 1 - PS_GTR_LAN_SEL1
 156                  * 2 - PS_GTR_LAN_SEL2
 157                  * 3 - PS_GTR_LAN_SEL3
 158                  * 4 - PCI_CLK_DIR_SEL
 159                  * 5 - IIC_MUX_RESET_B
 160                  * 6 - GEM3_EXP_RESET_B
 161                  * 7, 10 - 17 - not connected
 162                  */
 163
 164                 gtr_sel0 {
 165                         gpio-hog;
 166                         gpios = <0 0>;
 167                         output-low; /* PCIE = 0, DP = 1 */
 168                         line-name = "sel0";
 169                 };
 170                 gtr_sel1 {
 171                         gpio-hog;
 172                         gpios = <1 0>;
 173                         output-high; /* PCIE = 0, DP = 1 */
 174                         line-name = "sel1";
 175                 };
 176                 gtr_sel2 {
 177                         gpio-hog;
 178                         gpios = <2 0>;
 179                         output-high; /* PCIE = 0, USB0 = 1 */
 180                         line-name = "sel2";
 181                 };
 182                 gtr_sel3 {
 183                         gpio-hog;
 184                         gpios = <3 0>;
 185                         output-high; /* PCIE = 0, SATA = 1 */
 186                         line-name = "sel3";
 187                 };
 188         };
 189
 190         tca6416_u61: gpio@21 {
 191                 compatible = "ti,tca6416";
 192                 reg = <0x21>;
 193                 gpio-controller;
 194                 #gpio-cells = <2>;
 195                 /*
 196                  * IRQ not connected
 197                  * Lines:
 198                  * 0 - VCCPSPLL_EN
 199                  * 1 - MGTRAVCC_EN
 200                  * 2 - MGTRAVTT_EN
 201                  * 3 - VCCPSDDRPLL_EN
 202                  * 4 - MIO26_PMU_INPUT_LS
 203                  * 5 - PL_PMBUS_ALERT
 204                  * 6 - PS_PMBUS_ALERT
 205                  * 7 - MAXIM_PMBUS_ALERT
 206                  * 10 - PL_DDR4_VTERM_EN
 207                  * 11 - PL_DDR4_VPP_2V5_EN
 208                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 209                  * 13 - PS_DIMM_SUSPEND_EN
 210                  * 14 - PS_DDR4_VTERM_EN
 211                  * 15 - PS_DDR4_VPP_2V5_EN
 212                  * 16 - 17 - not connected
 213                  */
 214         };
 215
 216         i2c-mux@75 { /* u60 */
 217                 compatible = "nxp,pca9544";
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 reg = <0x75>;
 221                 i2c@0 {
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         reg = <0>;
 225                         /* PS_PMBUS */
 226                         ina226@40 { /* u76 */
 227                                 compatible = "ti,ina226";
 228                                 reg = <0x40>;
 229                                 shunt-resistor = <5000>;
 230                         };
 231                         ina226@41 { /* u77 */
 232                                 compatible = "ti,ina226";
 233                                 reg = <0x41>;
 234                                 shunt-resistor = <5000>;
 235                         };
 236                         ina226@42 { /* u78 */
 237                                 compatible = "ti,ina226";
 238                                 reg = <0x42>;
 239                                 shunt-resistor = <5000>;
 240                         };
 241                         ina226@43 { /* u87 */
 242                                 compatible = "ti,ina226";
 243                                 reg = <0x43>;
 244                                 shunt-resistor = <5000>;
 245                         };
 246                         ina226@44 { /* u85 */
 247                                 compatible = "ti,ina226";
 248                                 reg = <0x44>;
 249                                 shunt-resistor = <5000>;
 250                         };
 251                         ina226@45 { /* u86 */
 252                                 compatible = "ti,ina226";
 253                                 reg = <0x45>;
 254                                 shunt-resistor = <5000>;
 255                         };
 256                         ina226@46 { /* u93 */
 257                                 compatible = "ti,ina226";
 258                                 reg = <0x46>;
 259                                 shunt-resistor = <5000>;
 260                         };
 261                         ina226@47 { /* u88 */
 262                                 compatible = "ti,ina226";
 263                                 reg = <0x47>;
 264                                 shunt-resistor = <5000>;
 265                         };
 266                         ina226@4a { /* u15 */
 267                                 compatible = "ti,ina226";
 268                                 reg = <0x4a>;
 269                                 shunt-resistor = <5000>;
 270                         };
 271                         ina226@4b { /* u92 */
 272                                 compatible = "ti,ina226";
 273                                 reg = <0x4b>;
 274                                 shunt-resistor = <5000>;
 275                         };
 276                 };
 277                 i2c@1 {
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         reg = <1>;
 281                         /* PL_PMBUS */
 282                         ina226@40 { /* u79 */
 283                                 compatible = "ti,ina226";
 284                                 reg = <0x40>;
 285                                 shunt-resistor = <2000>;
 286                         };
 287                         ina226@41 { /* u81 */
 288                                 compatible = "ti,ina226";
 289                                 reg = <0x41>;
 290                                 shunt-resistor = <5000>;
 291                         };
 292                         ina226@42 { /* u80 */
 293                                 compatible = "ti,ina226";
 294                                 reg = <0x42>;
 295                                 shunt-resistor = <5000>;
 296                         };
 297                         ina226@43 { /* u84 */
 298                                 compatible = "ti,ina226";
 299                                 reg = <0x43>;
 300                                 shunt-resistor = <5000>;
 301                         };
 302                         ina226@44 { /* u16 */
 303                                 compatible = "ti,ina226";
 304                                 reg = <0x44>;
 305                                 shunt-resistor = <5000>;
 306                         };
 307                         ina226@45 { /* u65 */
 308                                 compatible = "ti,ina226";
 309                                 reg = <0x45>;
 310                                 shunt-resistor = <5000>;
 311                         };
 312                         ina226@46 { /* u74 */
 313                                 compatible = "ti,ina226";
 314                                 reg = <0x46>;
 315                                 shunt-resistor = <5000>;
 316                         };
 317                         ina226@47 { /* u75 */
 318                                 compatible = "ti,ina226";
 319                                 reg = <0x47>;
 320                                 shunt-resistor = <5000>;
 321                         };
 322                 };
 323                 i2c@2 {
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                         reg = <2>;
 327                         /* MAXIM_PMBUS - 00 */
 328                         max15301@a { /* u46 */
 329                                 compatible = "maxim,max15301";
 330                                 reg = <0xa>;
 331                         };
 332                         max15303@b { /* u4 */
 333                                 compatible = "maxim,max15303";
 334                                 reg = <0xb>;
 335                         };
 336                         max15303@10 { /* u13 */
 337                                 compatible = "maxim,max15303";
 338                                 reg = <0x10>;
 339                         };
 340                         max15301@13 { /* u47 */
 341                                 compatible = "maxim,max15301";
 342                                 reg = <0x13>;
 343                         };
 344                         max15303@14 { /* u7 */
 345                                 compatible = "maxim,max15303";
 346                                 reg = <0x14>;
 347                         };
 348                         max15303@15 { /* u6 */
 349                                 compatible = "maxim,max15303";
 350                                 reg = <0x15>;
 351                         };
 352                         max15303@16 { /* u10 */
 353                                 compatible = "maxim,max15303";
 354                                 reg = <0x16>;
 355                         };
 356                         max15303@17 { /* u9 */
 357                                 compatible = "maxim,max15303";
 358                                 reg = <0x17>;
 359                         };
 360                         max15301@18 { /* u63 */
 361                                 compatible = "maxim,max15301";
 362                                 reg = <0x18>;
 363                         };
 364                         max15303@1a { /* u49 */
 365                                 compatible = "maxim,max15303";
 366                                 reg = <0x1a>;
 367                         };
 368                         max15303@1d { /* u18 */
 369                                 compatible = "maxim,max15303";
 370                                 reg = <0x1d>;
 371                         };
 372                         max15303@20 { /* u8 */
 373                                 compatible = "maxim,max15303";
 374                                 status = "disabled"; /* unreachable */
 375                                 reg = <0x20>;
 376                         };
 377
 378                         max20751@72 { /* u95 */
 379                                 compatible = "maxim,max20751";
 380                                 reg = <0x72>;
 381                         };
 382                         max20751@73 { /* u96 */
 383                                 compatible = "maxim,max20751";
 384                                 reg = <0x73>;
 385                         };
 386                 };
 387                 /* Bus 3 is not connected */
 388         };
 389 };
 390
 391 &i2c1 {
 392         status = "okay";
 393         clock-frequency = <400000>;
 394         pinctrl-names = "default", "gpio";
 395         pinctrl-0 = <&pinctrl_i2c1_default>;
 396         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 397         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 398         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 399
 400         /* PL i2c via PCA9306 - u45 */
 401         i2c-mux@74 { /* u34 */
 402                 compatible = "nxp,pca9548";
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 reg = <0x74>;
 406                 i2c@0 {
 407                         #address-cells = <1>;
 408                         #size-cells = <0>;
 409                         reg = <0>;
 410                         /*
 411                          * IIC_EEPROM 1kB memory which uses 256B blocks
 412                          * where every block has different address.
 413                          *    0 - 256B address 0x54
 414                          * 256B - 512B address 0x55
 415                          * 512B - 768B address 0x56
 416                          * 768B - 1024B address 0x57
 417                          */
 418                         eeprom: eeprom@54 { /* u23 */
 419                                 compatible = "atmel,24c08";
 420                                 reg = <0x54>;
 421                         };
 422                 };
 423                 i2c@1 {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         reg = <1>;
 427                         si5341: clock-generator@36 { /* SI5341 - u69 */
 428                                 compatible = "si5341";
 429                                 reg = <0x36>;
 430                         };
 431
 432                 };
 433                 i2c@2 {
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <2>;
 437                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 438                                 #clock-cells = <0>;
 439                                 compatible = "silabs,si570";
 440                                 reg = <0x5d>;
 441                                 temperature-stability = <50>;
 442                                 factory-fout = <300000000>;
 443                                 clock-frequency = <300000000>;
 444                         };
 445                 };
 446                 i2c@3 {
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         reg = <3>;
 450                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 451                                 #clock-cells = <0>;
 452                                 compatible = "silabs,si570";
 453                                 reg = <0x5d>;
 454                                 temperature-stability = <50>; /* copy from zc702 */
 455                                 factory-fout = <156250000>;
 456                                 clock-frequency = <148500000>;
 457                         };
 458                 };
 459                 i2c@4 {
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         reg = <4>;
 463                         si5328: clock-generator@69 {/* SI5328 - u20 */
 464                                 compatible = "silabs,si5328";
 465                                 reg = <0x69>;
 466                                 /*
 467                                  * Chip has interrupt present connected to PL
 468                                  * interrupt-parent = <&>;
 469                                  * interrupts = <>;
 470                                  */
 471                         };
 472                 };
 473                 /* 5 - 7 unconnected */
 474         };
 475
 476         i2c-mux@75 {
 477                 compatible = "nxp,pca9548"; /* u135 */
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 reg = <0x75>;
 481
 482                 i2c@0 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <0>;
 486                         /* HPC0_IIC */
 487                 };
 488                 i2c@1 {
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         reg = <1>;
 492                         /* HPC1_IIC */
 493                 };
 494                 i2c@2 {
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         reg = <2>;
 498                         /* SYSMON */
 499                 };
 500                 i2c@3 {
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         reg = <3>;
 504                         /* DDR4 SODIMM */
 505                         dev@19 {
 506                                 reg = <0x19>;
 507                         };
 508                         dev@30 {
 509                                 reg = <0x30>;
 510                         };
 511                         dev@35 {
 512                                 reg = <0x35>;
 513                         };
 514                         dev@36 {
 515                                 reg = <0x36>;
 516                         };
 517                         dev@51 {
 518                                 reg = <0x51>;
 519                         };
 520                 };
 521                 i2c@4 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         reg = <4>;
 525                         /* SEP 3 */
 526                 };
 527                 i2c@5 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         reg = <5>;
 531                         /* SEP 2 */
 532                 };
 533                 i2c@6 {
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         reg = <6>;
 537                         /* SEP 1 */
 538                 };
 539                 i2c@7 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         reg = <7>;
 543                         /* SEP 0 */
 544                 };
 545         };
 546 };
 547
 548 &pinctrl0 {
 549         status = "okay";
 550         pinctrl_i2c0_default: i2c0-default {
 551                 mux {
 552                         groups = "i2c0_3_grp";
 553                         function = "i2c0";
 554                 };
 555
 556                 conf {
 557                         groups = "i2c0_3_grp";
 558                         bias-pull-up;
 559                         slew-rate = <SLEW_RATE_SLOW>;
 560                         io-standard = <IO_STANDARD_LVCMOS18>;
 561                 };
 562         };
 563
 564         pinctrl_i2c0_gpio: i2c0-gpio {
 565                 mux {
 566                         groups = "gpio0_14_grp", "gpio0_15_grp";
 567                         function = "gpio0";
 568                 };
 569
 570                 conf {
 571                         groups = "gpio0_14_grp", "gpio0_15_grp";
 572                         slew-rate = <SLEW_RATE_SLOW>;
 573                         io-standard = <IO_STANDARD_LVCMOS18>;
 574                 };
 575         };
 576
 577         pinctrl_i2c1_default: i2c1-default {
 578                 mux {
 579                         groups = "i2c1_4_grp";
 580                         function = "i2c1";
 581                 };
 582
 583                 conf {
 584                         groups = "i2c1_4_grp";
 585                         bias-pull-up;
 586                         slew-rate = <SLEW_RATE_SLOW>;
 587                         io-standard = <IO_STANDARD_LVCMOS18>;
 588                 };
 589         };
 590
 591         pinctrl_i2c1_gpio: i2c1-gpio {
 592                 mux {
 593                         groups = "gpio0_16_grp", "gpio0_17_grp";
 594                         function = "gpio0";
 595                 };
 596
 597                 conf {
 598                         groups = "gpio0_16_grp", "gpio0_17_grp";
 599                         slew-rate = <SLEW_RATE_SLOW>;
 600                         io-standard = <IO_STANDARD_LVCMOS18>;
 601                 };
 602         };
 603
 604         pinctrl_uart0_default: uart0-default {
 605                 mux {
 606                         groups = "uart0_4_grp";
 607                         function = "uart0";
 608                 };
 609
 610                 conf {
 611                         groups = "uart0_4_grp";
 612                         slew-rate = <SLEW_RATE_SLOW>;
 613                         io-standard = <IO_STANDARD_LVCMOS18>;
 614                 };
 615
 616                 conf-rx {
 617                         pins = "MIO18";
 618                         bias-high-impedance;
 619                 };
 620
 621                 conf-tx {
 622                         pins = "MIO19";
 623                         bias-disable;
 624                 };
 625         };
 626
 627         pinctrl_uart1_default: uart1-default {
 628                 mux {
 629                         groups = "uart1_5_grp";
 630                         function = "uart1";
 631                 };
 632
 633                 conf {
 634                         groups = "uart1_5_grp";
 635                         slew-rate = <SLEW_RATE_SLOW>;
 636                         io-standard = <IO_STANDARD_LVCMOS18>;
 637                 };
 638
 639                 conf-rx {
 640                         pins = "MIO21";
 641                         bias-high-impedance;
 642                 };
 643
 644                 conf-tx {
 645                         pins = "MIO20";
 646                         bias-disable;
 647                 };
 648         };
 649
 650         pinctrl_usb0_default: usb0-default {
 651                 mux {
 652                         groups = "usb0_0_grp";
 653                         function = "usb0";
 654                 };
 655
 656                 conf {
 657                         groups = "usb0_0_grp";
 658                         slew-rate = <SLEW_RATE_SLOW>;
 659                         io-standard = <IO_STANDARD_LVCMOS18>;
 660                 };
 661
 662                 conf-rx {
 663                         pins = "MIO52", "MIO53", "MIO55";
 664                         bias-high-impedance;
 665                 };
 666
 667                 conf-tx {
 668                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 669                                "MIO60", "MIO61", "MIO62", "MIO63";
 670                         bias-disable;
 671                 };
 672         };
 673
 674         pinctrl_gem3_default: gem3-default {
 675                 mux {
 676                         function = "ethernet3";
 677                         groups = "ethernet3_0_grp";
 678                 };
 679
 680                 conf {
 681                         groups = "ethernet3_0_grp";
 682                         slew-rate = <SLEW_RATE_SLOW>;
 683                         io-standard = <IO_STANDARD_LVCMOS18>;
 684                 };
 685
 686                 conf-rx {
 687                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 688                                                                         "MIO75";
 689                         bias-high-impedance;
 690                         low-power-disable;
 691                 };
 692
 693                 conf-tx {
 694                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 695                                                                         "MIO69";
 696                         bias-disable;
 697                         low-power-enable;
 698                 };
 699
 700                 mux-mdio {
 701                         function = "mdio3";
 702                         groups = "mdio3_0_grp";
 703                 };
 704
 705                 conf-mdio {
 706                         groups = "mdio3_0_grp";
 707                         slew-rate = <SLEW_RATE_SLOW>;
 708                         io-standard = <IO_STANDARD_LVCMOS18>;
 709                         bias-disable;
 710                 };
 711         };
 712
 713         pinctrl_can1_default: can1-default {
 714                 mux {
 715                         function = "can1";
 716                         groups = "can1_6_grp";
 717                 };
 718
 719                 conf {
 720                         groups = "can1_6_grp";
 721                         slew-rate = <SLEW_RATE_SLOW>;
 722                         io-standard = <IO_STANDARD_LVCMOS18>;
 723                 };
 724
 725                 conf-rx {
 726                         pins = "MIO25";
 727                         bias-high-impedance;
 728                 };
 729
 730                 conf-tx {
 731                         pins = "MIO24";
 732                         bias-disable;
 733                 };
 734         };
 735
 736         pinctrl_sdhci1_default: sdhci1-default {
 737                 mux {
 738                         groups = "sdio1_0_grp";
 739                         function = "sdio1";
 740                 };
 741
 742                 conf {
 743                         groups = "sdio1_0_grp";
 744                         slew-rate = <SLEW_RATE_SLOW>;
 745                         io-standard = <IO_STANDARD_LVCMOS18>;
 746                         bias-disable;
 747                 };
 748
 749                 mux-cd {
 750                         groups = "sdio1_0_cd_grp";
 751                         function = "sdio1_cd";
 752                 };
 753
 754                 conf-cd {
 755                         groups = "sdio1_0_cd_grp";
 756                         bias-high-impedance;
 757                         bias-pull-up;
 758                         slew-rate = <SLEW_RATE_SLOW>;
 759                         io-standard = <IO_STANDARD_LVCMOS18>;
 760                 };
 761
 762                 mux-wp {
 763                         groups = "sdio1_0_wp_grp";
 764                         function = "sdio1_wp";
 765                 };
 766
 767                 conf-wp {
 768                         groups = "sdio1_0_wp_grp";
 769                         bias-high-impedance;
 770                         bias-pull-up;
 771                         slew-rate = <SLEW_RATE_SLOW>;
 772                         io-standard = <IO_STANDARD_LVCMOS18>;
 773                 };
 774         };
 775
 776         pinctrl_gpio_default: gpio-default {
 777                 mux-sw {
 778                         function = "gpio0";
 779                         groups = "gpio0_22_grp", "gpio0_23_grp";
 780                 };
 781
 782                 conf-sw {
 783                         groups = "gpio0_22_grp", "gpio0_23_grp";
 784                         slew-rate = <SLEW_RATE_SLOW>;
 785                         io-standard = <IO_STANDARD_LVCMOS18>;
 786                 };
 787
 788                 mux-msp {
 789                         function = "gpio0";
 790                         groups = "gpio0_13_grp", "gpio0_38_grp";
 791                 };
 792
 793                 conf-msp {
 794                         groups = "gpio0_13_grp", "gpio0_38_grp";
 795                         slew-rate = <SLEW_RATE_SLOW>;
 796                         io-standard = <IO_STANDARD_LVCMOS18>;
 797                 };
 798
 799                 conf-pull-up {
 800                         pins = "MIO22", "MIO23";
 801                         bias-pull-up;
 802                 };
 803
 804                 conf-pull-none {
 805                         pins = "MIO13", "MIO38";
 806                         bias-disable;
 807                 };
 808         };
 809 };
 810
 811 &pcie {
 812         status = "okay";
 813 };
 814
 815 &qspi {
 816         status = "okay";
 817         is-dual = <1>;
 818         flash@0 {
 819                 compatible = "m25p80"; /* 32MB */
 820                 #address-cells = <1>;
 821                 #size-cells = <1>;
 822                 reg = <0x0>;
 823                 spi-tx-bus-width = <1>;
 824                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 825                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 826                 partition@qspi-fsbl-uboot { /* for testing purpose */
 827                         label = "qspi-fsbl-uboot";
 828                         reg = <0x0 0x100000>;
 829                 };
 830                 partition@qspi-linux { /* for testing purpose */
 831                         label = "qspi-linux";
 832                         reg = <0x100000 0x500000>;
 833                 };
 834                 partition@qspi-device-tree { /* for testing purpose */
 835                         label = "qspi-device-tree";
 836                         reg = <0x600000 0x20000>;
 837                 };
 838                 partition@qspi-rootfs { /* for testing purpose */
 839                         label = "qspi-rootfs";
 840                         reg = <0x620000 0x5E0000>;
 841                 };
 842         };
 843 };
 844
 845 &rtc {
 846         status = "okay";
 847 };
 848
 849 &sata {
 850         status = "okay";
 851         /* SATA OOB timing settings */
 852         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 853         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 854         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 855         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 856         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 857         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 858         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 859         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 860         phy-names = "sata-phy";
 861         phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 862 };
 863
 864 /* SD1 with level shifter */
 865 &sdhci1 {
 866         status = "okay";
 867         pinctrl-names = "default";
 868         pinctrl-0 = <&pinctrl_sdhci1_default>;
 869         no-1-8-v;       /* for 1.0 silicon */
 870         xlnx,mio_bank = <1>;
 871 };
 872
 873 &serdes {
 874         status = "okay";
 875 };
 876
 877 &uart0 {
 878         status = "okay";
 879         pinctrl-names = "default";
 880         pinctrl-0 = <&pinctrl_uart0_default>;
 881 };
 882
 883 &uart1 {
 884         status = "okay";
 885         pinctrl-names = "default";
 886         pinctrl-0 = <&pinctrl_uart1_default>;
 887 };
 888
 889 /* ULPI SMSC USB3320 */
 890 &usb0 {
 891         status = "okay";
 892         pinctrl-names = "default";
 893         pinctrl-0 = <&pinctrl_usb0_default>;
 894 };
 895
 896 &dwc3_0 {
 897         status = "okay";
 898         dr_mode = "host";
 899         snps,usb3_lpm_capable;
 900         phy-names = "usb3-phy";
 901         phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
 902         maximum-speed = "super-speed";
 903 };
 904
 905 &watchdog0 {
 906         status = "okay";
 907 };
 908
 909 &xilinx_ams {
 910         status = "okay";
 911 };
 912
 913 &ams_ps {
 914         status = "okay";
 915 };
 916
 917 &ams_pl {
 918         status = "okay";
 919 };
 920
 921 &xilinx_drm {
 922         status = "okay";
 923         clocks = <&si570_1>;
 924 };
 925
 926 &xlnx_dp {
 927         status = "okay";
 928 };
 929
 930 &xlnx_dp_sub {
 931         status = "okay";
 932         xlnx,vid-clk-pl;
 933 };
 934
 935 &xlnx_dp_snd_pcm0 {
 936         status = "okay";
 937 };
 938
 939 &xlnx_dp_snd_pcm1 {
 940         status = "okay";
 941 };
 942
 943 &xlnx_dp_snd_card {
 944         status = "okay";
 945 };
 946
 947 &xlnx_dp_snd_codec0 {
 948         status = "okay";
 949 };
 950
 951 &xlnx_dpdma {
 952         status = "okay";
 953 };