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   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
   4  */
   5 #ifndef _ASM_ARCH_CRU_RK3188_H
   6 #define _ASM_ARCH_CRU_RK3188_H
   7
   8 #define OSC_HZ          (24 * 1000 * 1000)
   9
  10 #define APLL_HZ         (1608 * 1000000)
  11 #define APLL_SAFE_HZ    (600 * 1000000)
  12 #define GPLL_HZ         (594 * 1000000)
  13 #define CPLL_HZ         (384 * 1000000)
  14
  15 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
  16 #define CPU_ACLK_HZ     297000000
  17 #define CPU_HCLK_HZ     148500000
  18 #define CPU_PCLK_HZ     74250000
  19 #define CPU_H2P_HZ      74250000
  20
  21 #define PERI_ACLK_HZ    148500000
  22 #define PERI_HCLK_HZ    148500000
  23 #define PERI_PCLK_HZ    74250000
  24
  25 /* Private data for the clock driver - used by rockchip_get_cru() */
  26 struct rk3188_clk_priv {
  27         struct rk3188_grf *grf;
  28         struct rk3188_cru *cru;
  29         ulong rate;
  30         bool has_bwadj;
  31 };
  32
  33 struct rk3188_cru {
  34         struct rk3188_pll {
  35                 u32 con0;
  36                 u32 con1;
  37                 u32 con2;
  38                 u32 con3;
  39         } pll[4];
  40         u32 cru_mode_con;
  41         u32 cru_clksel_con[35];
  42         u32 cru_clkgate_con[10];
  43         u32 reserved1[2];
  44         u32 cru_glb_srst_fst_value;
  45         u32 cru_glb_srst_snd_value;
  46         u32 reserved2[2];
  47         u32 cru_softrst_con[9];
  48         u32 cru_misc_con;
  49         u32 reserved3[2];
  50         u32 cru_glb_cnt_th;
  51 };
  52 check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
  53
  54 /* CRU_CLKSEL0_CON */
  55 enum {
  56         /* a9_core_div: core = core_src / (a9_core_div + 1) */
  57         A9_CORE_DIV_SHIFT       = 9,
  58         A9_CORE_DIV_MASK        = 0x1f,
  59         CORE_PLL_SHIFT          = 8,
  60         CORE_PLL_MASK           = 1,
  61         CORE_PLL_SELECT_APLL    = 0,
  62         CORE_PLL_SELECT_GPLL,
  63
  64         /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
  65         CORE_PERI_DIV_SHIFT     = 6,
  66         CORE_PERI_DIV_MASK      = 3,
  67
  68         /* aclk_cpu pll selection */
  69         CPU_ACLK_PLL_SHIFT      = 5,
  70         CPU_ACLK_PLL_MASK       = 1,
  71         CPU_ACLK_PLL_SELECT_APLL        = 0,
  72         CPU_ACLK_PLL_SELECT_GPLL,
  73
  74         /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
  75         A9_CPU_DIV_SHIFT        = 0,
  76         A9_CPU_DIV_MASK         = 0x1f,
  77 };
  78
  79 /* CRU_CLKSEL1_CON */
  80 enum {
  81         /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
  82         AHB2APB_DIV_SHIFT       = 14,
  83         AHB2APB_DIV_MASK        = 3,
  84
  85         /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
  86         CPU_PCLK_DIV_SHIFT      = 12,
  87         CPU_PCLK_DIV_MASK       = 3,
  88
  89         /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
  90         CPU_HCLK_DIV_SHIFT      = 8,
  91         CPU_HCLK_DIV_MASK       = 3,
  92
  93         /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
  94         CORE_ACLK_DIV_SHIFT     = 3,
  95         CORE_ACLK_DIV_MASK      = 7,
  96 };
  97
  98 /* CRU_CLKSEL10_CON */
  99 enum {
 100         PERI_SEL_PLL_MASK       = 1,
 101         PERI_SEL_PLL_SHIFT      = 15,
 102         PERI_SEL_CPLL           = 0,
 103         PERI_SEL_GPLL,
 104
 105         /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
 106         PERI_PCLK_DIV_SHIFT     = 12,
 107         PERI_PCLK_DIV_MASK      = 3,
 108
 109         /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
 110         PERI_HCLK_DIV_SHIFT     = 8,
 111         PERI_HCLK_DIV_MASK      = 3,
 112
 113         /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
 114         PERI_ACLK_DIV_SHIFT     = 0,
 115         PERI_ACLK_DIV_MASK      = 0x1f,
 116 };
 117 /* CRU_CLKSEL11_CON */
 118 enum {
 119         HSICPHY_DIV_SHIFT       = 8,
 120         HSICPHY_DIV_MASK        = 0x3f,
 121
 122         MMC0_DIV_SHIFT          = 0,
 123         MMC0_DIV_MASK           = 0x3f,
 124 };
 125
 126 /* CRU_CLKSEL12_CON */
 127 enum {
 128         UART_PLL_SHIFT          = 15,
 129         UART_PLL_MASK           = 1,
 130         UART_PLL_SELECT_GENERAL = 0,
 131         UART_PLL_SELECT_CODEC,
 132
 133         EMMC_DIV_SHIFT          = 8,
 134         EMMC_DIV_MASK           = 0x3f,
 135
 136         SDIO_DIV_SHIFT          = 0,
 137         SDIO_DIV_MASK           = 0x3f,
 138 };
 139
 140 /* CRU_CLKSEL25_CON */
 141 enum {
 142         SPI1_DIV_SHIFT          = 8,
 143         SPI1_DIV_MASK           = 0x7f,
 144
 145         SPI0_DIV_SHIFT          = 0,
 146         SPI0_DIV_MASK           = 0x7f,
 147 };
 148
 149 /* CRU_MODE_CON */
 150 enum {
 151         GPLL_MODE_SHIFT         = 12,
 152         GPLL_MODE_MASK          = 3,
 153         GPLL_MODE_SLOW          = 0,
 154         GPLL_MODE_NORMAL,
 155         GPLL_MODE_DEEP,
 156
 157         CPLL_MODE_SHIFT         = 8,
 158         CPLL_MODE_MASK          = 3,
 159         CPLL_MODE_SLOW          = 0,
 160         CPLL_MODE_NORMAL,
 161         CPLL_MODE_DEEP,
 162
 163         DPLL_MODE_SHIFT         = 4,
 164         DPLL_MODE_MASK          = 3,
 165         DPLL_MODE_SLOW          = 0,
 166         DPLL_MODE_NORMAL,
 167         DPLL_MODE_DEEP,
 168
 169         APLL_MODE_SHIFT         = 0,
 170         APLL_MODE_MASK          = 3,
 171         APLL_MODE_SLOW          = 0,
 172         APLL_MODE_NORMAL,
 173         APLL_MODE_DEEP,
 174 };
 175
 176 /* CRU_APLL_CON0 */
 177 enum {
 178         CLKR_SHIFT              = 8,
 179         CLKR_MASK               = 0x3f,
 180
 181         CLKOD_SHIFT             = 0,
 182         CLKOD_MASK              = 0x3f,
 183 };
 184
 185 /* CRU_APLL_CON1 */
 186 enum {
 187         CLKF_SHIFT              = 0,
 188         CLKF_MASK               = 0x1fff,
 189 };
 190
 191 #endif