1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
7 #ifndef _ASM_ARCH_GRF_RK3288_H
8 #define _ASM_ARCH_GRF_RK3288_H
10 struct rk3288_grf_gpio_lh {
54 struct rk3288_grf_gpio_lh gpio_sr[8];
106 u32 reserved1[(0x20-0x18)/4];
108 u32 reserved2[(0x40-0x28)/4];
110 u32 reserved3[(0x50-0x4c)/4];
127 u32 reserved4[(0x100-0x90)/4];
129 u32 reserved5[(0x120-0x108)/4];
133 /* GRF_GPIO1D_IOMUX */
156 /* GRF_GPIO2C_IOMUX */
169 /* GRF_GPIO3A_IOMUX */
174 GPIO3A7_FLASH0_DATA7,
180 GPIO3A6_FLASH0_DATA6,
186 GPIO3A5_FLASH0_DATA5,
192 GPIO3A4_FLASH0_DATA4,
198 GPIO3A3_FLASH0_DATA3,
204 GPIO3A2_FLASH0_DATA2,
210 GPIO3A1_FLASH0_DATA1,
216 GPIO3A0_FLASH0_DATA0,
220 /* GRF_GPIO3B_IOMUX */
264 /* GRF_GPIO3C_IOMUX */
276 GPIO3C1_EMMC_RSTNOUT,
285 /* GRF_GPIO3DL_IOMUX */
290 GPIO3D3_FLASH1_DATA3,
298 GPIO3D2_FLASH1_DATA2,
306 GPIO3DL1_FLASH1_DATA1,
314 GPIO3D0_FLASH1_DATA0,
320 /* GRF_GPIO3HL_IOMUX */
325 GPIO3D7_FLASH1_DATA7,
333 GPIO3D6_FLASH1_DATA6,
341 GPIO3D5_FLASH1_DATA5,
349 GPIO3D4_FLASH1_DATA4,
352 GPIO3D4_SDIO1_DETECTN,
355 /* GRF_GPIO4AL_IOMUX */
389 /* GRF_GPIO4AH_IOMUX */
397 GPIO4A7_SDIO1_CLKOUT,
423 /* GRF_GPIO4BL_IOMUX */
442 /* GRF_GPIO4C_IOMUX */
467 GPIO4C3_UART0BT_RTSN,
472 GPIO4C2_UART0BT_CTSN,
477 GPIO4C1_UART0BT_SOUT,
485 /* GRF_GPIO5B_IOMUX */
492 GPIO5B7_UART4EXP_SIN,
499 GPIO5B6_UART4EXP_SOUT,
506 GPIO5B5_UART4EXP_RTSN,
513 GPIO5B4_UART4EXP_CTSN,
518 GPIO5B3_UART1BB_RTSN,
524 GPIO5B2_UART1BB_CTSN,
530 GPIO5B1_UART1BB_SOUT,
540 /* GRF_GPIO5C_IOMUX */
564 /* GRF_GPIO6B_IOMUX */
574 GPIO6B2_I2C1AUDIO_SCL,
579 GPIO6B1_I2C1AUDIO_SDA,
587 /* GRF_GPIO6C_IOMUX */
592 GPIO6C6_SDMMC0_DECTN,
602 GPIO6C4_SDMMC0_CLKOUT,
608 GPIO6C3_SDMMC0_DATA3,
614 GPIO6C2_SDMMC0_DATA2,
620 GPIO6C1_SDMMC0_DATA1,
626 GPIO6C0_SDMMC0_DATA0,
630 /* GRF_GPIO7A_IOMUX */
635 GPIO7A7_UART3GPS_SIN,
637 GPIO7A7_HSADCT1_DATA0,
652 /* GRF_GPIO7B_IOMUX */
657 GPIO7B7_ISP_SHUTTERTRIG,
663 GPIO7B6_ISP_PRELIGHTTRIG,
669 GPIO7B5_ISP_FLASHTRIGOUT,
675 GPIO7B4_ISP_SHUTTEREN,
681 GPIO7B3_USB_DRVVBUS1,
687 GPIO7B2_UART3GPS_RTSN,
688 GPIO7B2_USB_DRVVBUS0,
693 GPIO7B1_UART3GPS_CTSN,
700 GPIO7B0_UART3GPS_SOUT,
702 GPIO7B0_HSADCT1_DATA1,
705 /* GRF_GPIO7CL_IOMUX */
710 GPIO7C3_I2C5HDMI_SDA,
711 GPIO7C3_EDPHDMII2C_SDA,
726 GPIO7C0_ISP_FLASHTRIGIN,
727 GPIO7C0_EDPHDMI_CECINOUTT1,
730 /* GRF_GPIO7CH_IOMUX */
735 GPIO7C7_UART2DBG_SOUT,
736 GPIO7C7_UART2DBG_SIROUT,
738 GPIO7C7_EDPHDMI_CECINOUT,
743 GPIO7C6_UART2DBG_SIN,
744 GPIO7C6_UART2DBG_SIRIN,
750 GPIO7C4_I2C5HDMI_SCL,
751 GPIO7C4_EDPHDMII2C_SCL,
754 /* GRF_GPIO8A_IOMUX */
773 GPIO8A5_I2C2SENSOR_SCL,
779 GPIO8A4_I2C2SENSOR_SDA,
806 /* GRF_GPIO8B_IOMUX */
823 PAUSE_MMC_PERI_SHIFT = 0xf,
824 PAUSE_MMC_PERI_MASK = 1,
826 PAUSE_EMEM_PERI_SHIFT = 0xe,
827 PAUSE_EMEM_PERI_MASK = 1,
829 PAUSE_USB_PERI_SHIFT = 0xd,
830 PAUSE_USB_PERI_MASK = 1,
832 GRF_FORCE_JTAG_SHIFT = 0xc,
833 GRF_FORCE_JTAG_MASK = 1,
835 GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
836 GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
838 GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
839 GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
841 DDR1_16BIT_EN_SHIFT = 9,
842 DDR1_16BIT_EN_MASK = 1,
844 DDR0_16BIT_EN_SHIFT = 8,
845 DDR0_16BIT_EN_MASK = 1,
849 VCODEC_SELECT_VEPU_ACLK = 0,
850 VCODEC_SELECT_VDPU_ACLK,
852 UPCTL1_C_ACTIVE_IN_SHIFT = 6,
853 UPCTL1_C_ACTIVE_IN_MASK = 1,
854 UPCTL1_C_ACTIVE_IN_MAY = 0,
855 UPCTL1_C_ACTIVE_IN_WILL,
857 UPCTL0_C_ACTIVE_IN_SHIFT = 5,
858 UPCTL0_C_ACTIVE_IN_MASK = 1,
859 UPCTL0_C_ACTIVE_IN_MAY = 0,
860 UPCTL0_C_ACTIVE_IN_WILL,
862 MSCH1_MAINDDR3_SHIFT = 4,
863 MSCH1_MAINDDR3_MASK = 1,
864 MSCH1_MAINDDR3_DDR3 = 1,
866 MSCH0_MAINDDR3_SHIFT = 3,
867 MSCH0_MAINDDR3_MASK = 1,
868 MSCH0_MAINDDR3_DDR3 = 1,
870 MSCH1_MAINPARTIALPOP_SHIFT = 2,
871 MSCH1_MAINPARTIALPOP_MASK = 1,
873 MSCH0_MAINPARTIALPOP_SHIFT = 1,
874 MSCH0_MAINPARTIALPOP_MASK = 1,
879 RK3288_RMII_MODE_SHIFT = 14,
880 RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT),
881 RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT),
883 RK3288_GMAC_CLK_SEL_SHIFT = 12,
884 RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
885 RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
886 RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
887 RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
889 RK3288_RMII_CLK_SEL_SHIFT = 11,
890 RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT),
891 RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
892 RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
894 GMAC_SPEED_SHIFT = 0xa,
899 GMAC_FLOWCTRL_SHIFT = 0x9,
900 GMAC_FLOWCTRL_MASK = 1,
902 RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
903 RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
904 RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
905 RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
907 HOST_REMAP_SHIFT = 0x5,
913 UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
914 UPCTL1_LPDDR3_ODT_EN_MASK = 1,
915 UPCTL1_LPDDR3_ODT_EN_ODT = 1,
917 UPCTL1_BST_DIABLE_SHIFT = 0xc,
918 UPCTL1_BST_DIABLE_MASK = 1,
919 UPCTL1_BST_DIABLE_DISABLE = 1,
921 LPDDR3_EN1_SHIFT = 0xb,
923 LPDDR3_EN1_LPDDR3 = 1,
925 UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
926 UPCTL0_LPDDR3_ODT_EN_MASK = 1,
927 UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
929 UPCTL0_BST_DIABLE_SHIFT = 9,
930 UPCTL0_BST_DIABLE_MASK = 1,
931 UPCTL0_BST_DIABLE_DISABLE = 1,
933 LPDDR3_EN0_SHIFT = 8,
935 LPDDR3_EN0_LPDDR3 = 1,
937 GRF_POC_FLASH0_CTRL_SHIFT = 7,
938 GRF_POC_FLASH0_CTRL_MASK = 1,
939 GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
940 GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
942 SIMCARD_MUX_SHIFT = 6,
943 SIMCARD_MUX_MASK = 1,
944 SIMCARD_MUX_USE_A = 1,
945 SIMCARD_MUX_USE_B = 0,
947 GRF_SPDIF_2CH_EN_SHIFT = 1,
948 GRF_SPDIF_2CH_EN_MASK = 1,
949 GRF_SPDIF_2CH_EN_8CH = 0,
950 GRF_SPDIF_2CH_EN_2CH,
960 RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
961 RK3288_RXCLK_DLY_ENA_GMAC_MASK =
962 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
963 RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
964 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
965 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
967 RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
968 RK3288_TXCLK_DLY_ENA_GMAC_MASK =
969 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
970 RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
971 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
972 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
974 RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
975 RK3288_CLK_RX_DL_CFG_GMAC_MASK =
976 (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
978 RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
979 RK3288_CLK_TX_DL_CFG_GMAC_MASK =
980 (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
985 RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
986 RK3288_HDMI_EDP_SEL_MASK =
987 1 << RK3288_HDMI_EDP_SEL_SHIFT,
988 RK3288_HDMI_EDP_SEL_EDP = 0,
989 RK3288_HDMI_EDP_SEL_HDMI,
991 RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
992 RK3288_DSI0_DPICOLORM_MASK =
993 1 << RK3288_DSI0_DPICOLORM_SHIFT,
995 RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
996 RK3288_DSI0_DPISHUTDN_MASK =
997 1 << RK3288_DSI0_DPISHUTDN_SHIFT,
999 RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
1000 RK3288_DSI0_LCDC_SEL_MASK =
1001 1 << RK3288_DSI0_LCDC_SEL_SHIFT,
1002 RK3288_DSI0_LCDC_SEL_BIG = 0,
1003 RK3288_DSI0_LCDC_SEL_LIT = 1,
1005 RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
1006 RK3288_EDP_LCDC_SEL_MASK =
1007 1 << RK3288_EDP_LCDC_SEL_SHIFT,
1008 RK3288_EDP_LCDC_SEL_BIG = 0,
1009 RK3288_EDP_LCDC_SEL_LIT = 1,
1011 RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
1012 RK3288_HDMI_LCDC_SEL_MASK =
1013 1 << RK3288_HDMI_LCDC_SEL_SHIFT,
1014 RK3288_HDMI_LCDC_SEL_BIG = 0,
1015 RK3288_HDMI_LCDC_SEL_LIT = 1,
1017 RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
1018 RK3288_LVDS_LCDC_SEL_MASK =
1019 1 << RK3288_LVDS_LCDC_SEL_SHIFT,
1020 RK3288_LVDS_LCDC_SEL_BIG = 0,
1021 RK3288_LVDS_LCDC_SEL_LIT = 1,
1024 /* RK3288_SOC_CON8 */
1026 RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
1027 RK3288_DPHY_TX0_RXMODE_MASK =
1028 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
1029 RK3288_DPHY_TX0_RXMODE_EN = 0xf,
1030 RK3288_DPHY_TX0_RXMODE_DIS = 0,
1032 RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
1033 RK3288_DPHY_TX0_TXSTOPMODE_MASK =
1034 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
1035 RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
1036 RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
1038 RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
1039 RK3288_DPHY_TX0_TURNREQUEST_MASK =
1040 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
1041 RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
1042 RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
1045 /* GPIO Bias settings */
1053 #define GPIO_BIAS_MASK 0x3
1054 #define GPIO_BIAS_SHIFT(x) ((x) * 2)
1057 GPIO_PULL_NORMAL = 0,
1063 #define GPIO_PULL_MASK 0x3
1064 #define GPIO_PULL_SHIFT(x) ((x) * 2)