1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 Google, Inc
5 * Copyright 2014 Rockchip Inc.
8 #ifndef _ASM_ARCH_RK3288_SDRAM_H__
9 #define _ASM_ARCH_RK3288_SDRAM_H__
17 struct rk3288_sdram_channel {
19 * bit width in address, eg:
20 * 8 banks using 3 bit to address,
21 * 2 cs using 1 bit to address.
31 #if CONFIG_IS_ENABLED(OF_PLATDATA)
33 * For of-platdata, which would otherwise convert this into two
34 * byte-swapped integers. With a size of 9 bytes, this struct will
35 * appear in of-platdata as a byte array.
37 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
43 struct rk3288_sdram_pctl_timing {
79 check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
81 struct rk3288_sdram_phy_timing {
88 struct rk3288_base_params {
95 * DDR Stride is address mapping for DRAM space
96 * Stride Ch 0 range Ch1 range Total
97 * 0x00 0-256MB 256MB-512MB 512MB
98 * 0x05 0-1GB 0-1GB 1GB
99 * 0x09 0-2GB 0-2GB 2GB
100 * 0x0d 0-4GB 0-4GB 4GB
102 * 0x1a 0-4GB 4GB-8GB 8GB