1 // SPDX-License-Identifier: GPL-2.0+
3 * Power and Sleep Controller (PSC) functions.
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
7 * Copyright (C) 2004 Texas Instruments.
11 #include <asm/arch/hardware.h>
15 * The PSC manages three inputs to a "module" which may be a peripheral or
16 * CPU. Those inputs are the module's: clock; reset signal; and sometimes
17 * its power domain. For our purposes, we only care whether clock and power
18 * are active, and the module is out of reset.
20 * DaVinci chips may include two separate power domains: "Always On" and "DSP".
21 * Chips without a DSP generally have only one domain.
23 * The "Always On" power domain is always on when the chip is on, and is
24 * powered by the VDD pins (on DM644X). The majority of DaVinci modules
25 * lie within the "Always On" power domain.
27 * A separate domain called the "DSP" domain houses the C64x+ and other video
28 * hardware such as VICP. In some chips, the "DSP" domain is not always on.
29 * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
32 /* Works on Always On power domain only (no PD argument) */
33 static void lpsc_transition(unsigned int id, unsigned int state)
35 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
36 #ifdef CONFIG_SOC_DA8XX
37 struct davinci_psc_regs *psc_regs;
40 #ifndef CONFIG_SOC_DA8XX
41 if (id >= DAVINCI_LPSC_GEM)
42 return; /* Don't work on DSP Power Domain */
44 mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
45 mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
46 ptstat = REG_P(PSC_PTSTAT);
47 ptcmd = REG_P(PSC_PTCMD);
49 if (id < DAVINCI_LPSC_PSC1_BASE) {
50 if (id >= PSC_PSC0_MODULE_ID_CNT)
52 psc_regs = davinci_psc0_regs;
53 mdstat = &psc_regs->psc0.mdstat[id];
54 mdctl = &psc_regs->psc0.mdctl[id];
56 id -= DAVINCI_LPSC_PSC1_BASE;
57 if (id >= PSC_PSC1_MODULE_ID_CNT)
59 psc_regs = davinci_psc1_regs;
60 mdstat = &psc_regs->psc1.mdstat[id];
61 mdctl = &psc_regs->psc1.mdctl[id];
63 ptstat = &psc_regs->ptstat;
64 ptcmd = &psc_regs->ptcmd;
67 while (readl(ptstat) & 0x01)
70 if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
71 return; /* Already in that state */
73 writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
76 #ifdef CONFIG_SOC_DM644X
77 /* Special treatment for some modules as for sprue14 p.7.4.2 */
78 case DAVINCI_LPSC_VPSSSLV:
79 case DAVINCI_LPSC_EMAC:
80 case DAVINCI_LPSC_EMAC_WRAPPER:
81 case DAVINCI_LPSC_MDIO:
82 case DAVINCI_LPSC_USB:
83 case DAVINCI_LPSC_ATA:
84 case DAVINCI_LPSC_VLYNQ:
85 case DAVINCI_LPSC_UHPI:
86 case DAVINCI_LPSC_DDR_EMIF:
87 case DAVINCI_LPSC_AEMIF:
88 case DAVINCI_LPSC_MMC_SD:
89 case DAVINCI_LPSC_MEMSTICK:
90 case DAVINCI_LPSC_McBSP:
91 case DAVINCI_LPSC_GPIO:
92 writel(readl(mdctl) | 0x200, mdctl);
99 while (readl(ptstat) & 0x01)
101 while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
105 void lpsc_on(unsigned int id)
107 lpsc_transition(id, 0x03);
110 void lpsc_syncreset(unsigned int id)
112 lpsc_transition(id, 0x01);
115 void lpsc_disable(unsigned int id)
117 lpsc_transition(id, 0x0);
120 /* Not all DaVinci chips have a DSP power domain. */
121 #ifdef CONFIG_SOC_DM644X
123 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
124 #if !defined(CONFIG_SYS_USE_DSPLINK)
129 if (REG(PSC_PDSTAT1) & 0x1f)
130 return; /* Already on */
132 REG(PSC_GBLCTL) |= 0x01;
133 REG(PSC_PDCTL1) |= 0x01;
134 REG(PSC_PDCTL1) &= ~0x100;
135 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
136 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
137 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
138 REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
139 REG(PSC_PTCMD) = 0x02;
141 for (i = 0; i < 100; i++) {
142 if (REG(PSC_EPCPR) & 0x02)
146 REG(PSC_CHP_SHRTSW) = 0x01;
147 REG(PSC_PDCTL1) |= 0x100;
148 REG(PSC_EPCCR) = 0x02;
150 for (i = 0; i < 100; i++) {
151 if (!(REG(PSC_PTSTAT) & 0x02))
155 REG(PSC_GBLCTL) &= ~0x1f;
157 #endif /* CONFIG_SYS_USE_DSPLINK */
159 #endif /* have a DSP */