1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock setup for SMDK5250 board based on EXYNOS5
5 * Copyright (C) 2012 Samsung Electronics
11 #include <asm/arch/clk.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/spl.h>
14 #include <asm/arch/dwmmc.h>
16 #include "clock_init.h"
17 #include "common_setup.h"
18 #include "exynos5_setup.h"
20 #define FSYS1_MMC0_DIV_MASK 0xff0f
21 #define FSYS1_MMC0_DIV_VAL 0x0701
23 struct arm_clk_ratios arm_clk_ratios[] = {
24 #ifdef CONFIG_EXYNOS5420
34 .pclk_dbg_ratio = 0x6,
51 .pclk_dbg_ratio = 0x1,
66 .pclk_dbg_ratio = 0x1,
81 .pclk_dbg_ratio = 0x1,
96 .pclk_dbg_ratio = 0x1,
103 .arm_freq_mhz = 1400,
111 .pclk_dbg_ratio = 0x1,
118 .arm_freq_mhz = 1700,
126 .pclk_dbg_ratio = 0x1,
136 struct mem_timings mem_timings[] = {
137 #ifdef CONFIG_EXYNOS5420
139 .mem_manuf = MEM_MANUF_SAMSUNG,
140 .mem_type = DDR_MODE_DDR3,
141 .frequency_mhz = 800,
185 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
188 .timing_ref = 0x000000bb,
189 .timing_row = 0x6836650f,
190 .timing_data = 0x3630580b,
191 .timing_power = 0x41000a26,
192 .phy0_dqs = 0x08080808,
193 .phy1_dqs = 0x08080808,
194 .phy0_dq = 0x08080808,
195 .phy1_dq = 0x08080808,
198 .phy0_pulld_dqs = 0xf,
199 .phy1_pulld_dqs = 0xf,
201 .lpddr3_ctrl_phy_reset = 0x1,
202 .ctrl_start_point = 0x10,
224 * Dynamic Clock: Always Running
225 * Memory Burst length: 8
227 * Memory Bus width: 32 bit
229 * Additional Latancy for PLL: 0 Cycle
231 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
232 DMC_MEMCONTROL_DPWRDN_DISABLE |
233 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
234 DMC_MEMCONTROL_TP_DISABLE |
235 DMC_MEMCONTROL_DSREF_DISABLE |
236 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
237 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
238 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
239 DMC_MEMCONTROL_NUM_CHIP_1 |
240 DMC_MEMCONTROL_BL_8 |
241 DMC_MEMCONTROL_PZQ_DISABLE |
242 DMC_MEMCONTROL_MRR_BYTE_7_0,
243 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
244 DMC_MEMCONFIGX_CHIP_COL_10 |
245 DMC_MEMCONFIGX_CHIP_ROW_15 |
246 DMC_MEMCONFIGX_CHIP_BANK_8,
247 .prechconfig_tp_cnt = 0xff,
250 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
251 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
252 DMC_CONCONTROL_RD_FETCH_DISABLE |
253 DMC_CONCONTROL_EMPTY_DISABLE |
254 DMC_CONCONTROL_AREF_EN_DISABLE |
255 DMC_CONCONTROL_IO_PD_CON_DISABLE,
257 .chips_per_channel = 1,
258 .chips_to_configure = 1,
260 .gate_leveling_enable = 1,
261 .read_leveling_enable = 0,
265 .mem_manuf = MEM_MANUF_ELPIDA,
266 .mem_type = DDR_MODE_DDR3,
267 .frequency_mhz = 800,
287 .pclk_cdrex_ratio = 0x5,
289 0x00020018, 0x00030000, 0x00010042, 0x00000d70
291 .timing_ref = 0x000000bb,
292 .timing_row = 0x8c36650e,
293 .timing_data = 0x3630580b,
294 .timing_power = 0x41000a44,
295 .phy0_dqs = 0x08080808,
296 .phy1_dqs = 0x08080808,
297 .phy0_dq = 0x08080808,
298 .phy1_dq = 0x08080808,
301 .phy0_pulld_dqs = 0xf,
302 .phy1_pulld_dqs = 0xf,
304 .lpddr3_ctrl_phy_reset = 0x1,
305 .ctrl_start_point = 0x10,
327 * Dynamic Clock: Always Running
328 * Memory Burst length: 8
330 * Memory Bus width: 32 bit
332 * Additional Latancy for PLL: 0 Cycle
334 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
335 DMC_MEMCONTROL_DPWRDN_DISABLE |
336 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
337 DMC_MEMCONTROL_TP_DISABLE |
338 DMC_MEMCONTROL_DSREF_ENABLE |
339 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
340 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
341 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
342 DMC_MEMCONTROL_NUM_CHIP_1 |
343 DMC_MEMCONTROL_BL_8 |
344 DMC_MEMCONTROL_PZQ_DISABLE |
345 DMC_MEMCONTROL_MRR_BYTE_7_0,
346 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
347 DMC_MEMCONFIGX_CHIP_COL_10 |
348 DMC_MEMCONFIGX_CHIP_ROW_15 |
349 DMC_MEMCONFIGX_CHIP_BANK_8,
350 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
351 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
352 .prechconfig_tp_cnt = 0xff,
355 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
356 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
357 DMC_CONCONTROL_RD_FETCH_DISABLE |
358 DMC_CONCONTROL_EMPTY_DISABLE |
359 DMC_CONCONTROL_AREF_EN_DISABLE |
360 DMC_CONCONTROL_IO_PD_CON_DISABLE,
362 .chips_per_channel = 2,
363 .chips_to_configure = 1,
365 .impedance = IMP_OUTPUT_DRV_30_OHM,
366 .gate_leveling_enable = 0,
368 .mem_manuf = MEM_MANUF_SAMSUNG,
369 .mem_type = DDR_MODE_DDR3,
370 .frequency_mhz = 800,
390 .pclk_cdrex_ratio = 0x5,
392 0x00020018, 0x00030000, 0x00010000, 0x00000d70
394 .timing_ref = 0x000000bb,
395 .timing_row = 0x8c36650e,
396 .timing_data = 0x3630580b,
397 .timing_power = 0x41000a44,
398 .phy0_dqs = 0x08080808,
399 .phy1_dqs = 0x08080808,
400 .phy0_dq = 0x08080808,
401 .phy1_dq = 0x08080808,
404 .phy0_pulld_dqs = 0xf,
405 .phy1_pulld_dqs = 0xf,
407 .lpddr3_ctrl_phy_reset = 0x1,
408 .ctrl_start_point = 0x10,
430 * Dynamic Clock: Always Running
431 * Memory Burst length: 8
433 * Memory Bus width: 32 bit
435 * Additional Latancy for PLL: 0 Cycle
437 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
438 DMC_MEMCONTROL_DPWRDN_DISABLE |
439 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
440 DMC_MEMCONTROL_TP_DISABLE |
441 DMC_MEMCONTROL_DSREF_ENABLE |
442 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
443 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
444 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
445 DMC_MEMCONTROL_NUM_CHIP_1 |
446 DMC_MEMCONTROL_BL_8 |
447 DMC_MEMCONTROL_PZQ_DISABLE |
448 DMC_MEMCONTROL_MRR_BYTE_7_0,
449 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
450 DMC_MEMCONFIGX_CHIP_COL_10 |
451 DMC_MEMCONFIGX_CHIP_ROW_15 |
452 DMC_MEMCONFIGX_CHIP_BANK_8,
453 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
454 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
455 .prechconfig_tp_cnt = 0xff,
458 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
459 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
460 DMC_CONCONTROL_RD_FETCH_DISABLE |
461 DMC_CONCONTROL_EMPTY_DISABLE |
462 DMC_CONCONTROL_AREF_EN_DISABLE |
463 DMC_CONCONTROL_IO_PD_CON_DISABLE,
465 .chips_per_channel = 2,
466 .chips_to_configure = 1,
468 .impedance = IMP_OUTPUT_DRV_40_OHM,
469 .gate_leveling_enable = 1,
475 * Get the required memory type and speed (SPL version).
477 * In SPL we have no device tree, so we use the machine parameters
479 * @param mem_type Returns memory type
480 * @param frequency_mhz Returns memory speed in MHz
481 * @param arm_freq Returns ARM clock speed in MHz
482 * @param mem_manuf Return Memory Manufacturer name
484 static void clock_get_mem_selection(enum ddr_mode *mem_type,
485 unsigned *frequency_mhz, unsigned *arm_freq,
486 enum mem_manuf *mem_manuf)
488 struct spl_machine_param *params;
490 params = spl_get_machine_params();
491 *mem_type = params->mem_type;
492 *frequency_mhz = params->frequency_mhz;
493 *arm_freq = params->arm_freq_mhz;
494 *mem_manuf = params->mem_manuf;
497 /* Get the ratios for setting ARM clock */
498 struct arm_clk_ratios *get_arm_ratios(void)
500 struct arm_clk_ratios *arm_ratio;
501 enum ddr_mode mem_type;
502 enum mem_manuf mem_manuf;
503 unsigned frequency_mhz, arm_freq;
506 clock_get_mem_selection(&mem_type, &frequency_mhz,
507 &arm_freq, &mem_manuf);
509 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
511 if (arm_ratio->arm_freq_mhz == arm_freq)
515 /* will hang if failed to find clock ratio */
522 struct mem_timings *clock_get_mem_timings(void)
524 struct mem_timings *mem;
525 enum ddr_mode mem_type;
526 enum mem_manuf mem_manuf;
527 unsigned frequency_mhz, arm_freq;
530 clock_get_mem_selection(&mem_type, &frequency_mhz,
531 &arm_freq, &mem_manuf);
532 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
534 if (mem->mem_type == mem_type &&
535 mem->frequency_mhz == frequency_mhz &&
536 mem->mem_manuf == mem_manuf)
540 /* will hang if failed to find memory timings */
547 static void exynos5250_system_clock_init(void)
549 struct exynos5_clock *clk =
550 (struct exynos5_clock *)samsung_get_base_clock();
551 struct mem_timings *mem;
552 struct arm_clk_ratios *arm_clk_ratio;
555 mem = clock_get_mem_timings();
556 arm_clk_ratio = get_arm_ratios();
558 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
560 val = readl(&clk->mux_stat_cpu);
561 } while ((val | MUX_APLL_SEL_MASK) != val);
563 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
565 val = readl(&clk->mux_stat_core1);
566 } while ((val | MUX_MPLL_SEL_MASK) != val);
568 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
569 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
570 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
571 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
572 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
575 val = readl(&clk->mux_stat_top2);
576 } while ((val | tmp) != val);
578 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
580 val = readl(&clk->mux_stat_cdrex);
581 } while ((val | MUX_BPLL_SEL_MASK) != val);
584 writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
585 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
586 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
587 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
588 writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
589 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
590 writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
592 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
594 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
596 val = readl(&clk->mux_stat_cpu);
597 } while ((val | HPM_SEL_SCLK_MPLL) != val);
599 val = arm_clk_ratio->arm2_ratio << 28
600 | arm_clk_ratio->apll_ratio << 24
601 | arm_clk_ratio->pclk_dbg_ratio << 20
602 | arm_clk_ratio->atb_ratio << 16
603 | arm_clk_ratio->periph_ratio << 12
604 | arm_clk_ratio->acp_ratio << 8
605 | arm_clk_ratio->cpud_ratio << 4
606 | arm_clk_ratio->arm_ratio;
607 writel(val, &clk->div_cpu0);
609 val = readl(&clk->div_stat_cpu0);
612 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
614 val = readl(&clk->div_stat_cpu1);
618 writel(APLL_CON1_VAL, &clk->apll_con1);
619 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
620 arm_clk_ratio->apll_sdiv);
621 writel(val, &clk->apll_con0);
622 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
626 writel(MPLL_CON1_VAL, &clk->mpll_con1);
627 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
628 writel(val, &clk->mpll_con0);
629 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
633 writel(BPLL_CON1_VAL, &clk->bpll_con1);
634 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
635 writel(val, &clk->bpll_con0);
636 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
640 writel(CPLL_CON1_VAL, &clk->cpll_con1);
641 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
642 writel(val, &clk->cpll_con0);
643 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
647 writel(GPLL_CON1_VAL, &clk->gpll_con1);
648 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
649 writel(val, &clk->gpll_con0);
650 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
654 writel(EPLL_CON2_VAL, &clk->epll_con2);
655 writel(EPLL_CON1_VAL, &clk->epll_con1);
656 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
657 writel(val, &clk->epll_con0);
658 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
662 writel(VPLL_CON2_VAL, &clk->vpll_con2);
663 writel(VPLL_CON1_VAL, &clk->vpll_con1);
664 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
665 writel(val, &clk->vpll_con0);
666 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
669 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
670 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
671 while (readl(&clk->div_stat_core0) != 0)
674 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
675 while (readl(&clk->div_stat_core1) != 0)
678 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
679 while (readl(&clk->div_stat_sysrgt) != 0)
682 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
683 while (readl(&clk->div_stat_acp) != 0)
686 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
687 while (readl(&clk->div_stat_syslft) != 0)
690 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
691 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
692 writel(TOP2_VAL, &clk->src_top2);
693 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
695 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
696 while (readl(&clk->div_stat_top0))
699 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
700 while (readl(&clk->div_stat_top1))
703 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
705 val = readl(&clk->mux_stat_lex);
706 if (val == (val | 1))
710 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
711 while (readl(&clk->div_stat_lex))
714 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
715 while (readl(&clk->div_stat_r0x))
718 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
719 while (readl(&clk->div_stat_r0x))
722 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
723 while (readl(&clk->div_stat_r1x))
726 writel(CLK_REG_DISABLE, &clk->src_cdrex);
728 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
729 while (readl(&clk->div_stat_cdrex))
732 val = readl(&clk->src_cpu);
733 val |= CLK_SRC_CPU_VAL;
734 writel(val, &clk->src_cpu);
736 val = readl(&clk->src_top2);
737 val |= CLK_SRC_TOP2_VAL;
738 writel(val, &clk->src_top2);
740 val = readl(&clk->src_core1);
741 val |= CLK_SRC_CORE1_VAL;
742 writel(val, &clk->src_core1);
744 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
745 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
746 while (readl(&clk->div_stat_fsys0))
749 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
750 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
751 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
752 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
753 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
754 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
755 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
756 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
758 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
759 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
761 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
762 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
763 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
764 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
766 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
767 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
769 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
770 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
772 /* FIMD1 SRC CLK SELECTION */
773 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
775 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
776 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
777 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
778 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
779 writel(val, &clk->div_fsys2);
782 static void exynos5420_system_clock_init(void)
784 struct exynos5420_clock *clk =
785 (struct exynos5420_clock *)samsung_get_base_clock();
786 struct mem_timings *mem;
787 struct arm_clk_ratios *arm_clk_ratio;
790 mem = clock_get_mem_timings();
791 arm_clk_ratio = get_arm_ratios();
794 writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
795 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
796 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
797 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
798 writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
799 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
800 writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
801 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
802 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
803 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
804 writel(mem->rpll_pdiv * PLL_X_LOCK_FACTOR, &clk->rpll_lock);
806 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
808 writel(0, &clk->src_top6);
810 writel(0, &clk->src_cdrex);
811 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
812 writel(HPM_RATIO, &clk->div_cpu1);
813 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
815 /* switch A15 clock source to OSC clock before changing APLL */
816 clrbits_le32(&clk->src_cpu, APLL_FOUT);
819 writel(APLL_CON1_VAL, &clk->apll_con1);
820 val = set_pll(arm_clk_ratio->apll_mdiv,
821 arm_clk_ratio->apll_pdiv,
822 arm_clk_ratio->apll_sdiv);
823 writel(val, &clk->apll_con0);
824 while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
827 /* now it is safe to switch to APLL */
828 setbits_le32(&clk->src_cpu, APLL_FOUT);
830 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
831 writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
833 /* switch A7 clock source to OSC clock before changing KPLL */
834 clrbits_le32(&clk->src_kfc, KPLL_FOUT);
837 writel(KPLL_CON1_VAL, &clk->kpll_con1);
838 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
839 writel(val, &clk->kpll_con0);
840 while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
843 /* now it is safe to switch to KPLL */
844 setbits_le32(&clk->src_kfc, KPLL_FOUT);
847 writel(MPLL_CON1_VAL, &clk->mpll_con1);
848 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
849 writel(val, &clk->mpll_con0);
850 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
854 writel(DPLL_CON1_VAL, &clk->dpll_con1);
855 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
856 writel(val, &clk->dpll_con0);
857 while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
861 writel(EPLL_CON2_VAL, &clk->epll_con2);
862 writel(EPLL_CON1_VAL, &clk->epll_con1);
863 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
864 writel(val, &clk->epll_con0);
865 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
869 writel(CPLL_CON1_VAL, &clk->cpll_con1);
870 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
871 writel(val, &clk->cpll_con0);
872 while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
876 writel(IPLL_CON1_VAL, &clk->ipll_con1);
877 val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
878 writel(val, &clk->ipll_con0);
879 while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
883 writel(VPLL_CON1_VAL, &clk->vpll_con1);
884 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
885 writel(val, &clk->vpll_con0);
886 while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
890 writel(BPLL_CON1_VAL, &clk->bpll_con1);
891 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
892 writel(val, &clk->bpll_con0);
893 while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
897 writel(SPLL_CON1_VAL, &clk->spll_con1);
898 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
899 writel(val, &clk->spll_con0);
900 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
904 writel(RPLL_CON2_VAL, &clk->rpll_con2);
905 writel(RPLL_CON1_VAL, &clk->rpll_con1);
906 val = set_pll(mem->rpll_mdiv, mem->rpll_pdiv, mem->rpll_sdiv);
907 writel(val, &clk->rpll_con0);
908 while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
911 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
912 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
914 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
915 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
916 writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
917 writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
919 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
920 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
921 writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
923 writel(0, &clk->src_top10);
924 writel(0, &clk->src_top11);
925 writel(0, &clk->src_top12);
927 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
928 writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
929 writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
931 /* DISP1 BLK CLK SELECTION */
932 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
933 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
936 writel(AUDIO0_SEL_EPLL, &clk->src_mau);
937 writel(DIV_MAU_VAL, &clk->div_mau);
940 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
941 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
942 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
943 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
945 writel(CLK_SRC_ISP_VAL, &clk->src_isp);
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
947 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
949 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
950 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
952 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
953 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
954 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
955 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
956 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
958 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
960 writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
961 writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
962 writel(CLK_DIV_G2D, &clk->div_g2d);
964 writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
965 writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
966 writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
969 void system_clock_init(void)
971 if (proid_is_exynos5420() || proid_is_exynos5422())
972 exynos5420_system_clock_init();
974 exynos5250_system_clock_init();
977 void clock_init_dp_clock(void)
979 struct exynos5_clock *clk =
980 (struct exynos5_clock *)samsung_get_base_clock();
982 /* DP clock enable */
983 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
985 /* We run DP at 267 Mhz */
986 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
990 * Set clock divisor value for booting from EMMC.
991 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
993 void emmc_boot_clk_div_set(void)
995 struct exynos5_clock *clk =
996 (struct exynos5_clock *)samsung_get_base_clock();
997 unsigned int div_mmc;
999 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
1000 div_mmc |= FSYS1_MMC0_DIV_VAL;
1001 writel(div_mmc, (unsigned int) &clk->div_fsys1);
projects / u-boot / blob