git.sur5r.net Git - u-boot/blob - arch/arm/mach-imx/cache.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/armv7.h>
   8 #include <asm/pl310.h>
   9 #include <asm/io.h>
  10 #include <asm/mach-imx/sys_proto.h>
  11
  12 #ifndef CONFIG_SYS_DCACHE_OFF
  13 void enable_caches(void)
  14 {
  15 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  16         enum dcache_option option = DCACHE_WRITETHROUGH;
  17 #else
  18         enum dcache_option option = DCACHE_WRITEBACK;
  19 #endif
  20         /* Avoid random hang when download by usb */
  21         invalidate_dcache_all();
  22
  23         /* Enable D-cache. I-cache is already enabled in start.S */
  24         dcache_enable();
  25
  26         /* Enable caching on OCRAM and ROM */
  27         mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
  28                                         ROMCP_ARB_END_ADDR,
  29                                         option);
  30         mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
  31                                         IRAM_SIZE,
  32                                         option);
  33 }
  34 #endif
  35
  36 #ifndef CONFIG_SYS_L2CACHE_OFF
  37 #ifdef CONFIG_SYS_L2_PL310
  38 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
  39 void v7_outer_cache_enable(void)
  40 {
  41         struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
  42         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  43         unsigned int val;
  44
  45
  46         /*
  47          * Must disable the L2 before changing the latency parameters
  48          * and auxiliary control register.
  49          */
  50         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  51
  52         /*
  53          * Set bit 22 in the auxiliary control register. If this bit
  54          * is cleared, PL310 treats Normal Shared Non-cacheable
  55          * accesses as Cacheable no-allocate.
  56          */
  57         setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
  58
  59         if (is_mx6sl() || is_mx6sll()) {
  60                 val = readl(&iomux->gpr[11]);
  61                 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
  62                         /* L2 cache configured as OCRAM, reset it */
  63                         val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
  64                         writel(val, &iomux->gpr[11]);
  65                 }
  66         }
  67
  68         writel(0x132, &pl310->pl310_tag_latency_ctrl);
  69         writel(0x132, &pl310->pl310_data_latency_ctrl);
  70
  71         val = readl(&pl310->pl310_prefetch_ctrl);
  72
  73         /* Turn on the L2 I/D prefetch */
  74         val |= 0x30000000;
  75
  76         /*
  77          * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
  78          * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
  79          * But according to ARM PL310 errata: 752271
  80          * ID: 752271: Double linefill feature can cause data corruption
  81          * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
  82          * Workaround: The only workaround to this erratum is to disable the
  83          * double linefill feature. This is the default behavior.
  84          */
  85
  86 #ifndef CONFIG_MX6Q
  87         val |= 0x40800000;
  88 #endif
  89         writel(val, &pl310->pl310_prefetch_ctrl);
  90
  91         val = readl(&pl310->pl310_power_ctrl);
  92         val |= L2X0_DYNAMIC_CLK_GATING_EN;
  93         val |= L2X0_STNDBY_MODE_EN;
  94         writel(val, &pl310->pl310_power_ctrl);
  95
  96         setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  97 }
  98
  99 void v7_outer_cache_disable(void)
 100 {
 101         struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
 102
 103         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 104 }
 105 #endif /* !CONFIG_SYS_L2_PL310 */
 106 #endif /* !CONFIG_SYS_L2CACHE_OFF */