git.sur5r.net Git - u-boot/blob - arch/arm/mach-imx/mx6/opos6ul.c

   1 /*
   2  * Copyright (C) 2017 Armadeus Systems
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/crm_regs.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <asm/arch/mx6ul_pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/iomux-v3.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <environment.h>
  19 #include <fsl_esdhc.h>
  20 #include <mmc.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_FEC_MXC
  25 #include <miiphy.h>
  26
  27 #define MDIO_PAD_CTRL ( \
  28         PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29         PAD_CTL_DSE_40ohm \
  30 )
  31
  32 #define ENET_PAD_CTRL_PU ( \
  33         PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34         PAD_CTL_DSE_40ohm \
  35 )
  36
  37 #define ENET_PAD_CTRL_PD ( \
  38         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  39         PAD_CTL_DSE_40ohm \
  40 )
  41
  42 #define ENET_CLK_PAD_CTRL ( \
  43         PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  44         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
  45 )
  46
  47 static iomux_v3_cfg_t const fec1_pads[] = {
  48         MX6_PAD_GPIO1_IO06__ENET1_MDIO        | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  49         MX6_PAD_GPIO1_IO07__ENET1_MDC         | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  50         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER      | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  51         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN      | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  52         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  53         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  54         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  55         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  56         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN      | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  57         /* PHY Int */
  58         MX6_PAD_NAND_DQS__GPIO4_IO16          | MUX_PAD_CTRL(ENET_PAD_CTRL_PU),
  59         /* PHY Reset */
  60         MX6_PAD_NAND_DATA00__GPIO4_IO02       | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  61         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  62 };
  63
  64 int board_phy_config(struct phy_device *phydev)
  65 {
  66         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  67
  68         if (phydev->drv->config)
  69                 phydev->drv->config(phydev);
  70
  71         return 0;
  72 }
  73
  74 int board_eth_init(bd_t *bis)
  75 {
  76         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  77         struct gpio_desc rst;
  78         int ret;
  79
  80         /* Use 50M anatop loopback REF_CLK1 for ENET1,
  81          * clear gpr1[13], set gpr1[17] */
  82         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  83                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  84
  85         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  86         if (ret)
  87                 return ret;
  88
  89         enable_enet_clk(1);
  90
  91         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  92
  93         ret = dm_gpio_lookup_name("GPIO4_2", &rst);
  94         if (ret) {
  95                 printf("Cannot get GPIO4_2\n");
  96                 return ret;
  97         }
  98
  99         ret = dm_gpio_request(&rst, "phy-rst");
 100         if (ret) {
 101                 printf("Cannot request GPIO4_2\n");
 102                 return ret;
 103         }
 104
 105         dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT);
 106         dm_gpio_set_value(&rst, 0);
 107         udelay(1000);
 108         dm_gpio_set_value(&rst, 1);
 109
 110         return fecmxc_initialize(bis);
 111 }
 112 #endif /* CONFIG_FEC_MXC */
 113
 114 int board_init(void)
 115 {
 116         /* Address of boot parameters */
 117         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 118
 119         return 0;
 120 }
 121
 122 int __weak opos6ul_board_late_init(void)
 123 {
 124         return 0;
 125 }
 126
 127 int board_late_init(void)
 128 {
 129         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 130         unsigned reg = readl(&psrc->sbmr2);
 131
 132         /* In bootstrap don't use the env vars */
 133         if (((reg & 0x3000000) >> 24) == 0x1) {
 134                 set_default_env(NULL);
 135                 env_set("preboot", "");
 136         }
 137
 138         return opos6ul_board_late_init();
 139 }
 140
 141 int board_mmc_getcd(struct mmc *mmc)
 142 {
 143         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 144         return cfg->esdhc_base == USDHC1_BASE_ADDR;
 145 }
 146
 147 int dram_init(void)
 148 {
 149         gd->ram_size = imx_ddr_size();
 150
 151         return 0;
 152 }
 153
 154 #ifdef CONFIG_SPL_BUILD
 155 #include <asm/arch/mx6-ddr.h>
 156 #include <asm/arch/opos6ul.h>
 157 #include <linux/libfdt.h>
 158 #include <spl.h>
 159
 160 #define USDHC_PAD_CTRL (                                       \
 161         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \
 162         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST                   \
 163 )
 164
 165 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 166         {USDHC1_BASE_ADDR, 0, 8},
 167 };
 168
 169 static iomux_v3_cfg_t const usdhc1_pads[] = {
 170         MX6_PAD_SD1_CLK__USDHC1_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD1_CMD__USDHC1_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_SD1_DATA0__USDHC1_DATA0    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_SD1_DATA1__USDHC1_DATA1    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_SD1_DATA2__USDHC1_DATA2    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_SD1_DATA3__USDHC1_DATA3    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         MX6_PAD_NAND_CE0_B__USDHC1_DATA5   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         MX6_PAD_NAND_CE1_B__USDHC1_DATA6   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         MX6_PAD_NAND_CLE__USDHC1_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 180 };
 181
 182 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 183         .grp_addds = 0x00000030,
 184         .grp_ddrmode_ctl = 0x00020000,
 185         .grp_b0ds = 0x00000030,
 186         .grp_ctlds = 0x00000030,
 187         .grp_b1ds = 0x00000030,
 188         .grp_ddrpke = 0x00000000,
 189         .grp_ddrmode = 0x00020000,
 190         .grp_ddr_type = 0x000c0000,
 191 };
 192
 193 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 194         .dram_dqm0 = 0x00000030,
 195         .dram_dqm1 = 0x00000030,
 196         .dram_ras = 0x00000030,
 197         .dram_cas = 0x00000030,
 198         .dram_odt0 = 0x00000030,
 199         .dram_odt1 = 0x00000030,
 200         .dram_sdba2 = 0x00000000,
 201         .dram_sdclk_0 = 0x00000008,
 202         .dram_sdqs0 = 0x00000038,
 203         .dram_sdqs1 = 0x00000030,
 204         .dram_reset = 0x00000030,
 205 };
 206
 207 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 208         .p0_mpwldectrl0 = 0x00070007,
 209         .p0_mpdgctrl0 = 0x41490145,
 210         .p0_mprddlctl = 0x40404546,
 211         .p0_mpwrdlctl = 0x4040524D,
 212 };
 213
 214 struct mx6_ddr_sysinfo ddr_sysinfo = {
 215         .dsize = 0,
 216         .cs_density = 20,
 217         .ncs = 1,
 218         .cs1_mirror = 0,
 219         .rtt_wr = 2,
 220         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 221         .walat = 1,             /* Write additional latency */
 222         .ralat = 5,             /* Read additional latency */
 223         .mif3_mode = 3,         /* Command prediction working mode */
 224         .bi_on = 1,             /* Bank interleaving enabled */
 225         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 226         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 227         .ddr_type = DDR_TYPE_DDR3,
 228 };
 229
 230 static struct mx6_ddr3_cfg mem_ddr = {
 231         .mem_speed = 800,
 232         .density = 2,
 233         .width = 16,
 234         .banks = 8,
 235         .rowaddr = 14,
 236         .coladdr = 10,
 237         .pagesz = 2,
 238         .trcd = 1500,
 239         .trcmin = 5250,
 240         .trasmin = 3750,
 241 };
 242
 243 int board_mmc_init(bd_t *bis)
 244 {
 245         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 246         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 247         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 248 }
 249
 250 static void ccgr_init(void)
 251 {
 252         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 253
 254         writel(0xFFFFFFFF, &ccm->CCGR0);
 255         writel(0xFFFFFFFF, &ccm->CCGR1);
 256         writel(0xFFFFFFFF, &ccm->CCGR2);
 257         writel(0xFFFFFFFF, &ccm->CCGR3);
 258         writel(0xFFFFFFFF, &ccm->CCGR4);
 259         writel(0xFFFFFFFF, &ccm->CCGR5);
 260         writel(0xFFFFFFFF, &ccm->CCGR6);
 261         writel(0xFFFFFFFF, &ccm->CCGR7);
 262 }
 263
 264 static void spl_dram_init(void)
 265 {
 266         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 267         struct fuse_bank *bank = &ocotp->bank[4];
 268         struct fuse_bank4_regs *fuse =
 269                 (struct fuse_bank4_regs *)bank->fuse_regs;
 270         int reg = readl(&fuse->gp1);
 271
 272         /* 512MB of RAM */
 273         if (reg & 0x1) {
 274                 mem_ddr.density = 4;
 275                 mem_ddr.rowaddr = 15;
 276                 mem_ddr.trcd = 1375;
 277                 mem_ddr.trcmin = 4875;
 278                 mem_ddr.trasmin = 3500;
 279         }
 280
 281         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 282         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 283 }
 284
 285 void board_init_f(ulong dummy)
 286 {
 287         ccgr_init();
 288
 289         /* setup AIPS and disable watchdog */
 290         arch_cpu_init();
 291
 292         /* setup GP timer */
 293         timer_init();
 294
 295         /* UART clocks enabled and gd valid - init serial console */
 296         opos6ul_setup_uart_debug();
 297         preloader_console_init();
 298
 299         /* DDR initialization */
 300         spl_dram_init();
 301 }
 302 #endif /* CONFIG_SPL_BUILD */