git.sur5r.net Git - u-boot/blob - arch/arm/mach-keystone/init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone2: Architecture initialization
   4  *
   5  * (C) Copyright 2012-2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <ns16550.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/msmc.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/psc_defs.h>
  16
  17 #define MAX_PCI_PORTS           2
  18 enum pci_mode   {
  19         ENDPOINT,
  20         LEGACY_ENDPOINT,
  21         ROOTCOMPLEX,
  22 };
  23
  24 #define DEVCFG_MODE_MASK                (BIT(2) | BIT(1))
  25 #define DEVCFG_MODE_SHIFT               1
  26
  27 void chip_configuration_unlock(void)
  28 {
  29         __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  30         __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  31 }
  32
  33 #ifdef CONFIG_SOC_K2L
  34 void osr_init(void)
  35 {
  36         u32 i;
  37         u32 j;
  38         u32 val;
  39         u32 base = KS2_OSR_CFG_BASE;
  40         u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  41
  42         /* Enable the OSR clock domain */
  43         psc_enable_module(KS2_LPSC_OSR);
  44
  45         /* Disable OSR ECC check for all the ram banks */
  46         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  47                 val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  48                         (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  49
  50                 writel(val , base + KS2_OSR_ECC_VEC);
  51
  52                 /**
  53                  * wait till read is done.
  54                  * Print should be added after earlyprintk support is added.
  55                  */
  56                 for (j = 0; j < 10000; j++) {
  57                         val = readl(base + KS2_OSR_ECC_VEC);
  58                         if (val & KS2_OSR_ECC_VEC_RD_DONE)
  59                                 break;
  60                 }
  61
  62                 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  63                                                 KS2_OSR_ECC_CTRL_CHK;
  64
  65                 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  66                 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  67         }
  68
  69         /* Reset OSR memory to all zeros */
  70         for (i = 0; i < KS2_OSR_SIZE; i += 4)
  71                 writel(0, KS2_OSR_DATA_BASE + i);
  72
  73         /* Enable OSR ECC check for all the ram banks */
  74         for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  75                 writel(ecc_ctrl[i] |
  76                        KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  77 }
  78 #endif
  79
  80 /* Function to set up PCIe mode */
  81 static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
  82 {
  83         u32 val = __raw_readl(KS2_DEVCFG);
  84
  85         if (pcie_port >= MAX_PCI_PORTS)
  86                 return;
  87
  88         /**
  89          * each pci port has two bits for mode and it starts at
  90          * bit 1. So use port number to get the right bit position.
  91          */
  92         pcie_port <<= 1;
  93         val &= ~(DEVCFG_MODE_MASK << pcie_port);
  94         val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  95         __raw_writel(val, KS2_DEVCFG);
  96 }
  97
  98 static void msmc_k2hkle_common_setup(void)
  99 {
 100         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 101         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
 102         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
 103         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
 104         msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
 105         msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 106 }
 107
 108 static void msmc_k2hk_setup(void)
 109 {
 110         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 111         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 112         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 113         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
 114         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
 115         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
 116         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
 117         msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 118 }
 119
 120 static inline void msmc_k2l_setup(void)
 121 {
 122         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
 123         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
 124         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
 125         msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
 126 }
 127
 128 static inline void msmc_k2e_setup(void)
 129 {
 130         msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
 131         msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
 132         msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
 133 }
 134
 135 static void msmc_k2g_setup(void)
 136 {
 137         msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
 138         msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
 139         msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
 140         msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
 141         msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
 142         msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
 143         msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
 144         msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
 145         msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
 146         msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
 147         msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
 148         msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
 149 }
 150
 151 int arch_cpu_init(void)
 152 {
 153         chip_configuration_unlock();
 154         icache_enable();
 155
 156         if (cpu_is_k2g()) {
 157                 msmc_k2g_setup();
 158         } else {
 159                 msmc_k2hkle_common_setup();
 160                 if (cpu_is_k2e())
 161                         msmc_k2e_setup();
 162                 else if (cpu_is_k2l())
 163                         msmc_k2l_setup();
 164                 else
 165                         msmc_k2hk_setup();
 166         }
 167
 168         /* Initialize the PCIe-0 to work as Root Complex */
 169         config_pcie_mode(0, ROOTCOMPLEX);
 170 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
 171         /* Initialize the PCIe-1 to work as Root Complex */
 172         config_pcie_mode(1, ROOTCOMPLEX);
 173 #endif
 174 #ifdef CONFIG_SOC_K2L
 175         osr_init();
 176 #endif
 177
 178         /*
 179          * just initialise the COM2 port so that TI specific
 180          * UART register PWREMU_MGMT is initialized. Linux UART
 181          * driver doesn't handle this.
 182          */
 183 #ifndef CONFIG_DM_SERIAL
 184         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
 185                      CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 186 #endif
 187
 188         return 0;
 189 }
 190
 191 void reset_cpu(ulong addr)
 192 {
 193         volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
 194         u32 tmp;
 195
 196         tmp = *rstctrl & KS2_RSTCTRL_MASK;
 197         *rstctrl = tmp | KS2_RSTCTRL_KEY;
 198
 199         *rstctrl &= KS2_RSTCTRL_SWRST;
 200
 201         for (;;)
 202                 ;
 203 }
 204
 205 void enable_caches(void)
 206 {
 207 #ifndef CONFIG_SYS_DCACHE_OFF
 208         /* Enable D-cache. I-cache is already enabled in start.S */
 209         dcache_enable();
 210 #endif
 211 }
 212
 213 #if defined(CONFIG_DISPLAY_CPUINFO)
 214 int print_cpuinfo(void)
 215 {
 216         u16 cpu = get_part_number();
 217         u8 rev = cpu_revision();
 218
 219         puts("CPU: ");
 220         switch (cpu) {
 221         case CPU_66AK2Hx:
 222                 puts("66AK2Hx SR");
 223                 break;
 224         case CPU_66AK2Lx:
 225                 puts("66AK2Lx SR");
 226                 break;
 227         case CPU_66AK2Ex:
 228                 puts("66AK2Ex SR");
 229                 break;
 230         case CPU_66AK2Gx:
 231                 puts("66AK2Gx");
 232 #ifdef CONFIG_SOC_K2G
 233                 {
 234                         int speed = get_max_arm_speed(speeds);
 235                         if (speed == SPD1000)
 236                                 puts("-100 ");
 237                         else if (speed == SPD600)
 238                                 puts("-60 ");
 239                         else
 240                                 puts("-xx ");
 241                 }
 242 #endif
 243                 puts("SR");
 244                 break;
 245         default:
 246                 puts("Unknown\n");
 247         }
 248
 249         if (rev == 2)
 250                 puts("2.0\n");
 251         else if (rev == 1)
 252                 puts("1.1\n");
 253         else if (rev == 0)
 254                 puts("1.0\n");
 255         else if (rev == 8)
 256                 puts("1.0\n");
 257         return 0;
 258 }
 259 #endif