1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Based on original Kirkwood support which is
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 * Header file for Marvell's Orion SoC with Feroceon CPU core.
13 #ifndef _ASM_ARCH_ORION5X_H
14 #define _ASM_ARCH_ORION5X_H
16 #if defined(CONFIG_FEROCEON)
18 /* SOC specific definations */
19 #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x)
21 /* Documented registers */
22 #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
23 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
24 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
25 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
26 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
27 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
28 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
29 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
30 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
31 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
32 #define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000))
33 #define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
34 #define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
35 #define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
36 #define ORION5X_SATA_BASE (ORION5X_REGISTER(0x80000))
37 #define ORION5X_SATA_PORT0_OFFSET 0x2000
38 #define ORION5X_SATA_PORT1_OFFSET 0x4000
40 /* Orion5x GbE controller has a single port */
41 #define MAX_MVGBE_DEVS 1
42 #define MVGBE0_BASE ORION5X_EGIGA_BASE
44 /* Orion5x USB Host controller is port 1 */
45 #define MVUSB0_BASE ORION5X_USB20_HOST_PORT_BASE
46 #define MVUSB0_CPU_ATTR_DRAM_CS0 ORION5X_ATTR_DRAM_CS0
47 #define MVUSB0_CPU_ATTR_DRAM_CS1 ORION5X_ATTR_DRAM_CS1
48 #define MVUSB0_CPU_ATTR_DRAM_CS2 ORION5X_ATTR_DRAM_CS2
49 #define MVUSB0_CPU_ATTR_DRAM_CS3 ORION5X_ATTR_DRAM_CS3
51 /* Kirkwood CPU memory windows */
52 #define MVCPU_WIN_CTRL_DATA ORION5X_CPU_WIN_CTRL_DATA
53 #define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE
54 #define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE
56 #define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
58 /* include here SoC variants. 5181, 5281, 6183 should go here when
59 adding support for them, and this comment should then be updated. */
60 #if defined(CONFIG_88F5182)
61 #include <asm/arch/mv88f5182.h>
63 #error "SOC Name not defined"
65 #endif /* CONFIG_FEROCEON */
66 #endif /* _ASM_ARCH_ORION5X_H */