git.sur5r.net Git - u-boot/blob - arch/arm/mach-rockchip/rk322x-board-spl.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <dm.h>
  10 #include <ram.h>
  11 #include <spl.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/bootrom.h>
  14 #include <asm/arch/cru_rk322x.h>
  15 #include <asm/arch/grf_rk322x.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/timer.h>
  18 #include <asm/arch/uart.h>
  19
  20 u32 spl_boot_device(void)
  21 {
  22         return BOOT_DEVICE_MMC1;
  23 }
  24 #define GRF_BASE        0x11000000
  25 #define SGRF_BASE       0x10140000
  26
  27 #define DEBUG_UART_BASE 0x11030000
  28
  29 void board_debug_uart_init(void)
  30 {
  31         static struct rk322x_grf * const grf = (void *)GRF_BASE;
  32         enum {
  33                 GPIO1B2_SHIFT           = 4,
  34                 GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
  35                 GPIO1B2_GPIO            = 0,
  36                 GPIO1B2_UART1_SIN,
  37                 GPIO1B2_UART21_SIN,
  38
  39                 GPIO1B1_SHIFT           = 2,
  40                 GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
  41                 GPIO1B1_GPIO            = 0,
  42                 GPIO1B1_UART1_SOUT,
  43                 GPIO1B1_UART21_SOUT,
  44         };
  45         enum {
  46                 CON_IOMUX_UART2SEL_SHIFT= 8,
  47                 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
  48                 CON_IOMUX_UART2SEL_2    = 0,
  49                 CON_IOMUX_UART2SEL_21,
  50         };
  51
  52         /* Enable early UART2 channel 1 on the RK322x */
  53         rk_clrsetreg(&grf->gpio1b_iomux,
  54                      GPIO1B1_MASK | GPIO1B2_MASK,
  55                      GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
  56                      GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
  57         /* Set channel C as UART2 input */
  58         rk_clrsetreg(&grf->con_iomux,
  59                      CON_IOMUX_UART2SEL_MASK,
  60                      CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
  61 }
  62
  63 #define SGRF_DDR_CON0 0x10150000
  64 void board_init_f(ulong dummy)
  65 {
  66         struct udevice *dev;
  67         int ret;
  68
  69         /*
  70          * Debug UART can be used from here if required:
  71          *
  72          * debug_uart_init();
  73          * printch('a');
  74          * printhex8(0x1234);
  75          * printascii("string");
  76          */
  77         debug_uart_init();
  78         printascii("SPL Init");
  79
  80         ret = spl_early_init();
  81         if (ret) {
  82                 debug("spl_early_init() failed: %d\n", ret);
  83                 hang();
  84         }
  85
  86         rockchip_timer_init();
  87         printf("timer init done\n");
  88         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  89         if (ret) {
  90                 printf("DRAM init failed: %d\n", ret);
  91                 return;
  92         }
  93
  94         /* Disable the ddr secure region setting to make it non-secure */
  95         rk_clrreg(SGRF_DDR_CON0, 0x4000);
  96 #if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
  97         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  98 #endif
  99 }