git.sur5r.net Git - u-boot/blob - arch/arm/mach-snapdragon/clock-apq8016.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Clock drivers for Qualcomm APQ8016
   4  *
   5  * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
   6  *
   7  * Based on Little Kernel driver, simplified
   8  */
   9
  10 #include <common.h>
  11 #include <clk-uclass.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <asm/io.h>
  15 #include <linux/bitops.h>
  16 #include "clock-snapdragon.h"
  17
  18 /* GPLL0 clock control registers */
  19 #define GPLL0_STATUS_ACTIVE BIT(17)
  20 #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
  21
  22 static const struct bcr_regs sdc_regs[] = {
  23         {
  24         .cfg_rcgr = SDCC_CFG_RCGR(1),
  25         .cmd_rcgr = SDCC_CMD_RCGR(1),
  26         .M = SDCC_M(1),
  27         .N = SDCC_N(1),
  28         .D = SDCC_D(1),
  29         },
  30         {
  31         .cfg_rcgr = SDCC_CFG_RCGR(2),
  32         .cmd_rcgr = SDCC_CMD_RCGR(2),
  33         .M = SDCC_M(2),
  34         .N = SDCC_N(2),
  35         .D = SDCC_D(2),
  36         }
  37 };
  38
  39 static struct gpll0_ctrl gpll0_ctrl = {
  40         .status = GPLL0_STATUS,
  41         .status_bit = GPLL0_STATUS_ACTIVE,
  42         .ena_vote = APCS_GPLL_ENA_VOTE,
  43         .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
  44 };
  45
  46 /* SDHCI */
  47 static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
  48 {
  49         int div = 8; /* 100MHz default */
  50
  51         if (rate == 200000000)
  52                 div = 4;
  53
  54         clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
  55         /* 800Mhz/div, gpll0 */
  56         clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
  57                              CFG_CLK_SRC_GPLL0);
  58         clk_enable_gpll0(priv->base, &gpll0_ctrl);
  59         clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
  60
  61         return rate;
  62 }
  63
  64 static const struct bcr_regs uart2_regs = {
  65         .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
  66         .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
  67         .M = BLSP1_UART2_APPS_M,
  68         .N = BLSP1_UART2_APPS_N,
  69         .D = BLSP1_UART2_APPS_D,
  70 };
  71
  72 /* UART: 115200 */
  73 static int clk_init_uart(struct msm_clk_priv *priv)
  74 {
  75         /* Enable iface clk */
  76         clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
  77         /* 7372800 uart block clock @ GPLL0 */
  78         clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
  79                              CFG_CLK_SRC_GPLL0);
  80         clk_enable_gpll0(priv->base, &gpll0_ctrl);
  81         /* Enable core clk */
  82         clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
  83
  84         return 0;
  85 }
  86
  87 ulong msm_set_rate(struct clk *clk, ulong rate)
  88 {
  89         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  90
  91         switch (clk->id) {
  92         case 0: /* SDC1 */
  93                 return clk_init_sdc(priv, 0, rate);
  94                 break;
  95         case 1: /* SDC2 */
  96                 return clk_init_sdc(priv, 1, rate);
  97                 break;
  98         case 4: /* UART2 */
  99                 return clk_init_uart(priv);
 100                 break;
 101         default:
 102                 return 0;
 103         }
 104 }