git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config TARGET_SOCFPGA_ARRIA5
   4         bool
   5         select TARGET_SOCFPGA_GEN5
   6
   7 config TARGET_SOCFPGA_CYCLONE5
   8         bool
   9         select TARGET_SOCFPGA_GEN5
  10
  11 config TARGET_SOCFPGA_GEN5
  12         bool
  13
  14 choice
  15         prompt "Altera SOCFPGA board select"
  16         optional
  17
  18 config TARGET_SOCFPGA_ARRIA5_SOCDK
  19         bool "Altera SOCFPGA SoCDK (Arria V)"
  20         select TARGET_SOCFPGA_ARRIA5
  21
  22 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  23         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  24         select TARGET_SOCFPGA_CYCLONE5
  25
  26 config TARGET_SOCFPGA_DENX_MCVEVK
  27         bool "DENX MCVEVK (Cyclone V)"
  28         select TARGET_SOCFPGA_CYCLONE5
  29
  30 config TARGET_SOCFPGA_SR1500
  31         bool "SR1500 (Cyclone V)"
  32         select TARGET_SOCFPGA_CYCLONE5
  33
  34 config TARGET_SOCFPGA_EBV_SOCRATES
  35         bool "EBV SoCrates (Cyclone V)"
  36         select TARGET_SOCFPGA_CYCLONE5
  37
  38 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  39         bool "samtec VIN|ING FPGA (Cyclone V)"
  40         select TARGET_SOCFPGA_CYCLONE5
  41
  42 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  43         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  44         select TARGET_SOCFPGA_CYCLONE5
  45
  46 config TARGET_SOCFPGA_TERASIC_SOCKIT
  47         bool "Terasic SoCkit (Cyclone V)"
  48         select TARGET_SOCFPGA_CYCLONE5
  49
  50 endchoice
  51
  52 config SYS_BOARD
  53         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  54         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  55         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  56         default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  57         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  58         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  59         default "sr1500" if TARGET_SOCFPGA_SR1500
  60         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  61
  62 config SYS_VENDOR
  63         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  64         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  65         default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
  66         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  67         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  68         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  69         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  70
  71 config SYS_SOC
  72         default "socfpga"
  73
  74 config SYS_CONFIG_NAME
  75         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  76         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  77         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  78         default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  79         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  80         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  81         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  82         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  83
  84 endif