git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SPL_LIBCOMMON_SUPPORT
   4         default y
   5
   6 config SPL_LIBDISK_SUPPORT
   7         default y
   8
   9 config SPL_LIBGENERIC_SUPPORT
  10         default y
  11
  12 config SPL_MMC_SUPPORT
  13         default y if DM_MMC
  14
  15 config SPL_NAND_SUPPORT
  16         default y if SPL_NAND_DENALI
  17
  18 config SPL_SERIAL_SUPPORT
  19         default y
  20
  21 config SPL_SPI_FLASH_SUPPORT
  22         default y if SPL_SPI_SUPPORT
  23
  24 config SPL_SPI_SUPPORT
  25         default y if DM_SPI
  26
  27 config SPL_WATCHDOG_SUPPORT
  28         default y
  29
  30 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
  31         default y
  32
  33 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  34         default 0xa2
  35
  36 config TARGET_SOCFPGA_ARRIA5
  37         bool
  38         select TARGET_SOCFPGA_GEN5
  39
  40 config TARGET_SOCFPGA_CYCLONE5
  41         bool
  42         select TARGET_SOCFPGA_GEN5
  43
  44 config TARGET_SOCFPGA_GEN5
  45         bool
  46         select ALTERA_SDRAM
  47
  48 choice
  49         prompt "Altera SOCFPGA board select"
  50         optional
  51
  52 config TARGET_SOCFPGA_ARRIA5_SOCDK
  53         bool "Altera SOCFPGA SoCDK (Arria V)"
  54         select TARGET_SOCFPGA_ARRIA5
  55
  56 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  57         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  58         select TARGET_SOCFPGA_CYCLONE5
  59
  60 config TARGET_SOCFPGA_ARIES_MCVEVK
  61         bool "Aries MCVEVK (Cyclone V)"
  62         select TARGET_SOCFPGA_CYCLONE5
  63
  64 config TARGET_SOCFPGA_EBV_SOCRATES
  65         bool "EBV SoCrates (Cyclone V)"
  66         select TARGET_SOCFPGA_CYCLONE5
  67
  68 config TARGET_SOCFPGA_IS1
  69         bool "IS1 (Cyclone V)"
  70         select TARGET_SOCFPGA_CYCLONE5
  71
  72 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  73         bool "samtec VIN|ING FPGA (Cyclone V)"
  74         select BOARD_LATE_INIT
  75         select TARGET_SOCFPGA_CYCLONE5
  76
  77 config TARGET_SOCFPGA_SR1500
  78         bool "SR1500 (Cyclone V)"
  79         select TARGET_SOCFPGA_CYCLONE5
  80
  81 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  82         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  83         select TARGET_SOCFPGA_CYCLONE5
  84
  85 config TARGET_SOCFPGA_TERASIC_DE1_SOC
  86         bool "Terasic DE1-SoC (Cyclone V)"
  87         select TARGET_SOCFPGA_CYCLONE5
  88
  89 config TARGET_SOCFPGA_TERASIC_SOCKIT
  90         bool "Terasic SoCkit (Cyclone V)"
  91         select TARGET_SOCFPGA_CYCLONE5
  92
  93 endchoice
  94
  95 config SYS_BOARD
  96         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  97         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  98         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  99         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 100         default "is1" if TARGET_SOCFPGA_IS1
 101         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 102         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 103         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 104         default "sr1500" if TARGET_SOCFPGA_SR1500
 105         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 106
 107 config SYS_VENDOR
 108         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 109         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 110         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 111         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 112         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 113         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 114         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 115         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 116
 117 config SYS_SOC
 118         default "socfpga"
 119
 120 config SYS_CONFIG_NAME
 121         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 122         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 123         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 124         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 125         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 126         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 127         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 128         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 129         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 130         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 131
 132 endif