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   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #ifndef _FIREWALL_S10_
   8 #define _FIREWALL_S10_
   9
  10 struct socfpga_firwall_l4_per {
  11         u32     nand;           /* 0x00 */
  12         u32     nand_data;
  13         u32     _pad_0x8;
  14         u32     usb0;
  15         u32     usb1;           /* 0x10 */
  16         u32     _pad_0x14;
  17         u32     _pad_0x18;
  18         u32     spim0;
  19         u32     spim1;          /* 0x20 */
  20         u32     spis0;
  21         u32     spis1;
  22         u32     emac0;
  23         u32     emac1;          /* 0x30 */
  24         u32     emac2;
  25         u32     _pad_0x38;
  26         u32     _pad_0x3c;
  27         u32     sdmmc;          /* 0x40 */
  28         u32     gpio0;
  29         u32     gpio1;
  30         u32     _pad_0x4c;
  31         u32     i2c0;           /* 0x50 */
  32         u32     i2c1;
  33         u32     i2c2;
  34         u32     i2c3;
  35         u32     i2c4;           /* 0x60 */
  36         u32     timer0;
  37         u32     timer1;
  38         u32     uart0;
  39         u32     uart1;          /* 0x70 */
  40 };
  41
  42 struct socfpga_firwall_l4_sys {
  43         u32     _pad_0x00;              /* 0x00 */
  44         u32     _pad_0x04;
  45         u32     dma_ecc;
  46         u32     emac0rx_ecc;
  47         u32     emac0tx_ecc;            /* 0x10 */
  48         u32     emac1rx_ecc;
  49         u32     emac1tx_ecc;
  50         u32     emac2rx_ecc;
  51         u32     emac2tx_ecc;            /* 0x20 */
  52         u32     _pad_0x24;
  53         u32     _pad_0x28;
  54         u32     nand_ecc;
  55         u32     nand_read_ecc;          /* 0x30 */
  56         u32     nand_write_ecc;
  57         u32     ocram_ecc;
  58         u32     _pad_0x3c;
  59         u32     sdmmc_ecc;              /* 0x40 */
  60         u32     usb0_ecc;
  61         u32     usb1_ecc;
  62         u32     clock_manager;
  63         u32     _pad_0x50;              /* 0x50 */
  64         u32     io_manager;
  65         u32     reset_manager;
  66         u32     system_manager;
  67         u32     osc0_timer;             /* 0x60 */
  68         u32     osc1_timer;
  69         u32     watchdog0;
  70         u32     watchdog1;
  71         u32     watchdog2;              /* 0x70 */
  72         u32     watchdog3;
  73 };
  74
  75 #define FIREWALL_L4_DISABLE_ALL         (BIT(0) | BIT(24) | BIT(16))
  76 #define FIREWALL_BRIDGE_DISABLE_ALL     (~0)
  77
  78 /* Cache coherency unit (CCU) registers */
  79 #define CCU_CPU0_MPRT_ADBASE_DDRREG             0x4400
  80 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE0          0x45c0
  81 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A         0x45e0
  82 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B         0x4600
  83 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C         0x4620
  84 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D         0x4640
  85 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E         0x4660
  86
  87 #define CCU_CPU0_MPRT_ADMASK_MEM_RAM0           0x4688
  88
  89 #define CCU_IOM_MPRT_ADBASE_MEMSPACE0           0x18560
  90 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1A          0x18580
  91 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1B          0x185a0
  92 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1C          0x185c0
  93 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1D          0x185e0
  94 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1E          0x18600
  95
  96 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0            0x18628
  97
  98 #define CCU_ADMASK_P_MASK                       BIT(0)
  99 #define CCU_ADMASK_NS_MASK                      BIT(1)
 100
 101 #define CCU_ADBASE_DI_MASK                      BIT(4)
 102
 103 #define CCU_REG_ADDR(reg)                       \
 104         (SOCFPGA_CCU_ADDRESS + (reg))
 105
 106 /* Firewall MPU DDR SCR registers */
 107 #define FW_MPU_DDR_SCR_EN                               0x00
 108 #define FW_MPU_DDR_SCR_EN_SET                           0x04
 109 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT             0x18
 110 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT          0x1c
 111 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT          0x98
 112 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT       0x9c
 113
 114 #define MPUREGION0_ENABLE                               BIT(0)
 115 #define NONMPUREGION0_ENABLE                            BIT(8)
 116
 117 #define FW_MPU_DDR_SCR_WRITEL(data, reg)                \
 118         writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
 119
 120 #endif /* _FIREWALL_S10_ */