2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fpga_manager.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/system_manager.h>
14 static const struct socfpga_reset_manager *reset_manager_base =
15 (void *)SOCFPGA_RSTMGR_ADDRESS;
16 static const struct socfpga_system_manager *sysmgr_regs =
17 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
19 /* Assert or de-assert SoCFPGA reset manager reset. */
20 void socfpga_per_reset(u32 reset, int set)
23 u32 rstmgr_bank = RSTMGR_BANK(reset);
25 switch (rstmgr_bank) {
27 reg = &reset_manager_base->mpu_mod_reset;
30 reg = &reset_manager_base->per_mod_reset;
33 reg = &reset_manager_base->per2_mod_reset;
36 reg = &reset_manager_base->brg_mod_reset;
39 reg = &reset_manager_base->misc_mod_reset;
47 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
49 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
53 * Assert reset on every peripheral but L4WD0.
54 * Watchdog must be kept intact to prevent glitches
57 void socfpga_per_reset_all(void)
59 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
61 writel(~l4wd0, &reset_manager_base->per_mod_reset);
62 writel(0xffffffff, &reset_manager_base->per2_mod_reset);
66 * Release peripherals from reset based on handoff
68 void reset_deassert_peripherals_handoff(void)
70 writel(0, &reset_manager_base->per_mod_reset);
73 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
74 void socfpga_bridges_reset(int enable)
76 /* For SoCFPGA-VT, this is NOP. */
81 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
82 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
83 #define L3REGS_REMAP_OCRAM_MASK 0x01
85 void socfpga_bridges_reset(int enable)
87 const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
88 L3REGS_REMAP_HPS2FPGA_MASK |
89 L3REGS_REMAP_OCRAM_MASK;
93 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
95 writel(0, &sysmgr_regs->iswgrp_handoff[0]);
96 writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
98 /* Check signal from FPGA. */
99 if (!fpgamgr_test_fpga_ready()) {
100 /* FPGA not ready, do nothing. We allow system to boot
101 * without FPGA ready. So, return 0 instead of error. */
102 printf("%s: FPGA not ready, aborting.\n", __func__);
107 writel(0, &reset_manager_base->brg_mod_reset);
109 /* Remap the bridges into memory map */
110 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);