git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/u-boot.h>
   9 #include <asm/utils.h>
  10 #include <common.h>
  11 #include <image.h>
  12 #include <spl.h>
  13 #include <asm/arch/clock_manager.h>
  14 #include <asm/arch/firewall_s10.h>
  15 #include <asm/arch/mailbox_s10.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/sdram_s10.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <watchdog.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static struct socfpga_system_manager *sysmgr_regs =
  24         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  25
  26 u32 spl_boot_device(void)
  27 {
  28         /* TODO: Get from SDM or handoff */
  29         return BOOT_DEVICE_MMC1;
  30 }
  31
  32 #ifdef CONFIG_SPL_MMC_SUPPORT
  33 u32 spl_boot_mode(const u32 boot_device)
  34 {
  35 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
  36         return MMCSD_MODE_FS;
  37 #else
  38         return MMCSD_MODE_RAW;
  39 #endif
  40 }
  41 #endif
  42
  43 void spl_disable_firewall_l4_per(void)
  44 {
  45         const struct socfpga_firwall_l4_per *firwall_l4_per_base =
  46                 (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
  47         u32 i;
  48         const u32 *addr[] = {
  49                         &firwall_l4_per_base->nand,
  50                         &firwall_l4_per_base->nand_data,
  51                         &firwall_l4_per_base->usb0,
  52                         &firwall_l4_per_base->usb1,
  53                         &firwall_l4_per_base->spim0,
  54                         &firwall_l4_per_base->spim1,
  55                         &firwall_l4_per_base->emac0,
  56                         &firwall_l4_per_base->emac1,
  57                         &firwall_l4_per_base->emac2,
  58                         &firwall_l4_per_base->sdmmc,
  59                         &firwall_l4_per_base->gpio0,
  60                         &firwall_l4_per_base->gpio1,
  61                         &firwall_l4_per_base->i2c0,
  62                         &firwall_l4_per_base->i2c1,
  63                         &firwall_l4_per_base->i2c2,
  64                         &firwall_l4_per_base->i2c3,
  65                         &firwall_l4_per_base->i2c4,
  66                         &firwall_l4_per_base->timer0,
  67                         &firwall_l4_per_base->timer1,
  68                         &firwall_l4_per_base->uart0,
  69                         &firwall_l4_per_base->uart1
  70                         };
  71
  72         /*
  73          * The following lines of code will enable non-secure access
  74          * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
  75          * is needed as most OS run in non-secure mode. Thus we need to
  76          * enable non-secure access to these peripherals in order for the
  77          * OS to use these peripherals.
  78          */
  79         for (i = 0; i < ARRAY_SIZE(addr); i++)
  80                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
  81 }
  82
  83 void spl_disable_firewall_l4_sys(void)
  84 {
  85         const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
  86                 (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
  87         u32 i;
  88         const u32 *addr[] = {
  89                         &firwall_l4_sys_base->dma_ecc,
  90                         &firwall_l4_sys_base->emac0rx_ecc,
  91                         &firwall_l4_sys_base->emac0tx_ecc,
  92                         &firwall_l4_sys_base->emac1rx_ecc,
  93                         &firwall_l4_sys_base->emac1tx_ecc,
  94                         &firwall_l4_sys_base->emac2rx_ecc,
  95                         &firwall_l4_sys_base->emac2tx_ecc,
  96                         &firwall_l4_sys_base->nand_ecc,
  97                         &firwall_l4_sys_base->nand_read_ecc,
  98                         &firwall_l4_sys_base->nand_write_ecc,
  99                         &firwall_l4_sys_base->ocram_ecc,
 100                         &firwall_l4_sys_base->sdmmc_ecc,
 101                         &firwall_l4_sys_base->usb0_ecc,
 102                         &firwall_l4_sys_base->usb1_ecc,
 103                         &firwall_l4_sys_base->clock_manager,
 104                         &firwall_l4_sys_base->io_manager,
 105                         &firwall_l4_sys_base->reset_manager,
 106                         &firwall_l4_sys_base->system_manager,
 107                         &firwall_l4_sys_base->watchdog0,
 108                         &firwall_l4_sys_base->watchdog1,
 109                         &firwall_l4_sys_base->watchdog2,
 110                         &firwall_l4_sys_base->watchdog3
 111                 };
 112
 113         for (i = 0; i < ARRAY_SIZE(addr); i++)
 114                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
 115 }
 116
 117 void board_init_f(ulong dummy)
 118 {
 119         const struct cm_config *cm_default_cfg = cm_get_default_config();
 120         int ret;
 121
 122 #ifdef CONFIG_HW_WATCHDOG
 123         /* Ensure watchdog is paused when debugging is happening */
 124         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
 125
 126         /* Enable watchdog before initializing the HW */
 127         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 128         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 129         hw_watchdog_init();
 130 #endif
 131
 132         /* ensure all processors are not released prior Linux boot */
 133         writeq(0, CPU_RELEASE_ADDR);
 134
 135         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 136         timer_init();
 137
 138         populate_sysmgr_pinmux();
 139
 140         /* configuring the HPS clocks */
 141         cm_basic_init(cm_default_cfg);
 142
 143 #ifdef CONFIG_DEBUG_UART
 144         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 145         debug_uart_init();
 146 #endif
 147         ret = spl_early_init();
 148         if (ret) {
 149                 debug("spl_early_init() failed: %d\n", ret);
 150                 hang();
 151         }
 152
 153         preloader_console_init();
 154         cm_print_clock_quick_summary();
 155
 156         /* enable non-secure interface to DMA330 DMA and peripherals */
 157         writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
 158         writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
 159
 160         spl_disable_firewall_l4_per();
 161
 162         spl_disable_firewall_l4_sys();
 163
 164         /* disable lwsocf2fpga and soc2fpga bridge security */
 165         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
 166         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
 167
 168         /* disable SMMU security */
 169         writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
 170
 171         /* disable ocram security at CCU for non secure access */
 172         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
 173                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 174         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
 175                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 176
 177         debug("DDR: Initializing Hard Memory Controller\n");
 178         if (sdram_mmr_init_full(0)) {
 179                 puts("DDR: Initialization failed.\n");
 180                 hang();
 181         }
 182
 183         gd->ram_size = sdram_calculate_size();
 184         printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
 185
 186         /* Sanity check ensure correct SDRAM size specified */
 187         debug("DDR: Running SDRAM size sanity check\n");
 188         if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
 189                 puts("DDR: SDRAM size check failed!\n");
 190                 hang();
 191         }
 192         debug("DDR: SDRAM size check passed!\n");
 193
 194         mbox_init();
 195
 196 #ifdef CONFIG_CADENCE_QSPI
 197         mbox_qspi_open();
 198 #endif
 199 }