4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
40 config MACH_SUNXI_H3_H5
45 select SUNXI_GEN_SUN6I
49 prompt "Sunxi SoC Variant"
53 bool "sun4i (Allwinner A10)"
55 select ARM_CORTEX_CPU_IS_UP
56 select SUNXI_GEN_SUN4I
60 bool "sun5i (Allwinner A13)"
62 select ARM_CORTEX_CPU_IS_UP
63 select SUNXI_GEN_SUN4I
67 bool "sun6i (Allwinner A31)"
69 select CPU_V7_HAS_NONSEC
70 select CPU_V7_HAS_VIRT
71 select ARCH_SUPPORT_PSCI
72 select SUNXI_GEN_SUN6I
74 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
77 bool "sun7i (Allwinner A20)"
79 select CPU_V7_HAS_NONSEC
80 select CPU_V7_HAS_VIRT
81 select ARCH_SUPPORT_PSCI
82 select SUNXI_GEN_SUN4I
84 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
87 bool "sun8i (Allwinner A23)"
89 select CPU_V7_HAS_NONSEC
90 select CPU_V7_HAS_VIRT
91 select ARCH_SUPPORT_PSCI
92 select SUNXI_GEN_SUN6I
94 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
97 bool "sun8i (Allwinner A33)"
99 select CPU_V7_HAS_NONSEC
100 select CPU_V7_HAS_VIRT
101 select ARCH_SUPPORT_PSCI
102 select SUNXI_GEN_SUN6I
104 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
106 config MACH_SUN8I_A83T
107 bool "sun8i (Allwinner A83T)"
109 select SUNXI_GEN_SUN6I
113 bool "sun8i (Allwinner H3)"
115 select CPU_V7_HAS_NONSEC
116 select CPU_V7_HAS_VIRT
117 select ARCH_SUPPORT_PSCI
118 select MACH_SUNXI_H3_H5
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_R40
122 bool "sun8i (Allwinner R40)"
124 select CPU_V7_HAS_NONSEC
125 select CPU_V7_HAS_VIRT
126 select ARCH_SUPPORT_PSCI
127 select SUNXI_GEN_SUN6I
131 config MACH_SUN8I_V3S
132 bool "sun8i (Allwinner V3s)"
134 select CPU_V7_HAS_NONSEC
135 select CPU_V7_HAS_VIRT
136 select ARCH_SUPPORT_PSCI
137 select SUNXI_GEN_SUN6I
138 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
141 bool "sun9i (Allwinner A80)"
143 select SUNXI_HIGH_SRAM
144 select SUNXI_GEN_SUN6I
148 bool "sun50i (Allwinner A64)"
152 select SUNXI_GEN_SUN6I
153 select SUNXI_HIGH_SRAM
159 config MACH_SUN50I_H5
160 bool "sun50i (Allwinner H5)"
162 select MACH_SUNXI_H3_H5
163 select SUNXI_HIGH_SRAM
169 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
172 default y if MACH_SUN8I_A23
173 default y if MACH_SUN8I_A33
174 default y if MACH_SUN8I_A83T
175 default y if MACH_SUNXI_H3_H5
176 default y if MACH_SUN8I_R40
177 default y if MACH_SUN8I_V3S
179 config RESERVE_ALLWINNER_BOOT0_HEADER
180 bool "reserve space for Allwinner boot0 header"
181 select ENABLE_ARM_SOC_BOOT0_HOOK
183 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
184 filled with magic values post build. The Allwinner provided boot0
185 blob relies on this information to load and execute U-Boot.
186 Only needed on 64-bit Allwinner boards so far when using boot0.
188 config ARM_BOOT_HOOK_RMR
192 select ENABLE_ARM_SOC_BOOT0_HOOK
194 Insert some ARM32 code at the very beginning of the U-Boot binary
195 which uses an RMR register write to bring the core into AArch64 mode.
196 The very first instruction acts as a switch, since it's carefully
197 chosen to be a NOP in one mode and a branch in the other, so the
198 code would only be executed if not already in AArch64.
199 This allows both the SPL and the U-Boot proper to be entered in
200 either mode and switch to AArch64 if needed.
203 int "sunxi dram type"
204 depends on MACH_SUN8I_A83T
207 Set the dram type, 3: DDR3, 7: LPDDR3
210 int "sunxi dram clock speed"
211 default 792 if MACH_SUN9I
212 default 648 if MACH_SUN8I_R40
213 default 312 if MACH_SUN6I || MACH_SUN8I
214 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
215 default 672 if MACH_SUN50I
217 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
218 must be a multiple of 24. For the sun9i (A80), the tested values
219 (for DDR3-1600) are 312 to 792.
221 if MACH_SUN5I || MACH_SUN7I
223 int "sunxi mbus clock speed"
226 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
231 int "sunxi dram zq value"
232 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
233 default 127 if MACH_SUN7I
234 default 3881979 if MACH_SUN8I_R40
235 default 4145117 if MACH_SUN9I
236 default 3881915 if MACH_SUN50I
238 Set the dram zq value.
241 bool "sunxi dram odt enable"
242 default n if !MACH_SUN8I_A23
243 default y if MACH_SUN8I_A23
244 default y if MACH_SUN8I_R40
245 default y if MACH_SUN50I
247 Select this to enable dram odt (on die termination).
249 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
251 int "sunxi dram emr1 value"
252 default 0 if MACH_SUN4I
253 default 4 if MACH_SUN5I || MACH_SUN7I
255 Set the dram controller emr1 value.
258 hex "sunxi dram tpr3 value"
261 Set the dram controller tpr3 parameter. This parameter configures
262 the delay on the command lane and also phase shifts, which are
263 applied for sampling incoming read data. The default value 0
264 means that no phase/delay adjustments are necessary. Properly
265 configuring this parameter increases reliability at high DRAM
268 config DRAM_DQS_GATING_DELAY
269 hex "sunxi dram dqs_gating_delay value"
272 Set the dram controller dqs_gating_delay parmeter. Each byte
273 encodes the DQS gating delay for each byte lane. The delay
274 granularity is 1/4 cycle. For example, the value 0x05060606
275 means that the delay is 5 quarter-cycles for one lane (1.25
276 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
277 The default value 0 means autodetection. The results of hardware
278 autodetection are not very reliable and depend on the chip
279 temperature (sometimes producing different results on cold start
280 and warm reboot). But the accuracy of hardware autodetection
281 is usually good enough, unless running at really high DRAM
282 clocks speeds (up to 600MHz). If unsure, keep as 0.
285 prompt "sunxi dram timings"
286 default DRAM_TIMINGS_VENDOR_MAGIC
288 Select the timings of the DDR3 chips.
290 config DRAM_TIMINGS_VENDOR_MAGIC
291 bool "Magic vendor timings from Android"
293 The same DRAM timings as in the Allwinner boot0 bootloader.
295 config DRAM_TIMINGS_DDR3_1066F_1333H
296 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
298 Use the timings of the standard JEDEC DDR3-1066F speed bin for
299 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
300 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
301 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
302 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
303 that down binning to DDR3-1066F is supported (because DDR3-1066F
304 uses a bit faster timings than DDR3-1333H).
306 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
307 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
309 Use the timings of the slowest possible JEDEC speed bin for the
310 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
311 DDR3-800E, DDR3-1066G or DDR3-1333J.
318 config DRAM_ODT_CORRECTION
319 int "sunxi dram odt correction value"
322 Set the dram odt correction value (range -255 - 255). In allwinner
323 fex files, this option is found in bits 8-15 of the u32 odt_en variable
324 in the [dram] section. When bit 31 of the odt_en variable is set
325 then the correction is negative. Usually the value for this is 0.
329 default 1008000000 if MACH_SUN4I
330 default 1008000000 if MACH_SUN5I
331 default 1008000000 if MACH_SUN6I
332 default 912000000 if MACH_SUN7I
333 default 1008000000 if MACH_SUN8I
334 default 1008000000 if MACH_SUN9I
335 default 816000000 if MACH_SUN50I
337 config SYS_CONFIG_NAME
338 default "sun4i" if MACH_SUN4I
339 default "sun5i" if MACH_SUN5I
340 default "sun6i" if MACH_SUN6I
341 default "sun7i" if MACH_SUN7I
342 default "sun8i" if MACH_SUN8I
343 default "sun9i" if MACH_SUN9I
344 default "sun50i" if MACH_SUN50I
353 bool "UART0 on MicroSD breakout board"
356 Repurpose the SD card slot for getting access to the UART0 serial
357 console. Primarily useful only for low level u-boot debugging on
358 tablets, where normal UART0 is difficult to access and requires
359 device disassembly and/or soldering. As the SD card can't be used
360 at the same time, the system can be only booted in the FEL mode.
361 Only enable this if you really know what you are doing.
363 config OLD_SUNXI_KERNEL_COMPAT
364 bool "Enable workarounds for booting old kernels"
367 Set this to enable various workarounds for old kernels, this results in
368 sub-optimal settings for newer kernels, only enable if needed.
371 string "MAC power pin"
374 Set the pin used to power the MAC. This takes a string in the format
375 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
378 string "Card detect pin for mmc0"
379 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
382 Set the card detect pin for mmc0, leave empty to not use cd. This
383 takes a string in the format understood by sunxi_name_to_gpio, e.g.
384 PH1 for pin 1 of port H.
387 string "Card detect pin for mmc1"
390 See MMC0_CD_PIN help text.
393 string "Card detect pin for mmc2"
396 See MMC0_CD_PIN help text.
399 string "Card detect pin for mmc3"
402 See MMC0_CD_PIN help text.
405 string "Pins for mmc1"
408 Set the pins used for mmc1, when applicable. This takes a string in the
409 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
412 string "Pins for mmc2"
415 See MMC1_PINS help text.
418 string "Pins for mmc3"
421 See MMC1_PINS help text.
423 config MMC_SUNXI_SLOT_EXTRA
424 int "mmc extra slot number"
427 sunxi builds always enable mmc0, some boards also have a second sdcard
428 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
431 config INITIAL_USB_SCAN_DELAY
432 int "delay initial usb scan by x ms to allow builtin devices to init"
435 Some boards have on board usb devices which need longer than the
436 USB spec's 1 second to connect from board powerup. Set this config
437 option to a non 0 value to add an extra delay before the first usb
441 string "Vbus enable pin for usb0 (otg)"
444 Set the Vbus enable pin for usb0 (otg). This takes a string in the
445 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
448 string "Vbus detect pin for usb0 (otg)"
451 Set the Vbus detect pin for usb0 (otg). This takes a string in the
452 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
455 string "ID detect pin for usb0 (otg)"
458 Set the ID detect pin for usb0 (otg). This takes a string in the
459 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
462 string "Vbus enable pin for usb1 (ehci0)"
463 default "PH6" if MACH_SUN4I || MACH_SUN7I
464 default "PH27" if MACH_SUN6I
466 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
467 a string in the format understood by sunxi_name_to_gpio, e.g.
468 PH1 for pin 1 of port H.
471 string "Vbus enable pin for usb2 (ehci1)"
472 default "PH3" if MACH_SUN4I || MACH_SUN7I
473 default "PH24" if MACH_SUN6I
475 See USB1_VBUS_PIN help text.
478 string "Vbus enable pin for usb3 (ehci2)"
481 See USB1_VBUS_PIN help text.
484 bool "Enable I2C/TWI controller 0"
485 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
486 default n if MACH_SUN6I || MACH_SUN8I
489 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
490 its clock and setting up the bus. This is especially useful on devices
491 with slaves connected to the bus or with pins exposed through e.g. an
492 expansion port/header.
495 bool "Enable I2C/TWI controller 1"
499 See I2C0_ENABLE help text.
502 bool "Enable I2C/TWI controller 2"
506 See I2C0_ENABLE help text.
508 if MACH_SUN6I || MACH_SUN7I
510 bool "Enable I2C/TWI controller 3"
514 See I2C0_ENABLE help text.
519 bool "Enable the PRCM I2C/TWI controller"
520 # This is used for the pmic on H3
521 default y if SY8106A_POWER
524 Set this to y to enable the I2C controller which is part of the PRCM.
529 bool "Enable I2C/TWI controller 4"
533 See I2C0_ENABLE help text.
537 bool "Enable support for gpio-s on axp PMICs"
540 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
543 bool "Enable graphical uboot console on HDMI, LCD or VGA"
544 depends on !MACH_SUN8I_A83T
545 depends on !MACH_SUNXI_H3_H5
546 depends on !MACH_SUN8I_R40
547 depends on !MACH_SUN8I_V3S
548 depends on !MACH_SUN9I
549 depends on !MACH_SUN50I
552 Say Y here to add support for using a cfb console on the HDMI, LCD
553 or VGA output found on most sunxi devices. See doc/README.video for
554 info on how to select the video output and mode.
557 bool "HDMI output support"
558 depends on VIDEO && !MACH_SUN8I
561 Say Y here to add support for outputting video over HDMI.
564 bool "VGA output support"
565 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
568 Say Y here to add support for outputting video over VGA.
570 config VIDEO_VGA_VIA_LCD
571 bool "VGA via LCD controller support"
572 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
575 Say Y here to add support for external DACs connected to the parallel
576 LCD interface driving a VGA connector, such as found on the
579 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
580 bool "Force sync active high for VGA via LCD controller support"
581 depends on VIDEO_VGA_VIA_LCD
584 Say Y here if you've a board which uses opendrain drivers for the vga
585 hsync and vsync signals. Opendrain drivers cannot generate steep enough
586 positive edges for a stable video output, so on boards with opendrain
587 drivers the sync signals must always be active high.
589 config VIDEO_VGA_EXTERNAL_DAC_EN
590 string "LCD panel power enable pin"
591 depends on VIDEO_VGA_VIA_LCD
594 Set the enable pin for the external VGA DAC. This takes a string in the
595 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
597 config VIDEO_COMPOSITE
598 bool "Composite video output support"
599 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
602 Say Y here to add support for outputting composite video.
604 config VIDEO_LCD_MODE
605 string "LCD panel timing details"
609 LCD panel timing details string, leave empty if there is no LCD panel.
610 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
611 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
612 Also see: http://linux-sunxi.org/LCD
614 config VIDEO_LCD_DCLK_PHASE
615 int "LCD panel display clock phase"
619 Select LCD panel display clock phase shift, range 0-3.
621 config VIDEO_LCD_POWER
622 string "LCD panel power enable pin"
626 Set the power enable pin for the LCD panel. This takes a string in the
627 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
629 config VIDEO_LCD_RESET
630 string "LCD panel reset pin"
634 Set the reset pin for the LCD panel. This takes a string in the format
635 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
637 config VIDEO_LCD_BL_EN
638 string "LCD panel backlight enable pin"
642 Set the backlight enable pin for the LCD panel. This takes a string in the
643 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
646 config VIDEO_LCD_BL_PWM
647 string "LCD panel backlight pwm pin"
651 Set the backlight pwm pin for the LCD panel. This takes a string in the
652 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
654 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
655 bool "LCD panel backlight pwm is inverted"
659 Set this if the backlight pwm output is active low.
661 config VIDEO_LCD_PANEL_I2C
662 bool "LCD panel needs to be configured via i2c"
667 Say y here if the LCD panel needs to be configured via i2c. This
668 will add a bitbang i2c controller using gpios to talk to the LCD.
670 config VIDEO_LCD_PANEL_I2C_SDA
671 string "LCD panel i2c interface SDA pin"
672 depends on VIDEO_LCD_PANEL_I2C
675 Set the SDA pin for the LCD i2c interface. This takes a string in the
676 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
678 config VIDEO_LCD_PANEL_I2C_SCL
679 string "LCD panel i2c interface SCL pin"
680 depends on VIDEO_LCD_PANEL_I2C
683 Set the SCL pin for the LCD i2c interface. This takes a string in the
684 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
687 # Note only one of these may be selected at a time! But hidden choices are
688 # not supported by Kconfig
689 config VIDEO_LCD_IF_PARALLEL
692 config VIDEO_LCD_IF_LVDS
700 bool "Display Engine 2 video driver"
706 Say y here if you want to build DE2 video driver which is present on
707 newer SoCs. Currently only HDMI output is supported.
711 prompt "LCD panel support"
714 Select which type of LCD panel to support.
716 config VIDEO_LCD_PANEL_PARALLEL
717 bool "Generic parallel interface LCD panel"
718 select VIDEO_LCD_IF_PARALLEL
720 config VIDEO_LCD_PANEL_LVDS
721 bool "Generic lvds interface LCD panel"
722 select VIDEO_LCD_IF_LVDS
724 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
725 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
726 select VIDEO_LCD_SSD2828
727 select VIDEO_LCD_IF_PARALLEL
729 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
731 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
732 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
733 select VIDEO_LCD_ANX9804
734 select VIDEO_LCD_IF_PARALLEL
735 select VIDEO_LCD_PANEL_I2C
737 Select this for eDP LCD panels with 4 lanes running at 1.62G,
738 connected via an ANX9804 bridge chip.
740 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
741 bool "Hitachi tx18d42vm LCD panel"
742 select VIDEO_LCD_HITACHI_TX18D42VM
743 select VIDEO_LCD_IF_LVDS
745 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
747 config VIDEO_LCD_TL059WV5C0
748 bool "tl059wv5c0 LCD panel"
749 select VIDEO_LCD_PANEL_I2C
750 select VIDEO_LCD_IF_PARALLEL
752 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
753 Aigo M60/M608/M606 tablets.
758 string "SATA power pin"
761 Set the pins used to power the SATA. This takes a string in the
762 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
766 int "GMAC Transmit Clock Delay Chain"
769 Set the GMAC Transmit Clock Delay Chain value.
771 config SPL_STACK_R_ADDR
772 default 0x4fe00000 if MACH_SUN4I
773 default 0x4fe00000 if MACH_SUN5I
774 default 0x4fe00000 if MACH_SUN6I
775 default 0x4fe00000 if MACH_SUN7I
776 default 0x4fe00000 if MACH_SUN8I
777 default 0x2fe00000 if MACH_SUN9I
778 default 0x4fe00000 if MACH_SUN50I